# -*- Mode:Python -*-
import Cfg
+from Hurricane import DataBase, Cell, Instance, Net
+from CRL import AllianceFramework, RoutingLayerGauge
import CRL
import Viewer
from helpers.overlay import CfgCache
+from helpers import overlay, l, u, n
import symbolic.cmos45 # do not remove
import os
else:
cellsTop = '../../../alliance-check-toolkit/cells'
+db = DataBase.getDB()
+af = AllianceFramework.get()
+
+
+def createSramBlackbox ():
+ global db, af
+ print( ' o Creating SRAM blackboxes for "ls180" design.' )
+ rootlib = db.getRootLibrary()
+ lib = rootlib.getLibrary( 'LibreSOCMem' )
+ sramName = 'spblock_512w64b8w'
+ sram = lib.getCell( sramName )
+ if not sram:
+ raise ErrorMessage( 1, 'settings.createSramBlocks(): '
+ 'SRAM Cell "{}" not found.' \
+ .format(sramName) )
+ sram.setAbstractedSupply( True )
+ blackboxeNames = [ 'spblock_512w64b8w'
+ ]
+ for blackboxName in blackboxeNames:
+ cell = Cell.create( lib, blackboxName )
+ instance = Instance.create( cell, 'real_sram', sram )
+ state = af.getCatalog().getState( blackboxName, True )
+ state.setCell( cell )
+ state.setLogical( True )
+ state.setInMemory( True )
+ print( ' - {}.'.format(cell) )
+ for masterNet in sram.getNets():
+ if not masterNet.isExternal():
+ continue
+ net = Net.create( cell, masterNet.getName() )
+ net.setDirection( masterNet.getDirection() )
+ net.setType( masterNet.getType() )
+ net.setExternal( True )
+ net.setGlobal( masterNet.isGlobal() )
+ if masterNet.isSupply():
+ continue
+ plug = instance.getPlug( masterNet )
+ plug.setNet( net )
+
+
with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg:
cfg.misc.catchCore = False
cfg.misc.info = False
Viewer.Graphics.setStyle('Alliance.Classic [black]')
+# XXX cannot run this in non-NDA'd mode because there is no
+# equivalent to NDA.node180.tsmc_c018.LibreSOCMem (or PLL)
+# TODO: create a fake one
+#with overlay.UpdateSession():
+# createSramBlackbox()
+
print( ' o Successfully run "<>/coriolis2/settings.py".' )
print( ' - CELLS_TOP = "{}"'.format(cellsTop) )
+
'SRAM Cell "{}" not found.' \
.format(sramName) )
sram.setAbstractedSupply( True )
- blackboxeNames = [ 'spblock512w64b8w_0'
- , 'spblock512w64b8w_1'
- , 'spblock512w64b8w_2'
- , 'spblock512w64b8w_3'
+ blackboxeNames = [ 'spblock_512w64b8w'
]
for blackboxName in blackboxeNames:
cell = Cell.create( lib, blackboxName )
env = af.getEnvironment()
env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
+# XXX cannot run this in non-NDA'd mode because there is no
+# NDA.node45.freepdk45_c4m.LibreSOCMem (or PLL)
+# TODO: create a fake one
with overlay.UpdateSession():
createSramBlackbox()
assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb;
always @(posedge clk)
sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
- spblock_512w64b8w spblock512w64b8w_0 (
+ spblock_512w64b8w spblock_512w64b8w (
.a(a),
.clk(clk),
.d(d),
assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb;
always @(posedge clk)
sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
- spblock_512w64b8w spblock512w64b8w_1 (
+ spblock_512w64b8w spblock_512w64b8w (
.a(a),
.clk(clk),
.d(d),
assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb;
always @(posedge clk)
sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
- spblock_512w64b8w spblock512w64b8w_2 (
+ spblock_512w64b8w spblock_512w64b8w (
.a(a),
.clk(clk),
.d(d),
assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb;
always @(posedge clk)
sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
- spblock_512w64b8w spblock512w64b8w_3 (
+ spblock_512w64b8w spblock_512w64b8w (
.a(a),
.clk(clk),
.d(d),
+++ /dev/null
-<* blackbox = 1 *)
-module spblock_512w64b8w(a, d, q, we, clk);
- input [8:0] a;
- input [63:0] d;
- output [63:0] q;
- input [7:0] we;
- input clk;
-endmodule // SPBlock_512W64B8W
-
+++ /dev/null
--- Phony VHDL interface for SRAM block.
-
-entity spblock512w64b8w is
- port ( clk : in bit
- ; we : in bit_vector( 7 downto 0)
- ; a : in bit_vector( 8 downto 0)
- ; d : in bit_vector(63 downto 0)
- ; q : out bit_vector(63 downto 0)
- ; vdd : in bit
- ; vss : in bit
- );
-end spblock512w64b8w;
-
-architecture behavioral of spblock512w64b8w is
-
-begin
-
-end behavioral;
--- /dev/null
+<* blackbox = 1 *)
+module spblock_512w64b8w(a, d, q, we, clk);
+ input [8:0] a;
+ input [63:0] d;
+ output [63:0] q;
+ input [7:0] we;
+ input clk;
+endmodule // SPBlock_512W64B8W
+
--- /dev/null
+-- Phony VHDL interface for SRAM block.
+
+entity spblock_512w64b8w is
+ port ( clk : in bit
+ ; we : in bit_vector( 7 downto 0)
+ ; a : in bit_vector( 8 downto 0)
+ ; d : in bit_vector(63 downto 0)
+ ; q : out bit_vector(63 downto 0)
+ ; vdd : in bit
+ ; vss : in bit
+ );
+end spblock_512w64b8w;
+
+architecture behavioral of spblock_512w64b8w is
+
+begin
+
+end behavioral;
raise ErrorMessage( 1, 'settings.createSramBlocks(): SRAM Cell "{}" not found.' \
.format(sramName) )
sram.setAbstractedSupply( True )
- blackboxeNames = [ 'spblock512w64b8w_0'
- , 'spblock512w64b8w_1'
- , 'spblock512w64b8w_2'
- , 'spblock512w64b8w_3'
+ blackboxeNames = [ 'spblock_512w64b8w' # go back to only one blackbox
]
for blackboxName in blackboxeNames:
cell = Cell.create( lib, blackboxName )
projects / soclayout.git / commitdiff