whitespace update

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index f9df4e563ccd9dc1ca1fa6239e75f609f0679b66..0b34a2978b74961cc812c84053df7c3901b13153 100644 (file)
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -26,8 +26,8 @@ class CoreBaseData(ALUInputData):
         self.dividend_neg = Signal(reset_less=True)
         self.div_by_zero = Signal(reset_less=True)
 
-        # set if an overflow for divide extended instructions is detected because
-        # `abs_dividend >= abs_divisor` for the appropriate bit width;
+        # set if an overflow for divide extended instructions is detected
+        # because `abs_dividend >= abs_divisor` for the appropriate bit width;
         # 0 if the instruction is not a divide extended instruction
         self.dive_abs_overflow_32 = Signal(reset_less=True)
         self.dive_abs_overflow_64 = Signal(reset_less=True)

diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py
index fb510ff04394b8212414111b94cbd19db2fb706b..c503f14b4c374ff736891cef7ba71b6b18978639 100644 (file)
--- a/src/soc/fu/div/pipeline.py
+++ b/src/soc/fu/div/pipeline.py
@@ -3,7 +3,8 @@ from nmutil.pipemodbase import PipeModBaseChain
 from soc.fu.alu.input_stage import ALUInputStage
 from soc.fu.alu.output_stage import ALUOutputStage
 from soc.fu.div.setup_stage import DivSetupStage
-from soc.fu.div.core_stages import DivCoreSetupStage, DivCoreCalculateStage, DivCoreFinalStage
+from soc.fu.div.core_stages import (DivCoreSetupStage, DivCoreCalculateStage,
+                                    DivCoreFinalStage)
 from soc.fu.div.output_stage import DivOutputStage