self.sticky = Signal(reset_less=True) # tot[0]
self.m0 = Signal(reset_less=True) # mantissa zero bit
- self.roundz = Signal(reset_less=True)
+ #self.roundz = Signal(reset_less=True)
def __iter__(self):
yield self.guard
self.sticky.eq(inp.sticky),
self.m0.eq(inp.m0)]
- def elaborate(self, platform):
- m = Module()
- m.d.comb += self.roundz.eq(self.guard & \
- (self.round_bit | self.sticky | self.m0))
- return m
+ @property
+ def roundz(self):
+ return self.guard & (self.round_bit | self.sticky | self.m0)
class FPBase:
m.d.comb += self.o.roundz.eq(of.roundz)
#m.submodules.norm1_out_z = self.o.z
- m.submodules.norm1_out_overflow = of
+ #m.submodules.norm1_out_overflow = of
#m.submodules.norm1_in_z = self.i.z
- m.submodules.norm1_in_overflow = self.i.of
+ #m.submodules.norm1_in_overflow = self.i.of
i = self.ispec()
m.submodules.norm1_insel_z = insel_z = FPNumBase(i.z)
- m.submodules.norm1_insel_overflow = i.of
+ #m.submodules.norm1_insel_overflow = i.of
espec = (len(insel_z.e), True)
ediff_n126 = Signal(espec, reset_less=True)