experiment with Object class

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 753dec1b6f9ea85084c47bbc62323e979ac96666..9b65f0906a7c0496d452758eaf45076518d96c68 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -175,13 +175,14 @@ from nmigen.hdl.ast import ArrayProxy
 from nmigen.hdl.rec import Record, Layout
 
 from abc import ABCMeta, abstractmethod
-from collections.abc import Sequence
+from collections.abc import Sequence, Iterable
+from collections import OrderedDict
 from queue import Queue
 
 
 class Object:
     def __init__(self):
-        self.fields = {}
+        self.fields = OrderedDict()
 
     def __setattr__(self, k, v):
         print ("kv", k, v)
@@ -191,18 +192,31 @@ class Object:
         self.fields[k] = v
 
     def __getattr__(self, k):
-        if k in self.fields:
+        if k in self.__dict__:
+            return object.__getattr__(self, k)
+        try:
             return self.fields[k]
-        return object.__getattr__(self, k)
+        except KeyError as e:
+            raise AttributeError(e)
 
     def __iter__(self):
         for x in self.fields.values():
-            yield x
+            if isinstance(x, Iterable):
+                yield from x
+            else:
+                yield x
 
     def eq(self, inp):
         res = []
-        for (o, i) in zip(self, inp):
-            res.append(eq(o, i))
+        for (k, o) in self.fields.items():
+            i = getattr(inp, k)
+            print ("eq", o, i)
+            rres = o.eq(i)
+            if isinstance(rres, Sequence):
+                res += rres
+            else:
+                res.append(rres)
+        print (res)
         return res
 
     def ports(self):
@@ -230,7 +244,10 @@ class RecordObject(Record):
 
     def __iter__(self):
         for x in self.fields.values():
-            yield x
+            if isinstance(x, Iterable):
+                yield from x
+            else:
+                yield x
 
     def ports(self):
         return list(self)

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index d184e1760fd2c8c2b03b80dce60b098d9fefa584..8861f281d5e4cea7800bf91225ca7b9c9b6c7ec5 100644 (file)
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -13,7 +13,7 @@ from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMultiOutPipeline, CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
-from singlepipe import SimpleHandshake, RecordObject
+from singlepipe import SimpleHandshake, RecordObject, Object
 
 
 class PassData2(RecordObject):
@@ -24,29 +24,13 @@ class PassData2(RecordObject):
         self.data = Signal(16, reset_less=True)
 
 
-class PassData:
+class PassData(Object):
     def __init__(self):
+        Object.__init__(self)
         self.mid = Signal(2, reset_less=True)
         self.idx = Signal(8, reset_less=True)
         self.data = Signal(16, reset_less=True)
 
-    def __iter__(self):
-        yield self.mid
-        yield self.idx
-        yield self.data
-
-    def shape(self):
-        bits, sign = 0, False
-        for elem_bits, elem_sign in (elem.shape() for elem in self.ports()):
-            bits = max(bits, elem_bits + elem_sign)
-            sign = max(sign, elem_sign)
-        return bits, sign
-
-    def eq(self, i):
-        return [self.mid.eq(i.mid), self.idx.eq(i.idx), self.data.eq(i.data)]
-
-    def ports(self):
-        return list(self)
 
 
 class PassThroughStage: