typo fix in test_l0_cache_buffer2.py

diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py
index ba2a81703502b74e18943e4452c17ae6df0ca627..f23536e9be3e0474bb56c28073200c50682a526f 100644 (file)
--- a/src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/src/soc/experiment/test/test_l0_cache_buffer2.py
@@ -35,7 +35,7 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
         #m.d.comb += self..eq(msbaddr)
 
     def set_wr_data(self, m, data, wen):
-        m.d.comb += self.ldst.st_data_i.eq(data)  # write st to mem
+        m.d.comb += self.ldst.st_data_i.data.eq(data)  # write st to mem
         m.d.comb += self.ldst.is_st_i.eq(wen)  # enable writes
         return Const(1, 1) #fixme -- write may be longer than one cycle