add rlwinm. test instruction (sets CR0)

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 8b942fcfc08e5869bc7e481166272209444ddecf..2a4ad4b77ec1841ba8a1e91bab71d9d98fbd1076 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -129,7 +129,8 @@ class ShiftRotTestCase(FHDLTestCase):
             mb = random.randint(0,31)
             me = random.randint(0,31)
             sh = random.randint(0,31)
-            lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}"]
+            lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}",
+                   f"rlwinm. 3, 1, {mb}, {me}, {sh}"]
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)