add comment about fast1 and fast2 in branch test_pipe_caller

diff --git a/libreriscv b/libreriscv
index 6b08375a1f5a0f3575fe86f7379506da4c4d9b90..041f868b620685068f375bce39c3aacf6aa986c4 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 6b08375a1f5a0f3575fe86f7379506da4c4d9b90
+Subproject commit 041f868b620685068f375bce39c3aacf6aa986c4

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 0028fb4146a6122c8c90e250dc24cc5d06d3adb0..dddfc4d14526c2a9721e7a6c4d4e9c35c4887098 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -215,6 +215,8 @@ class TestRunner(FHDLTestCase):
         yield branch.p.data_i.spr1.eq(sim.spr['CTR'].value)
         print(f"cr0: {sim.crl[0].get_range()}")
 
+        # TODO: this needs to now be read_fast1.data and read_fast2.data
+
         spr2_en = yield dec2.e.read_spr2.ok
         if spr2_en:
             spr2_sel = yield dec2.e.read_spr2.data