comment mmu test

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 85958d54651b3ea69d9f5d3e31d22738f94f4828..a8c514f7d6e1816a132a804369ebd24596cfeee2 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -577,8 +577,9 @@ def mmu_wait(dut):
             l_permerr or l_rc_err or l_segerr or l_invalid):
             break
         yield
-        yield dut.l_in.valid.eq(0)
-        yield dut.l_in.mtspr.eq(0)
+        yield dut.l_in.valid.eq(0) # data already in MMU by now
+        yield dut.l_in.mtspr.eq(0) # captured by RegStage(s)
+        yield dut.l_in.load.eq(0)  # can reset everything safely
 
 def mmu_sim(dut):
     global stop
@@ -598,7 +599,7 @@ def mmu_sim(dut):
     print ("prtbl after MTSPR %x" % prtbl)
     assert prtbl == 0x1000000
 
-    #yield dut.rin.prtbl.eq(0x1000000) # set process table
+    #yield dut.rin.prtbl.eq(0x1000000) # manually set process table
     #yield