"twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
str(dut.iocell_side_io2_cell_out))
- # Test for in
- # first check for tristate
- if str(dut.peripheral_side_twi_scl_in) != "x":
- raise TestFailure(
- "twi_scl=0/mux=0/out=1 %s twi_scl_in != x" %
- str(dut.peripheral_side_twi_scl_in))
+ dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
+ # Test for in
dut.peripheral_side_twi_scl_outen_in = 0
dut.iocell_side_io2_cell_in_in = 0
yield Timer(2)
"twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
str(dut.iocell_side_io1_cell_out))
- # Test for in
- # first check for tristate
- if str(dut.peripheral_side_twi_sda_in) != "x":
- raise TestFailure(
- "twi_sda=0/mux=0/out=1 %s twi_sda_in != x" %
- str(dut.peripheral_side_twi_sda_in))
+ dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
+ # Test for in
dut.peripheral_side_twi_sda_outen_in = 0
dut.iocell_side_io1_cell_in_in = 0
yield Timer(2)
if dut.peripheral_side_twi_sda_in != 1:
raise TestFailure(
- "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
+ "iocell_io1=1/mux=0/out=0 %s twi_sda != 1" %
str(dut.peripheral_side_twi_sda_in))
dut.peripheral_side_twi_sda_outen_in = 1