convert wb test to async

diff --git a/ls180/pre_pnr/run_iverilog_wb_ls180.sh b/ls180/pre_pnr/run_iverilog_wb_ls180.sh
index db24552ae4f6bc43dba4ee2c69f18096d26b774b..6b4bd266ef836539aedf7c3edfaa2e3b1f4d01ab 100755 (executable)
--- a/ls180/pre_pnr/run_iverilog_wb_ls180.sh
+++ b/ls180/pre_pnr/run_iverilog_wb_ls180.sh
@@ -10,7 +10,7 @@ make \
   SIM=icarus \
   TOPLEVEL=ls180 \
   COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \
-  COCOTB_HDL_TIMEUNIT=100ps \
+  COCOTB_HDL_TIMEUNIT=10ps \
   TESTCASE="wishbone_basic" \
   MODULE="testwb" \
   SIM_BUILD=sim_build_iverilog_wb_ls180

diff --git a/ls180/pre_pnr/testwb.py b/ls180/pre_pnr/testwb.py
index 9a20ae9667276ed3b553e8b4318c214d2ca1df7d..6e19eaa08382c9b1432d98d041fa1730af215399 100644 (file)
--- a/ls180/pre_pnr/testwb.py
+++ b/ls180/pre_pnr/testwb.py
@@ -2,7 +2,7 @@ from itertools import chain
 
 import cocotb
 from cocotb.clock import Clock
-from cocotb.triggers import Timer
+from cocotb.triggers import Timer, RisingEdge
 from cocotb.utils import get_sim_steps
 from cocotb.binary import BinaryValue
 
@@ -26,16 +26,18 @@ class DUTWrapper:
         except AttributeError:
             ls180 = dut
         ls180._discover_all()
+        self.ls180 = ls180
+        self.clk = dut.sys_clk
+        self.rst = dut.sys_rst
+        self.tck = dut.jtag_tck
+        self.tms = dut.jtag_tms
+        self.tdi = dut.jtag_tdi
+        self.tdo = dut.jtag_tdo
+
+        return
         ls180.test_issuer._discover_all()
         ls180.test_issuer.ti._discover_all()
         ls180.test_issuer.ti.dbg._discover_all()
-        self.ls180 = ls180
-        self.clk = ls180.sys_clk
-        self.rst = ls180.sys_rst
-        self.tck = ls180.jtag_tck
-        self.tms = ls180.jtag_tms
-        self.tdi = ls180.jtag_tdi
-        self.tdo = ls180.jtag_tdo
 
     def info(self, *args, **kwargs):
         return self.dut._log.info(*args, **kwargs)
@@ -132,7 +134,7 @@ def get_jtag_boundary():
     return pins
 
 
-def setup_sim(dut, *, info, clk_period, run):
+async def setup_sim(dut, *, info, clk_period, run):
     """Initialize CPU and setup clock"""
 
     wrap = DUTWrapper(dut)
@@ -144,10 +146,14 @@ def setup_sim(dut, *, info, clk_period, run):
     clk_steps = get_sim_steps(clk_period, "ns")
     cocotb.fork(Clock(wrap.clk, clk_steps).start())
 
+
     if run:
-        yield Timer(int(1.5*clk_steps))
+        for _ in range(2):
+            await RisingEdge(wrap.clk)
         wrap.rst <= 0
-        #yield Timer(int(3*clk_steps))
+        for _ in range(1):
+            await RisingEdge(wrap.clk)
+        #await Timer(int(3*clk_steps))
 
     return wrap
 
@@ -155,30 +161,30 @@ def setup_sim(dut, *, info, clk_period, run):
 def setup_jtag(wrap, *, tck_period):
     # TODO: Make this a generator
     if False:
-        yield Timer(0)
+        await Timer(0)
     return JTAG_Master(wrap.tck, wrap.tms, wrap.tdi, wrap.tdo,
                        clk_period=tck_period,
                        ir_width=4)
 
-def execute_svf(wrap, *, jtag, svf_filename):
-    yield jtag.reset()
+async def execute_svf(wrap, *, jtag, svf_filename):
+    await jtag.reset()
 
     jtag_svf = SVF_Executor(jtag)
     with open(svf_filename, "r") as f:
         svf_deck = f.read()
-    yield jtag_svf.run(svf_deck, p=wrap.info)
+    await jtag_svf.run(svf_deck, p=wrap.info)
 
 #
 # IDCODE using JTAG_master
 #
 
-def idcode(wrap, *, jtag):
-    yield jtag.idcode()
+async def idcode(wrap, *, jtag):
+    await jtag.idcode()
     result1 = jtag.result
     wrap.info("IDCODE1: {}".format(result1))
     assert(result1 == BinaryValue("00000000000000000001100011111111"))
 
-    yield jtag.idcode()
+    await jtag.idcode()
     result2 = jtag.result
     wrap.info("IDCODE2: {}".format(result2))
 
@@ -186,31 +192,31 @@ def idcode(wrap, *, jtag):
 
 
 @cocotb.test()
-def idcode_reset(dut):
+async def idcode_reset(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE test; cpu in reset..."
-    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
                                 run=False)
-    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
+    jtag = await setup_jtag(wrap, tck_period = tck_period)
 
-    yield from idcode(wrap, jtag=jtag)
+    await idcode(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-def idcode_run(dut):
+async def idcode_run(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE test; cpu running..."
-    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
                          run=True)
-    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
+    jtag = await setup_jtag(wrap, tck_period = tck_period)
 
-    yield from idcode(wrap, jtag=jtag)
+    await idcode(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
@@ -219,31 +225,31 @@ def idcode_run(dut):
 #
 
 @cocotb.test()
-def idcodesvf_reset(dut):
+async def idcodesvf_reset(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE through SVF test; cpu in reset..."
-    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
                                 run=False)
-    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
+    jtag = await setup_jtag(wrap, tck_period = tck_period)
 
-    yield from execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
+    await execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-def idcodesvf_run(dut):
+async def idcodesvf_run(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running IDCODE through SVF test; cpu running..."
-    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
                                 run=True)
-    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
+    jtag = await setup_jtag(wrap, tck_period = tck_period)
 
-    yield from execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
+    await execute_svf(wrap, jtag=jtag, svf_filename="idcode.svf")
 
     wrap.info("IDCODE test completed")
 
@@ -251,19 +257,19 @@ def idcodesvf_run(dut):
 # Boundary scan
 #
 
-def boundary_scan(wrap, *, jtag):
+async def boundary_scan(wrap, *, jtag):
     pins = get_jtag_boundary()
 
-    yield jtag.reset()
+    await jtag.reset()
 
     wrap.info("")
     wrap.info("Before scan")
     log_pins(wrap, pins)
 
-    yield jtag.load_ir([0, 0, 0, 0])
+    await jtag.load_ir([0, 0, 0, 0])
     pinsdata = tuple(pin.data(i=i%2, o=((i%3)%2), oe=((i%5)%2))
                      for i, pin in enumerate(pins))
-    yield jtag.shift_data(chain(*pinsdata))
+    await jtag.shift_data(chain(*pinsdata))
 
     wrap.info("")
     wrap.info("After scan")
@@ -271,7 +277,7 @@ def boundary_scan(wrap, *, jtag):
     for i, pin in enumerate(pins):
         pin.check(wrap=wrap, i=i%2, o=((i%3)%2), oe=((i%5)%2))
 
-    yield jtag.reset()
+    await jtag.reset()
 
     wrap.info("")
     wrap.info("After reset")
@@ -279,37 +285,37 @@ def boundary_scan(wrap, *, jtag):
 
 
 @cocotb.test()
-def boundary_scan_reset(dut):
+async def boundary_scan_reset(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running boundary scan test; cpu in reset..."
-    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
                                 run=False)
-    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
+    jtag = await setup_jtag(wrap, tck_period = tck_period)
 
-    yield from boundary_scan(wrap, jtag=jtag)
+    await boundary_scan(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-def boundary_scan_run(dut):
+async def boundary_scan_run(dut):
     clk_period = 100 # 10MHz
     tck_period = 300 # 3MHz
 
     info = "Running boundary scan test; cpu running..."
-    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
+    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
                                 run=True)
-    jtag = yield from setup_jtag(wrap, tck_period = tck_period)
+    jtag = await setup_jtag(wrap, tck_period = tck_period)
 
-    yield from boundary_scan(wrap, jtag=jtag)
+    await boundary_scan(wrap, jtag=jtag)
 
     wrap.info("IDCODE test completed")
 
 
 @cocotb.test()
-def wishbone_basic(dut):
+async def wishbone_basic(dut):
     """
     Test of an added Wishbone interface
     """
@@ -323,122 +329,119 @@ def wishbone_basic(dut):
     cmd_MEMREADWRITE = BinaryValue("0111")  # 7
 
     info = "Running Wishbone basic test"
-    wrap = yield from setup_sim(dut, info=info, clk_period=clk_period,
-                                run=False)
-    master = yield from setup_jtag(wrap, tck_period = tck_period)
-
-    wrap.dut.ls180.test_issuer.ti.dbg.core_stopped_i <= 1
+    wrap = await setup_sim(dut, info=info, clk_period=clk_period,
+                                run=True)
+    master = await setup_jtag(wrap, tck_period = tck_period)
 
-    clk_steps = get_sim_steps(clk_period, "ns")
-    yield Timer(int(4.5*clk_steps))
-    wrap.rst <= 0
 
-    #yield master.reset()
+    #clk_steps = get_sim_steps(clk_period, "ns")
+    #await Timer(int(4.5*clk_steps))
+    #wrap.rst <= 0
 
-    yield Timer(int(10.5*clk_steps))
+    #await master.reset()
 
-    return
+    #await Timer(int(10.5*clk_steps))
 
     #wrap.rst <= 0
 
     # Load the memory address
-    yield master.load_ir(cmd_MEMADDRESS)
+    await master.load_ir(cmd_MEMADDRESS)
     dut._log.info("Loading address")
 
-    data_in.binstr = "00000000000000000000000000001"
+    data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
     # Do write
-    yield master.load_ir(cmd_MEMREADWRITE)
+    await master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Writing memory")
 
-    data_in.binstr = "01010101" * 8
+    data_in.binstr = "01010101" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
-    data_in.binstr = "10101010" * 8
+    data_in.binstr = "10101010" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
 
     # Load the memory address
-    yield master.load_ir(cmd_MEMADDRESS)
+    await master.load_ir(cmd_MEMADDRESS)
     dut._log.info("Loading address")
 
-    data_in.binstr = "00000000000000000000000000001"
+    data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "00000000000000000000000000000"
+    assert master.result.binstr == "000000000000000000000000000000"
 
     # Do read and write
-    yield master.load_ir(cmd_MEMREADWRITE)
+    await master.load_ir(cmd_MEMREADWRITE)
     dut._log.info("Reading and writing memory")
 
-    data_in.binstr = "10101010" * 8
+    data_in.binstr = "10101010" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "01010101" * 8
+    assert master.result.binstr == "01010101" * 4
 
-    data_in.binstr = "01010101" * 8
+    data_in.binstr = "01010101" * 4
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "10101010" * 8
+    assert master.result.binstr == "10101010" * 4
 
     # Load the memory address
-    yield master.load_ir(cmd_MEMADDRESS)
+    await master.load_ir(cmd_MEMADDRESS)
     dut._log.info("Loading address")
 
-    data_in.binstr = "00000000000000000000000000001"
+    data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "00000000000000000000000000010"
 
     # Do read
-    yield master.load_ir(cmd_MEMREAD)
+    await master.load_ir(cmd_MEMREAD)
     dut._log.info("Reading memory")
-    data_in.binstr = "00000000" * 8
+    data_in.binstr = "00000000" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "10101010" * 8
+    assert master.result.binstr == "10101010" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "01010101" * 8
+    assert master.result.binstr == "01010101" * 4
 
     # Load the memory address
-    yield master.load_ir(cmd_MEMADDRESS) # MEMADDR
+    await master.load_ir(cmd_MEMADDRESS) # MEMADDR
     dut._log.info("Loading address")
 
-    data_in.binstr = "00000000000000000000000000001"
+    data_in.binstr = "000000000000000000000000000001"
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
     assert master.result.binstr == "00000000000000000000000000010"
 
     # Do read
-    yield master.load_ir(cmd_MEMREAD) # MEMREAD
+    await master.load_ir(cmd_MEMREAD) # MEMREAD
     dut._log.info("Reading memory")
-    data_in.binstr = "00000000" * 8
+    data_in.binstr = "00000000" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "10101010" * 8
+    assert master.result.binstr == "10101010" * 4
 
     dut._log.info("  input: {}".format(data_in.binstr))
-    yield master.shift_data(data_in)
+    await master.shift_data(data_in)
     dut._log.info("  output: {}".format(master.result.binstr))
-    assert master.result.binstr == "01010101" * 8
+    assert master.result.binstr == "01010101" * 4
 
     dut._log.info("{!r}".format(wbmem))