return instances() # return all instances
+
@block
def pmux1(clk, in_a,
sel_a, out):
@block
-def pmux4(clk, in_a, in_b, in_c, in_d,
- sel_a, sel_b, sel_c, sel_d, out):
+def pmux4(clk, ins, sels, out):
+
+ (sel_a, sel_b, sel_c, sel_d) = sels
+ (in_a, in_b, in_c, in_d) = ins
@always(sel_a, sel_b, sel_c, sel_d,
in_a, in_b, in_c, in_d)
sel_d = Signal(bool(0))
out = Signal(bool(0))
- mux_inst = pmux4(clk, in_a, in_b, in_c, in_d,
- sel_a, sel_b, sel_c, sel_d, out)
+ sels = (sel_a, sel_b, sel_c, sel_d)
+ ins = (in_a, in_b, in_c, in_d)
+ mux_inst = pmux4(clk, ins, sels, out)
@instance
def clk_signal():
file_data = open("pmux.csv", 'w') # file for saving data
# # print header on screen
s = "{0},{1},{2},{3},{4},{5},{6},{7},{8}".format(
- "in_a", "in_b", "in_c", "in_d",
- "sel_a", "sel_b", "sel_c", "sel_d",
- "out")
+ "in_a", "in_b", "in_c", "in_d",
+ "sel_a", "sel_b", "sel_c", "sel_d",
+ "out")
print(s)
# # print header to file
file_data.write(s)
return instances()
# testbench
+
+
@block
def mux_tb():
sel_d = Signal(bool(0))
out = Signal(bool(0))
- pmux_v = pmux4(clk, in_a, in_b, in_c, in_d,
- sel_a, sel_b, sel_c, sel_d, out)
+ sels = (sel_a, sel_b, sel_c, sel_d)
+ ins = (in_a, in_b, in_c, in_d)
+ pmux_v = pmux4(clk, ins, sels, out)
pmux_v.convert(hdl="Verilog", initial_values=True)
# test bench
# keep following lines below the 'tb.convert' line
# otherwise error will be reported
tb.config_sim(trace=True)
- tb.run_sim(4*66 * period) # run for 15 clock cycle
+ tb.run_sim(4 * 66 * period) # run for 15 clock cycle
if __name__ == '__main__':
- #test_mux()
+ # test_mux()
print "test pmux"
test_pmux4()