attempt 32-bit width to see if doAlu16Flat.py can cope (it cant)

diff --git a/experiments7/doAlu16.py b/experiments7/doAlu16.py
index 30383bd5e807a9829a7caf308cb4ab3e3aeab690..d9c2a97c6d1c894f0d256dc1f7d945750de0631c 100755 (executable)
--- a/experiments7/doAlu16.py
+++ b/experiments7/doAlu16.py
@@ -16,7 +16,7 @@ from utils import Module, SessionManager, Config
 import symbolic.cmos  # do not remove
 
 BIT_WIDTH = 16
-
+widths = {32: 600.0, 16: 490}
 
 def coriolis_setup():
     with Config(Cfg.Parameter.Priority.UserFile) as cfg:
@@ -169,7 +169,7 @@ class ALU16(Module):
             ])) + v_margin
 
             # experiment, over-ride
-            width = 490
+            width = widths[BIT_WIDTH]
             #width = 1310
             #height = 370
 
@@ -239,7 +239,7 @@ def scriptMain(editor=None, **kwargs):
         },
         orientation=Transformation.Orientation.ID,
     )
-    add.set_ab(160.0, 800.0)
+    add.set_ab(160.0, 50.0 * BIT_WIDTH)
     sub = AddSub(
         'sub', editor,
         west_pins=[
@@ -257,7 +257,7 @@ def scriptMain(editor=None, **kwargs):
         },
         orientation=Transformation.Orientation.ID,
     )
-    sub.set_ab(165.0, 800.0)
+    sub.set_ab(165.0, 50.0 * BIT_WIDTH)
 
     o = 00.0
     alu16 = ALU16(

diff --git a/experiments7/doAlu16Flat.py b/experiments7/doAlu16Flat.py
index e77220ea51d6322072e48d677855d1ec889c11c6..1538fb5a5038849eaa3a8c62f87f1e998643e625 100644 (file)
--- a/experiments7/doAlu16Flat.py
+++ b/experiments7/doAlu16Flat.py
@@ -16,7 +16,8 @@ from utils import Module, SessionManager, Config
 import symbolic.cmos  # do not remove
 
 BIT_WIDTH = 16
-
+widths = {16 : 465.0, 32: 800.0}
+offsets = {16 : 0.0, 32: 200.0}
 
 def coriolis_setup():
     with Config(Cfg.Parameter.Priority.UserFile) as cfg:
@@ -114,21 +115,22 @@ def scriptMain(editor=None, **kwargs):
         orientation=Transformation.Orientation.ID,
     )
 
+    o = offsets[BIT_WIDTH]
     alu16 = ALU16(
         'alu16', editor, submodules=[add, sub],
         north_pins=[
-            {'net': 'o({})', 'x': 365.0, 'delta': -5.0, 'repeat': BIT_WIDTH},
+            {'net': 'o({})', 'x': o+365.0, 'delta': -5.0, 'repeat': BIT_WIDTH},
             {'net': 'op'},
         ],
         south_pins=[
-            {'net': 'a({})', 'x': 205.0, 'delta': 5.0, 'repeat': BIT_WIDTH},
-            {'net': 'b({})', 'x': 295.0, 'delta': 5.0, 'repeat': BIT_WIDTH},
+            {'net': 'a({})', 'x': o+205.0, 'delta': 5.0, 'repeat': BIT_WIDTH},
+            {'net': 'b({})', 'x': o+295.0, 'delta': 5.0, 'repeat': BIT_WIDTH},
         ],
         west_pins=[
             {'net': 'rst', 'y': 10.0, 'layer': 'METAL2'},
         ],
     )
-    alu16.set_ab( 465, 800 )
+    alu16.set_ab( widths[BIT_WIDTH], BIT_WIDTH * 50.0 )
     return alu16.build()