Allow zero_a to be set when simulating an operation

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index db8ece4341905a4dc05f4a690fb20e8b4ae94054..23652c4538f21a71e2cdefa3d15410b319a23fb3 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -336,7 +336,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         return list(self)
 
 
-def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
+def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
     yield dut.issue_i.eq(0)
     yield
     yield dut.src_i[0].eq(a)
@@ -345,6 +345,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
     yield dut.oper_i.invert_a.eq(inv_a)
     yield dut.oper_i.imm_data.imm.eq(imm)
     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
+    yield dut.oper_i.zero_a.eq(zero_a)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)