update ls180 litex interfaces

diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il
index a3e07c1e66be158c328c75f332996247093e6c7a..ab4601ee31d9c9c4cb2e7ba7af21677b8e77039a 100644 (file)
--- a/experiments9/non_generated/full_core_ls180.il
+++ b/experiments9/non_generated/full_core_ls180.il
@@ -82689,24 +82689,24 @@ module \ls180
   wire \builder_sync_rhs_array_muxed6
   attribute \src "ls180.v:1894.6-1894.18"
   wire \builder_wait
-  attribute \src "ls180.v:30.19-30.23"
-  wire width 3 input 26 \eint
-  attribute \src "ls180.v:145.12-145.18"
+  attribute \src "ls180.v:42.19-42.23"
+  wire width 3 input 38 \eint
+  attribute \src "ls180.v:157.12-157.18"
   wire width 3 \eint_1
-  attribute \src "ls180.v:25.20-25.26"
-  wire width 16 input 21 \gpio_i
-  attribute \src "ls180.v:26.21-26.27"
-  wire width 16 output 22 \gpio_o
-  attribute \src "ls180.v:27.21-27.28"
-  wire width 16 output 23 \gpio_oe
-  attribute \src "ls180.v:5.14-5.21"
-  wire output 1 \i2c_scl
-  attribute \src "ls180.v:6.13-6.22"
-  wire input 2 \i2c_sda_i
-  attribute \src "ls180.v:7.14-7.23"
-  wire output 3 \i2c_sda_o
-  attribute \src "ls180.v:8.14-8.24"
-  wire output 4 \i2c_sda_oe
+  attribute \src "ls180.v:28.20-28.26"
+  wire width 16 input 24 \gpio_i
+  attribute \src "ls180.v:29.21-29.27"
+  wire width 16 output 25 \gpio_o
+  attribute \src "ls180.v:30.21-30.28"
+  wire width 16 output 26 \gpio_oe
+  attribute \src "ls180.v:35.14-35.21"
+  wire output 31 \i2c_scl
+  attribute \src "ls180.v:36.13-36.22"
+  wire input 32 \i2c_sda_i
+  attribute \src "ls180.v:37.14-37.23"
+  wire output 33 \i2c_sda_o
+  attribute \src "ls180.v:38.14-38.24"
+  wire output 34 \i2c_sda_oe
   attribute \src "ls180.v:49.13-49.21"
   wire input 45 \jtag_tck
   attribute \src "ls180.v:50.13-50.21"
@@ -82999,65 +82999,65 @@ module \ls180
   wire width 64 \main_libresocsim_libresoc2
   attribute \src "ls180.v:123.12-123.45"
   wire width 2 \main_libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:142.13-142.67"
+  attribute \src "ls180.v:145.13-145.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
-  attribute \src "ls180.v:143.13-143.67"
+  attribute \src "ls180.v:146.13-146.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
-  attribute \src "ls180.v:144.13-144.68"
+  attribute \src "ls180.v:147.13-147.68"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
-  attribute \src "ls180.v:125.6-125.61"
+  attribute \src "ls180.v:152.6-152.61"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
-  attribute \src "ls180.v:126.6-126.63"
+  attribute \src "ls180.v:153.6-153.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
-  attribute \src "ls180.v:127.6-127.63"
+  attribute \src "ls180.v:154.6-154.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
-  attribute \src "ls180.v:128.6-128.64"
+  attribute \src "ls180.v:155.6-155.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
-  attribute \src "ls180.v:134.6-134.64"
+  attribute \src "ls180.v:125.6-125.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
-  attribute \src "ls180.v:135.6-135.66"
+  attribute \src "ls180.v:126.6-126.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
-  attribute \src "ls180.v:136.6-136.66"
+  attribute \src "ls180.v:127.6-127.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
-  attribute \src "ls180.v:137.6-137.67"
+  attribute \src "ls180.v:128.6-128.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
-  attribute \src "ls180.v:146.13-146.68"
+  attribute \src "ls180.v:133.13-133.68"
   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
-  attribute \src "ls180.v:155.12-155.68"
+  attribute \src "ls180.v:142.12-142.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
-  attribute \src "ls180.v:152.6-152.65"
+  attribute \src "ls180.v:139.6-139.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
-  attribute \src "ls180.v:154.6-154.63"
+  attribute \src "ls180.v:141.6-141.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
-  attribute \src "ls180.v:153.6-153.64"
+  attribute \src "ls180.v:140.6-140.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
-  attribute \src "ls180.v:156.12-156.68"
+  attribute \src "ls180.v:143.12-143.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
-  attribute \src "ls180.v:147.13-147.71"
+  attribute \src "ls180.v:134.13-134.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
-  attribute \src "ls180.v:148.13-148.71"
+  attribute \src "ls180.v:135.13-135.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
-  attribute \src "ls180.v:149.6-149.65"
+  attribute \src "ls180.v:136.6-136.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
-  attribute \src "ls180.v:151.6-151.65"
+  attribute \src "ls180.v:138.6-138.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
-  attribute \src "ls180.v:150.6-150.64"
+  attribute \src "ls180.v:137.6-137.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
-  attribute \src "ls180.v:138.6-138.67"
+  attribute \src "ls180.v:129.6-129.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
-  attribute \src "ls180.v:140.6-140.68"
+  attribute \src "ls180.v:131.6-131.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
-  attribute \src "ls180.v:141.6-141.68"
+  attribute \src "ls180.v:132.6-132.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
-  attribute \src "ls180.v:139.6-139.68"
+  attribute \src "ls180.v:130.6-130.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
-  attribute \src "ls180.v:130.6-130.67"
+  attribute \src "ls180.v:148.6-148.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
-  attribute \src "ls180.v:132.6-132.68"
+  attribute \src "ls180.v:150.6-150.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
-  attribute \src "ls180.v:133.6-133.68"
+  attribute \src "ls180.v:151.6-151.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
-  attribute \src "ls180.v:131.6-131.68"
+  attribute \src "ls180.v:149.6-149.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
   attribute \src "ls180.v:72.5-72.39"
   wire \main_libresocsim_libresoc_dbus_ack
@@ -86227,50 +86227,50 @@ module \ls180
   wire width 24 input 48 \nc
   attribute \src "ls180.v:247.6-247.13"
   wire \por_clk
-  attribute \src "ls180.v:9.19-9.22"
-  wire width 2 output 5 \pwm
-  attribute \src "ls180.v:129.12-129.17"
+  attribute \src "ls180.v:41.19-41.22"
+  wire width 2 output 37 \pwm
+  attribute \src "ls180.v:156.12-156.17"
   wire width 2 \pwm_1
-  attribute \src "ls180.v:14.13-14.23"
-  wire output 10 \sdcard_clk
-  attribute \src "ls180.v:15.13-15.25"
-  wire input 11 \sdcard_cmd_i
-  attribute \src "ls180.v:16.13-16.25"
-  wire output 12 \sdcard_cmd_o
-  attribute \src "ls180.v:17.13-17.26"
-  wire output 13 \sdcard_cmd_oe
-  attribute \src "ls180.v:18.19-18.32"
-  wire width 4 input 14 \sdcard_data_i
-  attribute \src "ls180.v:19.19-19.32"
-  wire width 4 output 15 \sdcard_data_o
-  attribute \src "ls180.v:20.13-20.27"
-  wire output 16 \sdcard_data_oe
-  attribute \src "ls180.v:31.20-31.27"
-  wire width 13 output 27 \sdram_a
-  attribute \src "ls180.v:40.19-40.27"
-  wire width 2 output 36 \sdram_ba
-  attribute \src "ls180.v:37.13-37.24"
-  wire output 33 \sdram_cas_n
-  attribute \src "ls180.v:39.13-39.22"
-  wire output 35 \sdram_cke
-  attribute \src "ls180.v:42.13-42.24"
-  wire output 38 \sdram_clock
-  attribute \src "ls180.v:157.6-157.19"
+  attribute \src "ls180.v:5.13-5.23"
+  wire output 1 \sdcard_clk
+  attribute \src "ls180.v:6.13-6.25"
+  wire input 2 \sdcard_cmd_i
+  attribute \src "ls180.v:7.13-7.25"
+  wire output 3 \sdcard_cmd_o
+  attribute \src "ls180.v:8.13-8.26"
+  wire output 4 \sdcard_cmd_oe
+  attribute \src "ls180.v:9.19-9.32"
+  wire width 4 input 5 \sdcard_data_i
+  attribute \src "ls180.v:10.19-10.32"
+  wire width 4 output 6 \sdcard_data_o
+  attribute \src "ls180.v:11.13-11.27"
+  wire output 7 \sdcard_data_oe
+  attribute \src "ls180.v:16.20-16.27"
+  wire width 13 output 12 \sdram_a
+  attribute \src "ls180.v:25.19-25.27"
+  wire width 2 output 21 \sdram_ba
+  attribute \src "ls180.v:22.13-22.24"
+  wire output 18 \sdram_cas_n
+  attribute \src "ls180.v:24.13-24.22"
+  wire output 20 \sdram_cke
+  attribute \src "ls180.v:27.13-27.24"
+  wire output 23 \sdram_clock
+  attribute \src "ls180.v:144.6-144.19"
   wire \sdram_clock_1
-  attribute \src "ls180.v:38.13-38.23"
-  wire output 34 \sdram_cs_n
-  attribute \src "ls180.v:41.19-41.27"
-  wire width 2 output 37 \sdram_dm
-  attribute \src "ls180.v:32.20-32.30"
-  wire width 16 input 28 \sdram_dq_i
-  attribute \src "ls180.v:33.20-33.30"
-  wire width 16 output 29 \sdram_dq_o
-  attribute \src "ls180.v:34.13-34.24"
-  wire output 30 \sdram_dq_oe
-  attribute \src "ls180.v:36.13-36.24"
-  wire output 32 \sdram_ras_n
-  attribute \src "ls180.v:35.13-35.23"
-  wire output 31 \sdram_we_n
+  attribute \src "ls180.v:23.13-23.23"
+  wire output 19 \sdram_cs_n
+  attribute \src "ls180.v:26.19-26.27"
+  wire width 2 output 22 \sdram_dm
+  attribute \src "ls180.v:17.20-17.30"
+  wire width 16 input 13 \sdram_dq_i
+  attribute \src "ls180.v:18.20-18.30"
+  wire width 16 output 14 \sdram_dq_o
+  attribute \src "ls180.v:19.13-19.24"
+  wire output 15 \sdram_dq_oe
+  attribute \src "ls180.v:21.13-21.24"
+  wire output 17 \sdram_ras_n
+  attribute \src "ls180.v:20.13-20.23"
+  wire output 16 \sdram_we_n
   attribute \src "ls180.v:2643.6-2643.15"
   wire \sdrio_clk
   attribute \src "ls180.v:2644.6-2644.17"
@@ -86409,22 +86409,22 @@ module \ls180
   wire \sdrio_clk_8
   attribute \src "ls180.v:2652.6-2652.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:21.13-21.26"
-  wire output 17 \spimaster_clk
-  attribute \src "ls180.v:23.13-23.27"
-  wire output 19 \spimaster_cs_n
-  attribute \src "ls180.v:24.13-24.27"
-  wire input 20 \spimaster_miso
-  attribute \src "ls180.v:22.13-22.27"
-  wire output 18 \spimaster_mosi
-  attribute \src "ls180.v:10.13-10.26"
-  wire output 6 \spisdcard_clk
-  attribute \src "ls180.v:12.13-12.27"
-  wire output 8 \spisdcard_cs_n
+  attribute \src "ls180.v:12.13-12.26"
+  wire output 8 \spimaster_clk
+  attribute \src "ls180.v:14.13-14.27"
+  wire output 10 \spimaster_cs_n
+  attribute \src "ls180.v:15.13-15.27"
+  wire input 11 \spimaster_miso
   attribute \src "ls180.v:13.13-13.27"
-  wire input 9 \spisdcard_miso
-  attribute \src "ls180.v:11.13-11.27"
-  wire output 7 \spisdcard_mosi
+  wire output 9 \spimaster_mosi
+  attribute \src "ls180.v:31.13-31.26"
+  wire output 27 \spisdcard_clk
+  attribute \src "ls180.v:33.13-33.27"
+  wire output 29 \spisdcard_cs_n
+  attribute \src "ls180.v:34.13-34.27"
+  wire input 30 \spisdcard_miso
+  attribute \src "ls180.v:32.13-32.27"
+  wire output 28 \spisdcard_mosi
   attribute \src "ls180.v:43.13-43.20"
   wire input 39 \sys_clk
   attribute \src "ls180.v:245.6-245.15"
@@ -86439,10 +86439,10 @@ module \ls180
   wire input 40 \sys_rst
   attribute \src "ls180.v:246.6-246.15"
   wire \sys_rst_1
-  attribute \src "ls180.v:29.13-29.20"
-  wire input 25 \uart_rx
-  attribute \src "ls180.v:28.13-28.20"
-  wire output 24 \uart_tx
+  attribute \src "ls180.v:40.13-40.20"
+  wire input 36 \uart_rx
+  attribute \src "ls180.v:39.13-39.20"
+  wire output 35 \uart_tx
   attribute \src "ls180.v:10041.12-10041.15"
   memory width 32 size 128 \mem
   attribute \src "ls180.v:10061.12-10061.19"
@@ -126221,14 +126221,14 @@ module \ls180
   end
   attribute \src "ls180.v:7427.1-10039.4"
   process $proc$ls180.v:7427$2374
-    assign $0\pwm[1:0] \pwm
-    assign $0\spisdcard_clk[0:0] \spisdcard_clk
-    assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
-    assign { } { }
     assign $0\spimaster_clk[0:0] \spimaster_clk
     assign $0\spimaster_mosi[0:0] \spimaster_mosi
     assign { } { }
+    assign $0\spisdcard_clk[0:0] \spisdcard_clk
+    assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
+    assign { } { }
     assign $0\uart_tx[0:0] \uart_tx
+    assign $0\pwm[1:0] \pwm
     assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
     assign { } { }
     assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
@@ -130753,14 +130753,14 @@ module \ls180
         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
         assign $0\main_libresocsim_scratch_re[0:0] 1'0
         assign $0\main_libresocsim_bus_errors[31:0] 0
-        assign $0\pwm[1:0] 2'00
-        assign $0\spisdcard_clk[0:0] 1'0
-        assign $0\spisdcard_mosi[0:0] 1'0
-        assign $0\spisdcard_cs_n[0:0] 1'0
         assign $0\spimaster_clk[0:0] 1'0
         assign $0\spimaster_mosi[0:0] 1'0
         assign $0\spimaster_cs_n[0:0] 1'0
+        assign $0\spisdcard_clk[0:0] 1'0
+        assign $0\spisdcard_mosi[0:0] 1'0
+        assign $0\spisdcard_cs_n[0:0] 1'0
         assign $0\uart_tx[0:0] 1'1
+        assign $0\pwm[1:0] 2'00
         assign $0\main_libresocsim_converter0_counter[0:0] 1'0
         assign $0\main_libresocsim_converter1_counter[0:0] 1'0
         assign $0\main_libresocsim_converter2_counter[0:0] 1'0
@@ -131044,14 +131044,14 @@ module \ls180
       case 
     end
     sync posedge \sys_clk_1
-      update \pwm $0\pwm[1:0]
-      update \spisdcard_clk $0\spisdcard_clk[0:0]
-      update \spisdcard_mosi $0\spisdcard_mosi[0:0]
-      update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
       update \spimaster_clk $0\spimaster_clk[0:0]
       update \spimaster_mosi $0\spimaster_mosi[0:0]
       update \spimaster_cs_n $0\spimaster_cs_n[0:0]
+      update \spisdcard_clk $0\spisdcard_clk[0:0]
+      update \spisdcard_mosi $0\spisdcard_mosi[0:0]
+      update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
       update \uart_tx $0\uart_tx[0:0]
+      update \pwm $0\pwm[1:0]
       update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
       update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
       update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]