no need for sel0

diff --git a/src/soc/experiment/cache_ram.py b/src/soc/experiment/cache_ram.py
index 4f7e47057ade0135948814caebccc036cf99d42f..71dc89cac11286c77b1f448f29055e2db9b0127b 100644 (file)
--- a/src/soc/experiment/cache_ram.py
+++ b/src/soc/experiment/cache_ram.py
@@ -31,10 +31,8 @@ class CacheRam(Elaboratable):
      
         rd_data0 = Signal(WIDTH)
      
-        sel0 = Signal(WIDTH//8) # defaults to zero
-
         with m.If(TRACE):
-            with m.If(self.wr_sel != sel0):
+            with m.If(self.wr_sel.bool()):
                 sync += Display( "write a: %x sel: %x dat: %x",
                                 self.wr_addr, self.wr_sel, self.wr_data)
         for i in range(WIDTH//8):