add Makefile for creating ls180.il

diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile
new file mode 100644 (file)
index 0000000..48937c3
--- /dev/null
+++ b/src/soc/litex/florent/Makefile
@@ -0,0 +1,9 @@
+ls180:
+       ./ls180soc.py --build --platform=ls180
+       cp build/ls180/gateware/ls180.v .
+       cp build/ls180/gateware/mem.init .
+       cp libresoc/libresoc.v .
+       yosys -p 'read_verilog ls180.v; read_verilog libresoc.v; write_ilang ls180.il'
+       yosys -p 'read_verilog ls180.v' \
+          -p 'read_verilog libresoc.v' \
+          -p 'write_ilang ls180.il'