first cut at qemu memory dump and compare

diff --git a/src/soc/simulator/qemu.py b/src/soc/simulator/qemu.py
index 1dbdb20562895cb47290370e42bebb9cf5931891..4130f86337fcfaa5fb12a660b5fa809c0c2212e1 100644 (file)
--- a/src/soc/simulator/qemu.py
+++ b/src/soc/simulator/qemu.py
@@ -34,6 +34,13 @@ class QemuController:
             breakstring = f' {breakpoint}'
         return self.gdb.write('-break-delete' + breakstring)
 
+    def get_mem(self, addr, nbytes):
+        res = self.gdb.write("-data-read-memory %d u 8 1 %d" % (addr, nbytes))
+        print ("get_mem", res)
+        for x in res:
+            if(x["type"]=="result"):
+                return x['payload']['memory'][0]['data']
+        return None
 
     def get_registers(self):
         return self.gdb.write('-data-list-register-values x')

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index fbe792b556d5a28e0afa647c6f24924adfb103fb..76fc17f6a96076481f8d5f7b747b3380699f3baa 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -95,7 +95,7 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
-    def test_ldst_widths(self):
+    def test_0_ldst_widths(self):
         lst = ["addis 1, 0, 0xdead",
                "ori 1, 1, 0xbeef",
                "addi 2, 0, 0x1000",
@@ -145,12 +145,25 @@ class DecoderTestCase(FHDLTestCase):
             self.run_tst_program(program, [1])
 
     def run_tst_program(self, prog, reglist):
+        import sys
         simulator = self.run_tst(prog)
         prog.reset()
         with run_program(prog) as q:
             self.qemu_register_compare(simulator, q, reglist)
+            self.qemu_mem_compare(simulator, q, reglist)
         print(simulator.gpr.dump())
 
+    def qemu_mem_compare(self, sim, qemu, regs):
+        addr = 0x1000
+        qmemdump = qemu.get_mem(addr, 16)
+        for i in range(len(qmemdump)):
+            s = hex(int(qmemdump[i]))
+            print ("qemu mem %06x %s" % (addr+i*8, s))
+        for k, v in sim.mem.mem.items():
+            print ("sim      %06x %016x" % (k, v))
+        for k, v in sim.mem.mem.items():
+            self.assertEqual(int(qmemdump[(k-0x200)//8]), v) # magic constant??
+
     def qemu_register_compare(self, sim, qemu, regs):
         qpc, qxer, qcr = qemu.get_pc(), qemu.get_xer(), qemu.get_cr()
         sim_cr = sim.cr.get_range().value