reduce dcache/icache number of ways, to fit into ECP5 45k resource
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 16 Apr 2022 22:03:27 +0000 (23:03 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 16 Apr 2022 22:03:30 +0000 (23:03 +0100)
src/soc/experiment/dcache.py
src/soc/experiment/icache.py

index f2e4360abc5c68d87a6e3c923a5a5388fa0e0899..39578ebc98dd5e6f9bbe1548a62d4634cdb2ed63 100644 (file)
@@ -747,10 +747,10 @@ class DCache(Elaboratable, DCacheConfig):
 
         if self.microwatt_compat:
             # reduce way sizes and num lines
-            super().__init__(NUM_LINES = 4,
+            super().__init__(NUM_LINES = 2,
                               NUM_WAYS = 1,
                               TLB_NUM_WAYS = 1,
-                              TLB_SET_SIZE=4) # XXX needs device-tree entry
+                              TLB_SET_SIZE=2) # XXX needs device-tree entry
         else:
             super().__init__()
 
index e9c8ed1b1db45b50e6eb7d6158706aaeee6ed14e..b0b674c845601d369d379e880f199ef563df4263 100644 (file)
@@ -345,9 +345,9 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             # reduce way sizes and num lines
             ICacheConfig.__init__(self, LINE_SIZE=XLEN,
                                         XLEN=XLEN,
-                                        NUM_LINES = 4,
+                                        NUM_LINES = 2,
                                         NUM_WAYS = 1,
-                                        TLB_SIZE=4 # needs device-tree update
+                                        TLB_SIZE=2 # needs device-tree update
                                  )
         else:
             ICacheConfig.__init__(self, LINE_SIZE=XLEN, XLEN=XLEN)