Initialize the core SVSTATE from the corresponding test case

Handle the case of initialization by integer, which is the default for all
test_issuer.py cases.

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 72f470406b6d253398928fe1d6ffae4d3d775c79..3e22a8a01e19f651fe42407987d8c8c763322d09 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -13,12 +13,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle
 from nmutil.formaltest import FHDLTestCase
 from nmutil.gtkw import write_gtkw
 from nmigen.cli import rtlil
-from soc.decoder.isa.caller import special_sprs
+from soc.decoder.isa.caller import special_sprs, SVP64State
 from soc.decoder.isa.all import ISA
 from soc.config.endian import bigendian
 
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
+from soc.regfile.regfiles import StateRegs
 
 from soc.simple.issuer import TestIssuerInternal
 
@@ -216,6 +217,12 @@ class TestRunner(FHDLTestCase):
                 yield from setup_regs(pdecode2, core, test)
                 # TODO, setup svstate here in core.regs.state regfile
                 # https://bugs.libre-soc.org/show_bug.cgi?id=583#c35
+                # setup of SVSTATE
+                initial_svstate = test.svstate
+                if isinstance(initial_svstate, int):
+                    initial_svstate = SVP64State(initial_svstate)
+                svstate_reg = core.regs.state.regs[StateRegs.SVSTATE].reg
+                yield svstate_reg.eq(initial_svstate.spr.value)
 
                 yield pc_i.eq(pc)
                 yield issuer.pc_i.ok.eq(1)