add fn-unit src/dest latch registers

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 018c8a17a7893a42f5e1faf2d63eaa9ed6af912a..09d52451393458965cfd70ce0d67bbd40f956efc 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -305,7 +305,7 @@ def scoreboard_sim(dut, alusim):
 
         yield from alusim.check(dut)
 
-    for i in range(3):
+    for i in range(10):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
         while True:

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 220885f2503dc46426860c583e32f46e9a6bac4c..5ac1164dccde7cbb09ab9cec18dbe3826f9f8376 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -459,7 +459,6 @@ def scoreboard_sim(dut, alusim):
         for i in range(len(dut.int_insn_i)):
             yield dut.int_insn_i[i].eq(0)
         yield
-        yield
 
 
     yield

diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 220eee7b8e09dc7caf5184fb43da2401265778e3..a279c9f60a2ad30542fdab3cfeb48c7c4e76a36b 100644 (file)
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -1,9 +1,10 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Cat, Array, Const, Elaboratable
-from nmutil.latch import SRLatch
 from nmigen.lib.coding import Decoder
 
+from nmutil.latch import SRLatch, latchregister
+
 from .shadow_fn import ShadowFn
 
 
@@ -134,16 +135,24 @@ class FnUnit(Elaboratable):
         m.d.comb += rd_l.s.eq(self.issue_i)
         m.d.comb += rd_l.r.eq(self.go_rd_i | recover)
 
-        # dest decoder: write-pending out
-        m.d.comb += dest_d.i.eq(self.dest_i)
+        # latch/registers for dest / src1 / src2
+        dest_r = Signal(max=self.reg_width, reset_less=True)
+        src1_r = Signal(max=self.reg_width, reset_less=True)
+        src2_r = Signal(max=self.reg_width, reset_less=True)
+        latchregister(m, self.dest_i, dest_r, wr_l.qn)
+        latchregister(m, self.src1_i, src1_r, wr_l.qn)
+        latchregister(m, self.src2_i, src2_r, wr_l.qn)
+
+        # dest decoder (use dest reg as input): write-pending out
+        m.d.comb += dest_d.i.eq(dest_r)
         m.d.comb += dest_d.n.eq(wr_l.qn) # decode is inverted
         m.d.comb += self.busy_o.eq(wr_l.q) # busy if set
         m.d.comb += xx_pend_o.eq(dest_d.o)
 
-        # src1/src2 decoder: read-pending out
-        m.d.comb += src1_d.i.eq(self.src1_i)
+        # src1/src2 decoder (use src1/2 regs as input): read-pending out
+        m.d.comb += src1_d.i.eq(src1_r)
         m.d.comb += src1_d.n.eq(rd_l.qn) # decode is inverted
-        m.d.comb += src2_d.i.eq(self.src2_i)
+        m.d.comb += src2_d.i.eq(src2_r)
         m.d.comb += src2_d.n.eq(rd_l.qn) # decode is inverted
         m.d.comb += self.src1_pend_o.eq(src1_d.o)
         m.d.comb += self.src2_pend_o.eq(src2_d.o)