af = CRL.AllianceFramework.get()
-def find
def scriptMain ( **kw ):
"""The mandatory function that Coriolis CGT/Unicorn will look for."""
(IW | AB, 'oper_i_alu_div0_is_signed' , 0, l(20) ),
(IW | AB, 'oper_i_alu_div0_oe_oe' , 0, l(20) ),
(IW | AB, 'oper_i_alu_div0_oe_oe_ok' , 0, l(20) ),
+ (IW | AB, 'oper_i_alu_div0_output_carry' , 0, l(20) ),
(IW | AB, 'oper_i_alu_div0_rc_rc' , 0, l(20) ),
(IW | AB, 'oper_i_alu_div0_rc_rc_ok' , 0, l(20) ),
(IW | AB, 'oper_i_alu_div0_write_cr0' , 0, l(20) ),
(IW | AB, 'cu_rd_go_i({})' , 0, l(10.0), 3),
(IW | AB, 'cu_rdmaskn_i({})' , 0, l(10.0), 3),
(IW | AB, 'cu_wr_go_i({})' , 0, l(10.0), 4),
+ (IW | AB, 'oper_i_alu_div0_data_len' , 0, l(10.0), 7),
(IW | AB, 'oper_i_alu_div0_insn_type({})' , 0, l(10.0), 7),
(IW | AB, 'oper_i_alu_div0_fn_unit({})' , 0, l(10.0), 11),
(IW | AB, 'oper_i_alu_div0_insn({})' , 0, l(10.0), 32),
cr0 = af.getCell( 'cr0', CRL.Catalog.State.Views )
blockCr0 = Block.create \
( cr0
- , ioPins=[ (IN, 'clk' , l( 805.0) )
- , (IW , 'cu_issue_i' , l( 30.0) )
- , (IW , 'oper_i_alu_cr0_read_cr_whole' , l( 40.0) )
- , (IW , 'oper_i_alu_cr0_write_cr_whole' , l( 70.0) )
- , (IW , 'rst' , l( 160.0) )
- , (IW , 'src4_i({})' , l( 180.0), l( 10.0), 4)
- , (IW , 'src5_i({})' , l( 220.0), l( 10.0), 4)
- , (IW , 'src6_i({})' , l( 260.0), l( 10.0), 4)
- , (IW , 'cu_rd_go_i({})' , l( 300.0), l( 10.0), 6)
- , (IW , 'cu_rdmaskn_i({})' , l( 360.0), l( 10.0), 6)
- , (IW , 'cu_wr_go_i({})' , l( 420.0), l( 10.0), 3)
- , (IW , 'oper_i_alu_cr0_insn_type({})' , l( 450.0), l( 10.0), 7)
- , (IW , 'oper_i_alu_cr0_fn_unit({})' , l( 520.0), l( 10.0), 11)
- , (IW , 'oper_i_alu_cr0_insn({})' , l( 630.0), l( 10.0), 32)
- , (IS, 'src1_i({})' , l( 10.0), l( 10.0), 64)
- , (IS, 'src2_i({})' , l( 15.0), l( 10.0), 64)
- , (IE , 'src3_i({})' , l( 10.0), l( 20.0), 32)
- , (IE , 'cu_busy_o' , l(4320.0) )
- , (IE , 'cr_a_ok' , l(4340.0) )
- , (IE , 'full_cr_ok' , l(4360.0) )
- , (IE , 'o_ok' , l(4380.0) )
- , (IE , 'dest2_o({})' , l(4400.0), l( 10.0), 32)
- , (IE , 'dest3_o({})' , l(4720.0), l( 10.0), 4)
- , (IE , 'cu_rd_rel_o({})' , l(4800.0), l( 20.0), 6)
- , (IE , 'cu_wr_rel_o({})' , l(4920.0), l( 20.0), 3)
- , (IN, 'dest1_o({})' , l( 100.0), l( 10.0), 64)
+ , ioPins=[
+ (IN, 'clk' , l( 805.0) )
+ , (IW , 'cu_issue_i' , l( 30.0) )
+ , (IW , 'oper_i_alu_cr0_read_cr_whole' , l( 40.0) )
+ , (IW , 'oper_i_alu_cr0_write_cr_whole' , l( 70.0) )
+ , (IW , 'rst' , l( 160.0) )
+ , (IW , 'src4_i({})' , l( 180.0), l( 10.0), 4)
+ , (IW , 'src5_i({})' , l( 220.0), l( 10.0), 4)
+ , (IW , 'src6_i({})' , l( 260.0), l( 10.0), 4)
+ , (IW , 'cu_rd_go_i({})' , l( 300.0), l( 10.0), 6)
+ , (IW , 'cu_rdmaskn_i({})' , l( 360.0), l( 10.0), 6)
+ , (IW , 'cu_wr_go_i({})' , l( 420.0), l( 10.0), 3)
+ , (IW , 'oper_i_alu_cr0_insn_type({})' , l( 450.0), l( 10.0), 7)
+ , (IW , 'oper_i_alu_cr0_fn_unit({})' , l( 520.0), l( 10.0), 11)
+ , (IW , 'oper_i_alu_cr0_insn({})' , l( 630.0), l( 10.0), 32)
+ , (IS, 'src1_i({})' , l( 10.0), l( 10.0), 64)
+ , (IS, 'src2_i({})' , l( 15.0), l( 10.0), 64)
+ , (IE , 'src3_i({})' , l( 10.0), l( 20.0), 32)
+ , (IE , 'cu_busy_o' , l(4320.0) )
+ , (IE , 'cr_a_ok' , l(4340.0) )
+ , (IE , 'full_cr_ok' , l(4360.0) )
+ , (IE , 'o_ok' , l(4380.0) )
+ , (IE , 'dest2_o({})' , l(4400.0), l( 10.0), 32)
+ , (IE , 'dest3_o({})' , l(4720.0), l( 10.0), 4)
+ , (IE , 'cu_rd_rel_o({})' , l(4800.0), l( 20.0), 6)
+ , (IE , 'cu_wr_rel_o({})' , l(4920.0), l( 20.0), 3)
+ , (IN, 'dest1_o({})' , l( 100.0), l( 10.0), 64)
]
)
blockCr0.state.cfg.etesian.spaceMargin = 0.10
ldst0 = af.getCell( 'ldst0', CRL.Catalog.State.Views )
blockLdst0 = Block.create \
( ldst0
- , ioPins=[ (IN , 'clk' , l(805.0) )
- , (IW | AB, 'cu_ad_go_i' , 0, l(20), 1)
- , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
- , (IW | AB, 'ldst_port0_addr_exc_o' , 0, l(20), 1)
- , (IW | AB, 'ldst_port0_addr_ok_o' , 0, l(20), 1)
- , (IW | AB, 'ldst_port0_ld_data_o_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_byte_reverse' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_is_32bit' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_is_signed' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_oe_oe' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_oe_oe_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_rc_rc' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_rc_rc_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_sign_extend' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_zero_a' , 0, l(20), 1)
- , (IW | AB, 'rst' , 0, l(20), 1)
- , (IW | AB, 'cu_st_go_i' , 0, l(20), 1)
- , (IW | AB, 'oper_i_ldst_ldst0_ldst_mode({})' , 0, l(20), 2)
- , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 3)
- , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 3)
- , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 2)
- , (IW | AB, 'oper_i_ldst_ldst0_data_len({})' , 0, l(20), 4)
- , (IW | AB, 'oper_i_ldst_ldst0_insn_type({})' , 0, l(20), 7)
- , (IW | AB, 'ldst_port0_ld_data_o({})' , 0, l(20), 64)
- , (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm({})' , 0, l(20), 64)
- , (IS | AB, 'src1_i({})' , 0, l(10), 64)
- , (IS | AB, 'src2_i({})' , 0, l(5), 64)
- , (IE | AE , 'src3_i({})' , 0, 0, 64)
- , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
- , (IE | AE , 'cu_ad_rel_o' , 0, l(20), 1)
- , (IE | AE , 'ldst_port0_addr_i_ok' , 0, l(20), 1)
- , (IE | AE , 'ldst_port0_is_ld_i' , 0, l(20), 1)
- , (IE | AE , 'ldst_port0_is_st_i' , 0, l(20), 1)
- , (IE | AE , 'load_mem_o' , 0, l(20), 1)
- , (IE | AE , 'cu_st_rel_o' , 0, l(20), 1)
- , (IE | AE , 'stwd_mem_o' , 0, l(20), 1)
- , (IE | AE , 'ea({})' , 0, l(20), 64)
- , (IE | AE , 'ldst_port0_st_data_i({})' , 0, l(20), 64)
- , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 3)
- , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 2)
- , (IE | AE , 'ldst_port0_addr_i_95' , 0, l(20), 1)
- , (IE | AE , 'ldst_port0_addr_i_{}' , 0, l(20), 64)
- , (IN | AE , 'o({})' , 0, 0, 64)
+ , ioPins=[
+ (IN , 'clk' , l(805.0) )
+ , (IW | AB, 'cu_ad_go_i' , 0, l(20), 1)
+ , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
+ , (IW | AB, 'ldst_port0_addr_exc_o' , 0, l(20), 1)
+ , (IW | AB, 'ldst_port0_addr_ok_o' , 0, l(20), 1)
+ , (IW | AB, 'ldst_port0_ld_data_o_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_byte_reverse' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_is_32bit' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_is_signed' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_oe_oe' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_oe_oe_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_rc_rc' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_rc_rc_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_sign_extend' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_zero_a' , 0, l(20), 1)
+ , (IW | AB, 'rst' , 0, l(20), 1)
+ , (IW | AB, 'cu_st_go_i' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_ldst_ldst0_ldst_mode({})' , 0, l(20), 2)
+ , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 3)
+ , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 3)
+ , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 2)
+ , (IW | AB, 'oper_i_ldst_ldst0_data_len({})' , 0, l(20), 4)
+ , (IW | AB, 'oper_i_ldst_ldst0_insn_type({})' , 0, l(20), 7)
+ , (IW | AB, 'ldst_port0_ld_data_o({})' , 0, l(20), 64)
+ , (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm({})' , 0, l(20), 64)
+ , (IS | AB, 'src1_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src2_i({})' , 0, l(5), 64)
+ , (IE | AE , 'src3_i({})' , 0, 0, 64)
+ , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
+ , (IE | AE , 'cu_ad_rel_o' , 0, l(20), 1)
+ , (IE | AE , 'ldst_port0_addr_i_ok' , 0, l(20), 1)
+ , (IE | AE , 'ldst_port0_is_ld_i' , 0, l(20), 1)
+ , (IE | AE , 'ldst_port0_is_st_i' , 0, l(20), 1)
+ , (IE | AE , 'load_mem_o' , 0, l(20), 1)
+ , (IE | AE , 'cu_st_rel_o' , 0, l(20), 1)
+ , (IE | AE , 'stwd_mem_o' , 0, l(20), 1)
+ , (IE | AE , 'ea({})' , 0, l(20), 64)
+ , (IE | AE , 'ldst_port0_st_data_i({})' , 0, l(20), 64)
+ , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 3)
+ , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 2)
+ , (IE | AE , 'ldst_port0_addr_i_95' , 0, l(20), 1)
+ , (IE | AE , 'ldst_port0_addr_i_{}' , 0, l(20), 64)
+ , (IN | AE , 'o({})' , 0, 0, 64)
]
)
blockLdst0.state.cfg.etesian.uniformDensity = True
logical0 = af.getCell( 'logical0', CRL.Catalog.State.Views )
blockLogical0 = Block.create \
( logical0
- , ioPins=[ (IN , 'clk' , l(805.0) )
- , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_imm_data_imm_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_invert_a' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_invert_out' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_is_32bit' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_is_signed' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_oe_oe' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_oe_oe_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_output_carry' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_rc_rc' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_rc_rc_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_write_cr0' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_zero_a' , 0, l(20), 1)
- , (IW | AB, 'rst' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_logical0_input_carry({})' , 0, l(20), 2)
- , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 2)
- , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 2)
- , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 3)
- , (IW | AB, 'oper_i_alu_logical0_data_len({})' , 0, l(20), 4)
- , (IW | AB, 'oper_i_alu_logical0_insn_type({})' , 0, l(20), 7)
- , (IW | AB, 'oper_i_alu_logical0_fn_unit({})' , 0, l(20), 11)
- , (IW | AB, 'oper_i_alu_logical0_insn({})' , 0, l(20), 32)
- , (IW | AB, 'oper_i_alu_logical0_imm_data_imm({})', 0, l(20), 64)
- , (IS | AB, 'src1_i({})' , 0, l(10), 64)
- , (IS | AB, 'src2_i({})' , 0, l(5), 64)
- , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
- , (IE | AE , 'cr_a_ok' , 0, l(20), 1)
- , (IE | AE , 'o_ok' , 0, l(20), 1)
- , (IE | AE , 'xer_ca_ok' , 0, l(20), 1)
- , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 2)
- , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 3)
- , (IN | AE , 'dest3_o({})' , 0, 0, 2)
- , (IN | AE , 'dest2_o({})' , 0, 0, 4)
- , (IN | AE , 'dest1_o({})' , 0, 0, 64)
+ , ioPins=[
+ (IN , 'clk' , l(805.0) )
+ , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_imm_data_imm_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_invert_a' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_invert_out' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_is_32bit' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_is_signed' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_oe_oe' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_oe_oe_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_output_carry' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_rc_rc' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_rc_rc_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_write_cr0' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_zero_a' , 0, l(20), 1)
+ , (IW | AB, 'rst' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_logical0_input_carry({})' , 0, l(20), 2)
+ , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 2)
+ , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 2)
+ , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 3)
+ , (IW | AB, 'oper_i_alu_logical0_data_len({})' , 0, l(20), 4)
+ , (IW | AB, 'oper_i_alu_logical0_insn_type({})' , 0, l(20), 7)
+ , (IW | AB, 'oper_i_alu_logical0_fn_unit({})' , 0, l(20), 11)
+ , (IW | AB, 'oper_i_alu_logical0_insn({})' , 0, l(20), 32)
+ , (IW | AB, 'oper_i_alu_logical0_imm_data_imm({})', 0, l(20), 64)
+ , (IS | AB, 'src1_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src2_i({})' , 0, l(5), 64)
+ , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
+ , (IE | AE , 'cr_a_ok' , 0, l(20), 1)
+ , (IE | AE , 'o_ok' , 0, l(20), 1)
+ , (IE | AE , 'xer_ca_ok' , 0, l(20), 1)
+ , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 2)
+ , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 3)
+ , (IN | AE , 'dest3_o({})' , 0, 0, 2)
+ , (IN | AE , 'dest2_o({})' , 0, 0, 4)
+ , (IN | AE , 'dest1_o({})' , 0, 0, 64)
]
)
blockLogical0.state.cfg.etesian.uniformDensity = True
shiftrot0 = af.getCell( 'shiftrot0', CRL.Catalog.State.Views )
blockShiftrot0 = Block.create \
( shiftrot0
- , ioPins=[ (IN , 'clk' , l(805.0) )
- , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_input_cr' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_is_32bit' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_is_signed' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_oe_oe' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_oe_oe_ok' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_output_carry' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_output_cr' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc_ok' , 0, l(20), 1)
- , (IW | AB, 'rst' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_shift_rot0_input_carry({})' , 0, l(20), 2)
- , (IW | AB, 'src4_i({})' , 0, l(10), 2)
- , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4)
- , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 4)
- , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 3)
- , (IW | AB, 'oper_i_alu_shift_rot0_insn_type({})' , 0, l(20), 7)
- , (IW | AB, 'oper_i_alu_shift_rot0_fn_unit({})' , 0, l(20), 11)
- , (IW | AB, 'oper_i_alu_shift_rot0_insn({})' , 0, l(20), 32)
- , (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm({})', 0, l(20), 64)
- , (IW | AB, 'src3_i({})' , 0, l(10), 64)
- , (IS | AB, 'src1_i({})' , 0, l(10), 64)
- , (IS | AB, 'src2_i({})' , 0, l(5), 64)
- , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
- , (IE | AE , 'cr_a_ok' , 0, l(20), 1)
- , (IE | AE , 'o_ok' , 0, l(20), 1)
- , (IE | AE , 'xer_ca_ok' , 0, l(20), 1)
- , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 4)
- , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 3)
- , (IN | AE , 'dest3_o({})' , 0, 0, 2)
- , (IN | AE , 'dest2_o({})' , 0, 0, 4)
- , (IN | AE , 'dest1_o({})' , 0, 0, 64)
+ , ioPins=[
+ (IN , 'clk' , l(805.0) )
+ , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_input_cr' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_is_32bit' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_is_signed' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_oe_oe' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_oe_oe_ok' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_output_carry' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_output_cr' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc_ok' , 0, l(20), 1)
+ , (IW | AB, 'rst' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_shift_rot0_input_carry({})' , 0, l(20), 2)
+ , (IW | AB, 'src4_i({})' , 0, l(10), 2)
+ , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4)
+ , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 4)
+ , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 3)
+ , (IW | AB, 'oper_i_alu_shift_rot0_insn_type({})' , 0, l(20), 7)
+ , (IW | AB, 'oper_i_alu_shift_rot0_fn_unit({})' , 0, l(20), 11)
+ , (IW | AB, 'oper_i_alu_shift_rot0_insn({})' , 0, l(20), 32)
+ , (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm({})', 0, l(20), 64)
+ , (IW | AB, 'src3_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src1_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src2_i({})' , 0, l(5), 64)
+ , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
+ , (IE | AE , 'cr_a_ok' , 0, l(20), 1)
+ , (IE | AE , 'o_ok' , 0, l(20), 1)
+ , (IE | AE , 'xer_ca_ok' , 0, l(20), 1)
+ , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 4)
+ , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 3)
+ , (IN | AE , 'dest3_o({})' , 0, 0, 2)
+ , (IN | AE , 'dest2_o({})' , 0, 0, 4)
+ , (IN | AE , 'dest1_o({})' , 0, 0, 64)
]
)
blockShiftrot0.state.cfg.etesian.uniformDensity = True
spr0 = af.getCell( 'spr0', CRL.Catalog.State.Views )
blockSpr0 = Block.create \
( spr0
- , ioPins=[ (IN , 'clk' , l(805.0) )
- , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_spr0_is_32bit' , 0, l(20), 1)
- , (IW | AB, 'rst' , 0, l(20), 1)
- , (IW | AB, 'src4_i' , 0, l(10), 1)
- , (IW | AB, 'src5_i({})' , 0, l(10), 2)
- , (IW | AB, 'src6_i({})' , 0, l(10), 2)
- , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 6)
- , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 6)
- , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 6)
- , (IW | AB, 'oper_i_alu_spr0_insn_type({})', 0, l(20), 7)
- , (IW | AB, 'oper_i_alu_spr0_fn_unit({})' , 0, l(20), 11)
- , (IW | AB, 'oper_i_alu_spr0_insn({})' , 0, l(20), 32)
- , (IW | AB, 'src3_i({})' , 0, l(10), 64)
- , (IS | AB, 'src1_i({})' , 0, l(10), 64)
- , (IS | AB, 'src2_i({})' , 0, l(5), 64)
- , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
- , (IE | AE , 'dest4_o' , 0, l(20), 1)
- , (IE | AE , 'fast1_ok' , 0, l(20), 1)
- , (IE | AE , 'o_ok' , 0, l(20), 1)
- , (IE | AE , 'spr1_ok' , 0, l(20), 1)
- , (IE | AE , 'xer_ca_ok' , 0, l(20), 1)
- , (IE | AE , 'xer_ov_ok' , 0, l(20), 1)
- , (IE | AE , 'xer_so_ok' , 0, l(20), 1)
- , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 6)
- , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 6)
- , (IN | AE , 'dest5_o({})' , 0, 0, 2)
- , (IN | AE , 'dest6_o({})' , 0, 0, 2)
- , (IE | AE , 'dest3_o({})' , 0, l(20), 64)
- , (IE | AE , 'dest2_o({})' , 0, l(20), 64)
- , (IE | AE , 'dest1_o({})' , 0, l(20), 64)
+ , ioPins=[
+ (IN , 'clk' , l(805.0) )
+ , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_spr0_is_32bit' , 0, l(20), 1)
+ , (IW | AB, 'rst' , 0, l(20), 1)
+ , (IW | AB, 'src4_i' , 0, l(10), 1)
+ , (IW | AB, 'src5_i({})' , 0, l(10), 2)
+ , (IW | AB, 'src6_i({})' , 0, l(10), 2)
+ , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 6)
+ , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 6)
+ , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 6)
+ , (IW | AB, 'oper_i_alu_spr0_insn_type({})', 0, l(20), 7)
+ , (IW | AB, 'oper_i_alu_spr0_fn_unit({})' , 0, l(20), 11)
+ , (IW | AB, 'oper_i_alu_spr0_insn({})' , 0, l(20), 32)
+ , (IW | AB, 'src3_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src1_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src2_i({})' , 0, l(5), 64)
+ , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
+ , (IE | AE , 'dest4_o' , 0, l(20), 1)
+ , (IE | AE , 'fast1_ok' , 0, l(20), 1)
+ , (IE | AE , 'o_ok' , 0, l(20), 1)
+ , (IE | AE , 'spr1_ok' , 0, l(20), 1)
+ , (IE | AE , 'xer_ca_ok' , 0, l(20), 1)
+ , (IE | AE , 'xer_ov_ok' , 0, l(20), 1)
+ , (IE | AE , 'xer_so_ok' , 0, l(20), 1)
+ , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 6)
+ , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 6)
+ , (IN | AE , 'dest5_o({})' , 0, 0, 2)
+ , (IN | AE , 'dest6_o({})' , 0, 0, 2)
+ , (IE | AE , 'dest3_o({})' , 0, l(20), 64)
+ , (IE | AE , 'dest2_o({})' , 0, l(20), 64)
+ , (IE | AE , 'dest1_o({})' , 0, l(20), 64)
]
)
blockSpr0.state.cfg.etesian.uniformDensity = True
trap0 = af.getCell( 'trap0', CRL.Catalog.State.Views )
blockTrap0 = Block.create \
( trap0
- , ioPins=[ (IN , 'clk' , l(805.0) )
- , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
- , (IW | AB, 'oper_i_alu_trap0_is_32bit' , 0, l(20), 1)
- , (IW | AB, 'rst' , 0, l(20), 1)
- , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4)
- , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 4)
- , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 5)
- , (IW | AB, 'oper_i_alu_trap0_traptype({})' , 0, l(20), 5)
- , (IW | AB, 'oper_i_alu_trap0_insn_type({})', 0, l(20), 7)
- , (IW | AB, 'oper_i_alu_trap0_fn_unit({})' , 0, l(20), 11)
- , (IW | AB, 'oper_i_alu_trap0_trapaddr({})' , 0, l(20), 13)
- , (IW | AB, 'oper_i_alu_trap0_insn({})' , 0, l(20), 32)
- , (IW | AB, 'oper_i_alu_trap0_cia({})' , 0, l(20), 64)
- , (IW | AB, 'oper_i_alu_trap0_msr({})' , 0, l(20), 64)
- , (IW | AB, 'src3_i({})' , 0, l(10), 64)
- , (IS | AB, 'src4_i({})' , 0, l(10), 64)
- , (IS | AB, 'src1_i({})' , 0, l(10), 64)
- , (IS | AB, 'src2_i({})' , 0, l(5), 64)
- , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
- , (IE | AE , 'fast1_ok' , 0, l(20), 1)
- , (IE | AE , 'fast2_ok' , 0, l(20), 1)
- , (IE | AE , 'msr_ok' , 0, l(20), 1)
- , (IE | AE , 'nia_ok' , 0, l(20), 1)
- , (IE | AE , 'o_ok' , 0, l(20), 1)
- , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 4)
- , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 5)
- , (IN | AE , 'dest5_o({})' , 0, l(10), 64)
- , (IN | AE , 'dest4_o({})' , 0, l(10), 64)
- , (IE | AE , 'dest3_o({})' , 0, l(10), 64)
- , (IE | AE , 'dest2_o({})' , 0, l(10), 64)
- , (IE | AE , 'dest1_o({})' , 0, l(10), 64)
+ , ioPins=[
+ (IN , 'clk' , l(805.0) )
+ , (IW | AB, 'cu_issue_i' , 0, l(20), 1)
+ , (IW | AB, 'oper_i_alu_trap0_is_32bit' , 0, l(20), 1)
+ , (IW | AB, 'rst' , 0, l(20), 1)
+ , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4)
+ , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 4)
+ , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 5)
+ , (IW | AB, 'oper_i_alu_trap0_traptype({})' , 0, l(20), 5)
+ , (IW | AB, 'oper_i_alu_trap0_insn_type({})', 0, l(20), 7)
+ , (IW | AB, 'oper_i_alu_trap0_fn_unit({})' , 0, l(20), 11)
+ , (IW | AB, 'oper_i_alu_trap0_trapaddr({})' , 0, l(20), 13)
+ , (IW | AB, 'oper_i_alu_trap0_insn({})' , 0, l(20), 32)
+ , (IW | AB, 'oper_i_alu_trap0_cia({})' , 0, l(20), 64)
+ , (IW | AB, 'oper_i_alu_trap0_msr({})' , 0, l(20), 64)
+ , (IW | AB, 'src3_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src4_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src1_i({})' , 0, l(10), 64)
+ , (IS | AB, 'src2_i({})' , 0, l(5), 64)
+ , (IE | AE , 'cu_busy_o' , 0, l(20), 1)
+ , (IE | AE , 'fast1_ok' , 0, l(20), 1)
+ , (IE | AE , 'fast2_ok' , 0, l(20), 1)
+ , (IE | AE , 'msr_ok' , 0, l(20), 1)
+ , (IE | AE , 'nia_ok' , 0, l(20), 1)
+ , (IE | AE , 'o_ok' , 0, l(20), 1)
+ , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 4)
+ , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 5)
+ , (IN | AE , 'dest5_o({})' , 0, l(10), 64)
+ , (IN | AE , 'dest4_o({})' , 0, l(10), 64)
+ , (IE | AE , 'dest3_o({})' , 0, l(10), 64)
+ , (IE | AE , 'dest2_o({})' , 0, l(10), 64)
+ , (IE | AE , 'dest1_o({})' , 0, l(10), 64)
]
)
blockTrap0.state.cfg.etesian.uniformDensity = True
blockFast.state.cfg.katana.searchHalo = 1
blockFast.state.useSpares = False
#rvalue = blockFast.build()
-
+
cellInt = af.getCell( 'int', CRL.Catalog.State.Views )
blockInt = Block.create \
( cellInt
( issuer
, ioPins=[]
)
-
+
# Cell width:
#
# ================ =================
# int ?
# pdecode ?
# ================ =================
-
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_0_alu0'
- , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_1_branch0'
- , Transformation( l(2700), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_2_cr0'
- , Transformation( l(4950), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_3_ldst0'
- , Transformation( l(6400), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_4_logical0'
- , Transformation( l(8000), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_5_mul0'
- , Transformation( l(10300), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_6_shiftrot0'
- , Transformation( l(20400), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_7_spr0'
- , Transformation( l(23250), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2031_fus.subckt_8_trap0'
- , Transformation( l(25300), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2030_fast'
- , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2032_int'
- , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
- blockIssuer.useBlockInstance( 'subckt_1008_core.subckt_2034_pdecode2'
- , Transformation( l(1000), l(4000), Transformation.Orientation.ID ))
+
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_0_alu0',
+ Transformation( l(1000), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_1_branch0',
+ Transformation( l(2700), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_2_cr0' ,
+ Transformation( l(4950), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_3_div0' ,
+ Transformation( l(27000), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_4_ldst0' ,
+ Transformation( l(6400), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_5_logical0' ,
+ Transformation( l(8000), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_6_mul0' ,
+ Transformation( l(10300), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_7_shiftrot0' ,
+ Transformation( l(20400), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_8_spr0' ,
+ Transformation( l(23250), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2227_fus.subckt_0_trap0' ,
+ Transformation( l(25300), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2030_fast' ,
+ Transformation( l(1000), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2032_int' ,
+ Transformation( l(1000), l(4000),
+ Transformation.Orientation.ID ))
+ blockIssuer.useBlockInstance(
+ 'subckt_1150_core.subckt_2034_pdecode2' ,
+ Transformation( l(1000), l(4000),
+ Transformation.Orientation.ID ))
+
blockIssuer.state.cfg.etesian.uniformDensity = True
blockIssuer.state.cfg.etesian.aspectRatio = 1.0
blockIssuer.state.cfg.etesian.spaceMargin = 0.07
blockIssuer.state.cfg.katana.searchHalo = 10000
blockIssuer.state.fixedHeight = l(15000)
- blockIssuer.state.fixedWidth = l(29550)
+ blockIssuer.state.fixedWidth = l(31550)
blockIssuer.state.useSpares = False
blockIssuer.state.editor = editor
rvalue = blockIssuer.build()
sys.stdout.flush()
sys.stderr.flush()
-
+
return rvalue
projects / soclayout.git / commitdiff