convert to more general base classes, start support for FP64

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 3b60567144c5f431f9ac9e3d682c672a4ecf76e1..7d98eb6be8c53e1e0b2967a60b4dce04057384fc 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -22,7 +22,7 @@ class FPMUL(FPBase):
         # Latches
         a = FPNum(self.width)
         b = FPNum(self.width)
-        z = FPNum(self.width, 24)
+        z = FPNum(self.width, False)
 
         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 
@@ -259,4 +259,4 @@ always @(posedge clk)
       s_output_z_stb <= 0;
     end
  end
- """
\ No newline at end of file
+ """

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 01bf3faa1398b89ebe98dcedc6f8500a7e20da33..c10e5d9bd370ee60c5d39745817e831c06c6a238 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -17,22 +17,28 @@ class FPNum:
         (m[-1]) is effectively a carry-overflow.  The other three are
         guard (m[2]), round (m[1]), and sticky (m[0])
     """
-    def __init__(self, width, m_width=None):
+    def __init__(self, width, m_extra=True):
         self.width = width
-        if m_width is None:
-            m_width = width - 5 # mantissa extra bits (top,guard,round)
+        m_width = {32: 24, 64: 53}[width]
+        e_width = {32: 10, 64: 13}[width]
+        e_max = 1<<(e_width-3)
+        if m_extra:
+            # mantissa extra bits (top,guard,round)
+            m_width += 3
+        print (m_width, e_width, e_max)
         self.m_width = m_width
+        self.e_width = e_width
         self.v = Signal(width)      # Latched copy of value
         self.m = Signal(m_width)    # Mantissa
-        self.e = Signal((10, True)) # Exponent: 10 bits, signed
+        self.e = Signal((e_width, True)) # Exponent: 10 bits, signed
         self.s = Signal()           # Sign bit
 
         self.mzero = Const(0, (m_width, False))
         self.m1s = Const(-1, (m_width, False))
-        self.P128 = Const(128, (10, True))
-        self.P127 = Const(127, (10, True))
-        self.N127 = Const(-127, (10, True))
-        self.N126 = Const(-126, (10, True))
+        self.P128 = Const(e_max, (e_width, True))
+        self.P127 = Const(e_max-1, (e_width, True))
+        self.N127 = Const(-(e_max-1), (e_width, True))
+        self.N126 = Const(-(e_max-2), (e_width, True))
 
     def decode(self, v):
         """ decodes a latched value into sign / exponent / mantissa

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index ddd7ad07710994aff1dacaf77e2fddb7e43010c1..efb0c8bfa1de2bd8526d213e8426f934841f112a 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -26,7 +26,7 @@ class FPADD(FPBase):
         # Latches
         a = FPNum(self.width)
         b = FPNum(self.width)
-        z = FPNum(self.width, 24)
+        z = FPNum(self.width, False)
 
         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 

diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
index 1cbabd9ed03e925964cba15882726a186718ef79..918713a0bbd94d9d49a1bdd3db412df618b6ee12 100644 (file)
--- a/src/add/nmigen_div_experiment.py
+++ b/src/add/nmigen_div_experiment.py
@@ -42,9 +42,9 @@ class FPDIV(FPBase):
         m = Module()
 
         # Latches
-        a = FPNum(self.width, 24)
-        b = FPNum(self.width, 24)
-        z = FPNum(self.width, 24)
+        a = FPNum(self.width, False)
+        b = FPNum(self.width, False)
+        z = FPNum(self.width, False)
 
         div = Div(51)