add debug info of what instruction was executed and Asserted

diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py
index ccb41a76faf9642fb0efa578272533cd6a244ee9..ef90ddca771c6aa7dc0b3536c3e471e76c5ee3e0 100644 (file)
--- a/src/soc/cr/test/test_pipe_caller.py
+++ b/src/soc/cr/test/test_pipe_caller.py
@@ -186,6 +186,7 @@ class TestRunner(FHDLTestCase):
                         cr_expected = simulator.cr.get_range().value
                         cr_real = yield alu.n.data_o.cr
                         msg = f"real: {cr_expected:x}, actual: {cr_real:x}"
+                        msg += " code: %s" % code
                         self.assertEqual(cr_expected, cr_real, msg)
 
         sim.add_sync_process(process)