intel/compiler: Lower ffma on Gen4 and Gen5

flrp32 is also a 3-source instruction, but there is another pending
series that handles that for Gen4 and Gen5.

v2: Rebase on "intel/compiler: Don't have sepearate, per-Gen
nir_options"

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index f1acf83888768350737d989cdb66b86fc0bdc888..44296083711e251e151ded7c07190f6800114eed 100644 (file)
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -183,6 +183,10 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
             nir_options->lower_flrp32 = true;
          }
       }
+
+      /* Prior to Gen6, there are no three source operations. */
+      nir_options->lower_ffma = devinfo->gen < 6;
+
       nir_options->lower_int64_options = int64_options;
       nir_options->lower_doubles_options = fp64_options;
       compiler->glsl_compiler_options[i].NirOptions = nir_options;