add inout spec

diff --git a/src/spec/gen.py b/src/spec/gen.py
index 74abac9eecc43b501e38a334b75ed8b15277dfc4..2f859eb278ef7a07977056c3ab3d6199e1e5f034 100644 (file)
--- a/src/spec/gen.py
+++ b/src/spec/gen.py
@@ -7,9 +7,9 @@ def specgen(pth, pinouts, bankspec, fixedpins):
         for reading in by pinmux
     """
     pth = pth or ''
-    print bankspec.keys()
-    print pinouts.keys()
-    print fixedpins.keys()
+    #print bankspec.keys()
+    #print pinouts.keys()
+    #print fixedpins.keys()
     if not os.path.exists(pth):
         os.makedirs(pth)
     with open(os.path.join(pth, 'interfaces.txt'), 'w') as f:
@@ -25,7 +25,7 @@ def specgen(pth, pinouts, bankspec, fixedpins):
                         g.write("%s\t%s\n" % (k_, fntype))
                 else:
                     for pinname in s0.pingroup:
-                        fntype = 'inout'
+                        fntype = s0.fntype.get(pinname, 'inout')
                         k_ = k.lower()
                         pn = pinname.lower()
                         g.write("%s_%s\t%s\n" % (k_, pn, fntype))

diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py
index 4e843feb72405c116bc180e999cc31709cc4bccc..6565bb6c5abe7d4a53846b9dcb3d63cfe1f515ab 100644 (file)
--- a/src/spec/interfaces.py
+++ b/src/spec/interfaces.py
@@ -39,6 +39,22 @@ class Pins(object):
 
     def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
              spec=None, limit=None, origsuffix=None):
+
+        # function type can be in, out or inout, represented by - + *
+        # strip function type out of each pin name
+        self.fntype = {}
+        for i in range(len(pingroup)):
+            pname = pingroup[i]
+            if not pname:
+                continue
+            fntype = pname[-1]
+            if fntype not in '+-*':
+                continue
+            pname = pname[:-1]
+            fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
+            self.fntype[pname] = fntype
+            pingroup[i] = pname
+
         self.fname = fname
         self.pingroup = pingroup
         self.bankspec = bankspec
@@ -47,8 +63,9 @@ class Pins(object):
         self.bank = bank
         self.mux = mux
 
+        # create consistent name suffixes
         pingroup = namesuffix(fname, suffix, pingroup)
-        suffix = ''
+        suffix = '' # hack
 
         res = {}
         names = {}
@@ -88,50 +105,50 @@ class Pins(object):
 
 
 def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
-    i2spins = ['MCK', 'BCK', 'LRCK', 'DI']
+    i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-']
     for i in range(4):
-        i2spins.append("DO%d" % i)
+        i2spins.append("DO%d+" % i)
     return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
 def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
-    emmcpins = ['CMD', 'CLK']
+    emmcpins = ['CMD+', 'CLK+']
     for i in range(8):
-        emmcpins.append("D%d" % i)
+        emmcpins.append("D%d*" % i)
     return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
                 start=None, limit=None):
-    sdmmcpins = ['CMD', 'CLK']
+    sdmmcpins = ['CMD+', 'CLK+']
     for i in range(4):
-        sdmmcpins.append("D%d" % i)
+        sdmmcpins.append("D%d*" % i)
     sdmmcpins = sdmmcpins[start:limit]
     return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
-    spipins = ['CLK', 'NSS', 'MOSI', 'MISO', 'NSS']
+    spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
     return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
-    spipins = ['CK', 'NSS', 'IO0', 'IO1', 'IO2', 'IO3']
+    spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
     return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
 def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
-    spipins = ['SDA', 'SCL']
+    spipins = ['SDA*', 'SCL*']
     return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
-    uartpins = ['MS', 'DI', 'DO', 'CK']
-    return Pins('JTAG', uartpins, bankspec, suffix, offs, bank, mux, spec,
+    jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
+    return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
-    uartpins = ['TX', 'RX']
+    uartpins = ['TX+', 'RX-']
     return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
@@ -145,100 +162,100 @@ def namesuffix(name, suffix, namelist):
     return names
 
 def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
-    ulpipins = ['CK', 'DIR', 'STP', 'NXT']
+    ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
     for i in range(8):
-        ulpipins.append('D%d' % i)
+        ulpipins.append('D%d*' % i)
     return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
-    uartpins = ['TX', 'RX', 'CTS', 'RTS']
+    uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
     return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
-    ttlpins = ['CK', 'DE', 'HS', 'VS']
+    ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
     for i in range(24):
-        ttlpins.append("D%d" % i)
+        ttlpins.append("D%d+" % i)
     return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
     buspins = []
     for i in range(4):
-        buspins.append("ERXD%d" % i)
+        buspins.append("ERXD%d-" % i)
     for i in range(4):
-        buspins.append("ETXD%d" % i)
-    buspins += ['ERXCK', 'ERXERR', 'ERXDV',
-                'EMDC', 'EMDIO',
-                'ETXEN', 'ETXCK', 'ECRS',
-                'ECOL', 'ETXERR']
+        buspins.append("ETXD%d+" % i)
+    buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
+                'EMDC+', 'EMDIO*',
+                'ETXEN+', 'ETXCK+', 'ECRS-',
+                'ECOL+', 'ETXERR+']
     return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     buspins = []
     for i in range(8):
-        buspins.append("AD%d" % i)
+        buspins.append("AD%d*" % i)
     for i in range(2):
-        buspins.append("CS%d" % i)
-    buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK',
+        buspins.append("CS%d+" % i)
+    buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
                 'A0', 'A1', 'TS', 'TBST',
                 'TSIZ0', 'TSIZ1']
     for i in range(4):
         buspins.append("BWE%d" % i)
     for i in range(2,6):
-        buspins.append("CS%d" % i)
+        buspins.append("CS%d+" % i)
     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
 def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     buspins = []
     for i in range(8,32):
-        buspins.append("AD%d" % i)
+        buspins.append("AD%d*" % i)
     return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
 def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
     buspins = []
     for i in range(16):
-        buspins.append("SDRDQM%d" % i)
+        buspins.append("SDRDQM%d*" % i)
     for i in range(12):
-        buspins.append("SDRAD%d" % i)
+        buspins.append("SDRAD%d+" % i)
     for i in range(8):
-        buspins.append("SDRDQ%d" % i)
+        buspins.append("SDRDQ%d+" % i)
     for i in range(3):
-        buspins.append("SDRCS%d#" % i)
+        buspins.append("SDRCS%d#+" % i)
     for i in range(2):
-        buspins.append("SDRDQ%d" % i)
+        buspins.append("SDRDQ%d+" % i)
     for i in range(2):
-        buspins.append("SDRBA%d" % i)
-    buspins += ['SDRCKE', 'SDRRAS#', 'SDRCAS#', 'SDRWE#',
-                'SDRRST']
+        buspins.append("SDRBA%d+" % i)
+    buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
+                'SDRRST+']
     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
     buspins = []
     for i in range(3,6):
-        buspins.append("SDRCS%d#" % i)
+        buspins.append("SDRCS%d#+" % i)
     for i in range(8,32):
-        buspins.append("SDRDQ%d" % i)
+        buspins.append("SDRDQ%d*" % i)
     return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
                 origsuffix=suffix)
 
 def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
     buspins = []
     for i in range(8):
-        buspins.append("MCUD%d" % i)
+        buspins.append("MCUD%d*" % i)
     for i in range(8):
-        buspins.append("MCUAD%d" % (i+8))
+        buspins.append("MCUAD%d+" % (i+8))
     for i in range(6):
-        buspins.append("MCUCS%d" % i)
+        buspins.append("MCUCS%d+" % i)
     for i in range(2):
-        buspins.append("MCUNRB%d" % i)
-    buspins += ['MCUCD', 'MCURD', 'MCUWR', 'MCUCLE', 'MCUALE',
-                'MCURST']
+        buspins.append("MCUNRB%d+" % i)
+    buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
+                'MCURST+']
     return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
@@ -246,19 +263,19 @@ def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
              spec=None):
     gpiopins = []
     for i in range(gpiooffs, gpiooffs+gpionum):
-        gpiopins.append("%s%d" % (bank, i))
+        gpiopins.append("%s%d*" % (bank, i))
     return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
     gpiopins = []
     for i in range(gpiooffs, gpiooffs+gpionum):
-        gpiopins.append("%d" % (i))
+        gpiopins.append("%d*" % (i))
     return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def pwm(bankspec, suffix, offs, bank, mux=1, spec=None):
-    return Pins('PWM', ['', ], bankspec, suffix, offs, bank, mux, spec,
+    return Pins('PWM', ['+', ], bankspec, suffix, offs, bank, mux, spec,
                 origsuffix=suffix)
 
 def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):