Turned the add_0 verilog state into nmigen

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 1b9af6705293edf5ea24d3ad6c49f44edca530d9..119b13568305776e5ccd352a71399f0e08d719f0 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -183,6 +183,22 @@ class FPADD:
                         m.d.sync += b_e.eq(-126) # limit b exponent
                     with m.Else():
                         m.d.sync += b_m[26].eq(1) # set highest mantissa bit
+
+            with m.State("add_0"):
+              m.next = "add_1"
+              m.d.sync += z_e.eq(a_e)
+              with m.If(a_s == b_s):
+                m.d.sync += [
+                tot.eq(a_m + b_m),
+                z_s.eq(a_s)]
+              with m.Else(a_m >= b_m):
+                m.d.sync += [
+                tot.eq(a_m - b_m),
+                z_s.eq(a_s)]
+              with m.Else():
+                m.sync += [
+                tot.eq(b_m - a_m),
+                z_s.eq(b_s)]
         return m
 
 """