updated test_issuer.il to include new names

diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il
index 21092283f1384d71948541fa8fc9e1da83f446aa..7cfde61727a018b856c1ee65476ed937eefcb0e1 100644 (file)
--- a/experiments9/non_generated/test_issuer.il
+++ b/experiments9/non_generated/test_issuer.il
@@ -1,7 +1,7 @@
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec19"
 module \dec19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -15,7 +15,7 @@ module \dec19
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -47,7 +47,7 @@ module \dec19
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -122,7 +122,7 @@ module \dec19
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -130,7 +130,7 @@ module \dec19
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -147,20 +147,20 @@ module \dec19
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -170,7 +170,7 @@ module \dec19
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -178,13 +178,13 @@ module \dec19
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -192,102 +192,102 @@ module \dec19
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 10 \opcode_switch
   process $group_0
     assign \opcode_switch 10'0000000000
     assign \opcode_switch \opcode_in [10:1]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch$1
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \function_unit 11'00000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \function_unit 11'00000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \function_unit 11'00000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \function_unit 11'00010000000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00000000010
     end
@@ -295,54 +295,54 @@ module \dec19
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \form 5'01001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \form 5'01001
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'00111
     end
@@ -350,54 +350,54 @@ module \dec19
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \internal_op 7'0101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \internal_op 7'1000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \internal_op 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \internal_op 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \internal_op 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \internal_op 7'0100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \internal_op 7'1000110
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0000000
     end
@@ -405,54 +405,54 @@ module \dec19
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \in1_sel 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \in1_sel 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \in1_sel 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \in1_sel 3'011
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'000
     end
@@ -460,54 +460,54 @@ module \dec19
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \in2_sel 4'1100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \in2_sel 4'1100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \in2_sel 4'1100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \in2_sel 4'1100
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0000
     end
@@ -515,54 +515,54 @@ module \dec19
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \in3_sel 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
     end
@@ -570,54 +570,54 @@ module \dec19
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \out_sel 2'11
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \out_sel 2'11
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \out_sel 2'11
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \out_sel 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'00
     end
@@ -625,54 +625,54 @@ module \dec19
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \cr_in 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \cr_in 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \cr_in 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \cr_in 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \cr_in 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \cr_in 3'000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
     end
@@ -680,54 +680,54 @@ module \dec19
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \cr_out 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \cr_out 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \cr_out 3'000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'000
     end
@@ -735,54 +735,54 @@ module \dec19
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \ldst_len 4'0000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0000
     end
@@ -790,54 +790,54 @@ module \dec19
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \upd 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
     end
@@ -845,54 +845,54 @@ module \dec19
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \rc_sel 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'10
     end
@@ -900,54 +900,54 @@ module \dec19
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \cry_in 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
     end
@@ -955,48 +955,48 @@ module \dec19
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \asmcode 8'01101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \asmcode 8'00100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \asmcode 8'00100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \asmcode 8'00100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \asmcode 8'00101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \asmcode 8'00101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \asmcode 8'00101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \asmcode 8'00101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \asmcode 8'00101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \asmcode 8'00010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \asmcode 8'00010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \asmcode 8'00011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \asmcode 8'01001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \asmcode 8'10001111
     end
@@ -1004,54 +1004,54 @@ module \dec19
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \inv_a 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
     end
@@ -1059,54 +1059,54 @@ module \dec19
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \inv_out 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
     end
@@ -1114,54 +1114,54 @@ module \dec19
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \cry_out 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
     end
@@ -1169,54 +1169,54 @@ module \dec19
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \br 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
     end
@@ -1224,54 +1224,54 @@ module \dec19
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \sgn_ext 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
     end
@@ -1279,54 +1279,54 @@ module \dec19
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \rsrv 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
     end
@@ -1334,54 +1334,54 @@ module \dec19
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \is_32b 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
     end
@@ -1389,54 +1389,54 @@ module \dec19
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \sgn 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'0
     end
@@ -1444,54 +1444,54 @@ module \dec19
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \lk 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \lk 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \lk 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \lk 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
     end
@@ -1499,54 +1499,54 @@ module \dec19
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000000000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100000001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010000001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0100100001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011100001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000100001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0111000001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0110100001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0011000001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000010000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'1000110000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0010010110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 10'0000010010
         assign \sgl_pipe 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'1
     end
@@ -1561,7 +1561,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec30"
 module \dec30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -1575,7 +1575,7 @@ module \dec30
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -1607,7 +1607,7 @@ module \dec30
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -1682,7 +1682,7 @@ module \dec30
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -1690,7 +1690,7 @@ module \dec30
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -1707,20 +1707,20 @@ module \dec30
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -1730,7 +1730,7 @@ module \dec30
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -1738,13 +1738,13 @@ module \dec30
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -1752,44 +1752,44 @@ module \dec30
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 4 \opcode_switch
   process $group_0
     assign \opcode_switch 4'0000
@@ -1798,36 +1798,36 @@ module \dec30
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \function_unit 11'00000001000
     end
@@ -1835,36 +1835,36 @@ module \dec30
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \form 5'10100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \form 5'10100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \form 5'10101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \form 5'10101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \form 5'10100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \form 5'10100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \form 5'10100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \form 5'10100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \form 5'10100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \form 5'10100
     end
@@ -1872,36 +1872,36 @@ module \dec30
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \internal_op 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \internal_op 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \internal_op 7'0111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \internal_op 7'0111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \internal_op 7'0111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \internal_op 7'0111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \internal_op 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \internal_op 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \internal_op 7'0111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \internal_op 7'0111010
     end
@@ -1909,36 +1909,36 @@ module \dec30
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \in1_sel 3'000
     end
@@ -1946,36 +1946,36 @@ module \dec30
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \in2_sel 4'0001
     end
@@ -1983,36 +1983,36 @@ module \dec30
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \in3_sel 2'01
     end
@@ -2020,36 +2020,36 @@ module \dec30
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \out_sel 2'10
     end
@@ -2057,36 +2057,36 @@ module \dec30
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \cr_in 3'000
     end
@@ -2094,36 +2094,36 @@ module \dec30
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \cr_out 3'001
     end
@@ -2131,36 +2131,36 @@ module \dec30
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \ldst_len 4'0000
     end
@@ -2168,36 +2168,36 @@ module \dec30
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \upd 2'00
     end
@@ -2205,36 +2205,36 @@ module \dec30
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \rc_sel 2'10
     end
@@ -2242,36 +2242,36 @@ module \dec30
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \cry_in 2'00
     end
@@ -2279,36 +2279,36 @@ module \dec30
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \asmcode 8'10010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \asmcode 8'10010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \asmcode 8'10010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \asmcode 8'10010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \asmcode 8'10010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \asmcode 8'10010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \asmcode 8'10010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \asmcode 8'10010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \asmcode 8'10010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \asmcode 8'10010001
     end
@@ -2316,36 +2316,36 @@ module \dec30
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \inv_a 1'0
     end
@@ -2353,36 +2353,36 @@ module \dec30
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \inv_out 1'0
     end
@@ -2390,36 +2390,36 @@ module \dec30
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \cry_out 1'0
     end
@@ -2427,36 +2427,36 @@ module \dec30
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \br 1'0
     end
@@ -2464,36 +2464,36 @@ module \dec30
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \sgn_ext 1'0
     end
@@ -2501,36 +2501,36 @@ module \dec30
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \rsrv 1'0
     end
@@ -2538,36 +2538,36 @@ module \dec30
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \is_32b 1'0
     end
@@ -2575,36 +2575,36 @@ module \dec30
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \sgn 1'0
     end
@@ -2612,36 +2612,36 @@ module \dec30
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \lk 1'0
     end
@@ -2649,36 +2649,36 @@ module \dec30
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'0111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 4'1001
         assign \sgl_pipe 1'0
     end
@@ -2688,7 +2688,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub10"
 module \dec_sub10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -2702,7 +2702,7 @@ module \dec_sub10
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -2734,7 +2734,7 @@ module \dec_sub10
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -2809,7 +2809,7 @@ module \dec_sub10
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -2817,7 +2817,7 @@ module \dec_sub10
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -2834,20 +2834,20 @@ module \dec_sub10
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -2857,7 +2857,7 @@ module \dec_sub10
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -2865,13 +2865,13 @@ module \dec_sub10
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -2879,44 +2879,44 @@ module \dec_sub10
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -2925,36 +2925,36 @@ module \dec_sub10
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \function_unit 11'00000000010
     end
@@ -2962,36 +2962,36 @@ module \dec_sub10
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \form 5'10001
     end
@@ -2999,36 +2999,36 @@ module \dec_sub10
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \internal_op 7'0000010
     end
@@ -3036,36 +3036,36 @@ module \dec_sub10
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in1_sel 3'001
     end
@@ -3073,36 +3073,36 @@ module \dec_sub10
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in2_sel 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in2_sel 4'0000
     end
@@ -3110,36 +3110,36 @@ module \dec_sub10
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in3_sel 2'00
     end
@@ -3147,36 +3147,36 @@ module \dec_sub10
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \out_sel 2'01
     end
@@ -3184,36 +3184,36 @@ module \dec_sub10
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_in 3'000
     end
@@ -3221,36 +3221,36 @@ module \dec_sub10
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_out 3'001
     end
@@ -3258,36 +3258,36 @@ module \dec_sub10
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \ldst_len 4'0000
     end
@@ -3295,36 +3295,36 @@ module \dec_sub10
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \upd 2'00
     end
@@ -3332,36 +3332,36 @@ module \dec_sub10
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rc_sel 2'10
     end
@@ -3369,36 +3369,36 @@ module \dec_sub10
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_in 2'10
     end
@@ -3406,36 +3406,36 @@ module \dec_sub10
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \asmcode 8'00000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \asmcode 8'00001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'00000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'00000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'00000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \asmcode 8'00000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'00001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \asmcode 8'00001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \asmcode 8'00001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \asmcode 8'00001110
     end
@@ -3443,36 +3443,36 @@ module \dec_sub10
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_a 1'0
     end
@@ -3480,36 +3480,36 @@ module \dec_sub10
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_out 1'0
     end
@@ -3517,36 +3517,36 @@ module \dec_sub10
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_out 1'1
     end
@@ -3554,36 +3554,36 @@ module \dec_sub10
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \br 1'0
     end
@@ -3591,36 +3591,36 @@ module \dec_sub10
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn_ext 1'0
     end
@@ -3628,36 +3628,36 @@ module \dec_sub10
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rsrv 1'0
     end
@@ -3665,36 +3665,36 @@ module \dec_sub10
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \is_32b 1'0
     end
@@ -3702,36 +3702,36 @@ module \dec_sub10
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn 1'0
     end
@@ -3739,36 +3739,36 @@ module \dec_sub10
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \lk 1'0
     end
@@ -3776,36 +3776,36 @@ module \dec_sub10
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgl_pipe 1'0
     end
@@ -3815,7 +3815,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub28"
 module \dec_sub28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -3829,7 +3829,7 @@ module \dec_sub28
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -3861,7 +3861,7 @@ module \dec_sub28
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -3936,7 +3936,7 @@ module \dec_sub28
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -3944,7 +3944,7 @@ module \dec_sub28
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -3961,20 +3961,20 @@ module \dec_sub28
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -3984,7 +3984,7 @@ module \dec_sub28
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -3992,13 +3992,13 @@ module \dec_sub28
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -4006,44 +4006,44 @@ module \dec_sub28
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -4052,36 +4052,36 @@ module \dec_sub28
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \function_unit 11'00000010000
     end
@@ -4089,36 +4089,36 @@ module \dec_sub28
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \form 5'01000
     end
@@ -4126,36 +4126,36 @@ module \dec_sub28
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \internal_op 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \internal_op 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \internal_op 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \internal_op 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \internal_op 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \internal_op 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \internal_op 7'1000011
     end
@@ -4163,36 +4163,36 @@ module \dec_sub28
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in1_sel 3'100
     end
@@ -4200,36 +4200,36 @@ module \dec_sub28
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in2_sel 4'0001
     end
@@ -4237,36 +4237,36 @@ module \dec_sub28
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in3_sel 2'00
     end
@@ -4274,36 +4274,36 @@ module \dec_sub28
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \out_sel 2'10
     end
@@ -4311,36 +4311,36 @@ module \dec_sub28
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cr_in 3'000
     end
@@ -4348,36 +4348,36 @@ module \dec_sub28
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cr_out 3'001
     end
@@ -4385,36 +4385,36 @@ module \dec_sub28
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \ldst_len 4'0000
     end
@@ -4422,36 +4422,36 @@ module \dec_sub28
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \upd 2'00
     end
@@ -4459,36 +4459,36 @@ module \dec_sub28
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \rc_sel 2'10
     end
@@ -4496,36 +4496,36 @@ module \dec_sub28
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cry_in 2'00
     end
@@ -4533,36 +4533,36 @@ module \dec_sub28
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'00001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'00010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'00011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \asmcode 8'00011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \asmcode 8'01000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \asmcode 8'10000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \asmcode 8'10000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \asmcode 8'10000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \asmcode 8'10000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \asmcode 8'11001010
     end
@@ -4570,36 +4570,36 @@ module \dec_sub28
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \inv_a 1'0
     end
@@ -4607,36 +4607,36 @@ module \dec_sub28
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \inv_out 1'0
     end
@@ -4644,36 +4644,36 @@ module \dec_sub28
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cry_out 1'0
     end
@@ -4681,36 +4681,36 @@ module \dec_sub28
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \br 1'0
     end
@@ -4718,36 +4718,36 @@ module \dec_sub28
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgn_ext 1'0
     end
@@ -4755,36 +4755,36 @@ module \dec_sub28
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \rsrv 1'0
     end
@@ -4792,36 +4792,36 @@ module \dec_sub28
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \is_32b 1'0
     end
@@ -4829,36 +4829,36 @@ module \dec_sub28
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgn 1'0
     end
@@ -4866,36 +4866,36 @@ module \dec_sub28
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \lk 1'0
     end
@@ -4903,36 +4903,36 @@ module \dec_sub28
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgl_pipe 1'0
     end
@@ -4942,7 +4942,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub0"
 module \dec_sub0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -4956,7 +4956,7 @@ module \dec_sub0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -4988,7 +4988,7 @@ module \dec_sub0
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -5063,7 +5063,7 @@ module \dec_sub0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -5071,7 +5071,7 @@ module \dec_sub0
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -5088,20 +5088,20 @@ module \dec_sub0
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -5111,7 +5111,7 @@ module \dec_sub0
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -5119,13 +5119,13 @@ module \dec_sub0
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -5133,44 +5133,44 @@ module \dec_sub0
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -5179,18 +5179,18 @@ module \dec_sub0
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00001000000
     end
@@ -5198,18 +5198,18 @@ module \dec_sub0
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'11000
     end
@@ -5217,18 +5217,18 @@ module \dec_sub0
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0111011
     end
@@ -5236,18 +5236,18 @@ module \dec_sub0
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'000
     end
@@ -5255,18 +5255,18 @@ module \dec_sub0
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0000
     end
@@ -5274,18 +5274,18 @@ module \dec_sub0
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'00
     end
@@ -5293,18 +5293,18 @@ module \dec_sub0
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'01
     end
@@ -5312,18 +5312,18 @@ module \dec_sub0
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'011
     end
@@ -5331,18 +5331,18 @@ module \dec_sub0
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'000
     end
@@ -5350,18 +5350,18 @@ module \dec_sub0
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0000
     end
@@ -5369,18 +5369,18 @@ module \dec_sub0
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
     end
@@ -5388,18 +5388,18 @@ module \dec_sub0
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
     end
@@ -5407,18 +5407,18 @@ module \dec_sub0
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
     end
@@ -5426,18 +5426,18 @@ module \dec_sub0
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'00011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'00011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'00011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'10011001
     end
@@ -5445,18 +5445,18 @@ module \dec_sub0
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
     end
@@ -5464,18 +5464,18 @@ module \dec_sub0
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
     end
@@ -5483,18 +5483,18 @@ module \dec_sub0
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
     end
@@ -5502,18 +5502,18 @@ module \dec_sub0
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
     end
@@ -5521,18 +5521,18 @@ module \dec_sub0
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
     end
@@ -5540,18 +5540,18 @@ module \dec_sub0
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
     end
@@ -5559,18 +5559,18 @@ module \dec_sub0
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
     end
@@ -5578,18 +5578,18 @@ module \dec_sub0
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
     end
@@ -5597,18 +5597,18 @@ module \dec_sub0
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
     end
@@ -5616,18 +5616,18 @@ module \dec_sub0
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'0
     end
@@ -5637,7 +5637,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub26"
 module \dec_sub26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -5651,7 +5651,7 @@ module \dec_sub26
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -5683,7 +5683,7 @@ module \dec_sub26
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -5758,7 +5758,7 @@ module \dec_sub26
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -5766,7 +5766,7 @@ module \dec_sub26
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -5783,20 +5783,20 @@ module \dec_sub26
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -5806,7 +5806,7 @@ module \dec_sub26
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -5814,13 +5814,13 @@ module \dec_sub26
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -5828,44 +5828,44 @@ module \dec_sub26
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -5874,51 +5874,51 @@ module \dec_sub26
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \function_unit 11'00000001000
     end
@@ -5926,51 +5926,51 @@ module \dec_sub26
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \form 5'10000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \form 5'10000
     end
@@ -5978,51 +5978,51 @@ module \dec_sub26
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \internal_op 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \internal_op 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \internal_op 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \internal_op 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \internal_op 7'0100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \internal_op 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \internal_op 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \internal_op 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \internal_op 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \internal_op 7'0111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \internal_op 7'0111101
     end
@@ -6030,51 +6030,51 @@ module \dec_sub26
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in1_sel 3'000
     end
@@ -6082,51 +6082,51 @@ module \dec_sub26
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in2_sel 4'1010
     end
@@ -6134,51 +6134,51 @@ module \dec_sub26
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in3_sel 2'01
     end
@@ -6186,51 +6186,51 @@ module \dec_sub26
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \out_sel 2'10
     end
@@ -6238,51 +6238,51 @@ module \dec_sub26
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_in 3'000
     end
@@ -6290,51 +6290,51 @@ module \dec_sub26
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_out 3'001
     end
@@ -6342,51 +6342,51 @@ module \dec_sub26
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \ldst_len 4'0000
     end
@@ -6394,51 +6394,51 @@ module \dec_sub26
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \upd 2'00
     end
@@ -6446,51 +6446,51 @@ module \dec_sub26
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rc_sel 2'10
     end
@@ -6498,51 +6498,51 @@ module \dec_sub26
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_in 2'00
     end
@@ -6550,51 +6550,51 @@ module \dec_sub26
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'00100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'00100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \asmcode 8'00100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'00100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \asmcode 8'01000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \asmcode 8'01000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \asmcode 8'01000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \asmcode 8'01000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \asmcode 8'10001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \asmcode 8'10001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \asmcode 8'10001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \asmcode 8'10001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'10001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \asmcode 8'10011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \asmcode 8'10011110
     end
@@ -6602,51 +6602,51 @@ module \dec_sub26
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_a 1'0
     end
@@ -6654,51 +6654,51 @@ module \dec_sub26
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_out 1'0
     end
@@ -6706,51 +6706,51 @@ module \dec_sub26
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_out 1'1
     end
@@ -6758,51 +6758,51 @@ module \dec_sub26
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \br 1'0
     end
@@ -6810,51 +6810,51 @@ module \dec_sub26
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn_ext 1'0
     end
@@ -6862,51 +6862,51 @@ module \dec_sub26
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rsrv 1'0
     end
@@ -6914,51 +6914,51 @@ module \dec_sub26
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \is_32b 1'0
     end
@@ -6966,51 +6966,51 @@ module \dec_sub26
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn 1'1
     end
@@ -7018,51 +7018,51 @@ module \dec_sub26
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \lk 1'0
     end
@@ -7070,51 +7070,51 @@ module \dec_sub26
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgl_pipe 1'0
     end
@@ -7124,7 +7124,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub19"
 module \dec_sub19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -7138,7 +7138,7 @@ module \dec_sub19
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -7170,7 +7170,7 @@ module \dec_sub19
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -7245,7 +7245,7 @@ module \dec_sub19
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -7253,7 +7253,7 @@ module \dec_sub19
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -7270,20 +7270,20 @@ module \dec_sub19
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -7293,7 +7293,7 @@ module \dec_sub19
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -7301,13 +7301,13 @@ module \dec_sub19
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -7315,44 +7315,44 @@ module \dec_sub19
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -7361,18 +7361,18 @@ module \dec_sub19
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00010000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \function_unit 11'10000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \function_unit 11'10000000000
     end
@@ -7380,18 +7380,18 @@ module \dec_sub19
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \form 5'01010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \form 5'01010
     end
@@ -7399,18 +7399,18 @@ module \dec_sub19
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0101101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \internal_op 7'0101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \internal_op 7'0110001
     end
@@ -7418,18 +7418,18 @@ module \dec_sub19
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in1_sel 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in1_sel 3'100
     end
@@ -7437,18 +7437,18 @@ module \dec_sub19
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in2_sel 4'0000
     end
@@ -7456,18 +7456,18 @@ module \dec_sub19
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in3_sel 2'00
     end
@@ -7475,18 +7475,18 @@ module \dec_sub19
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \out_sel 2'11
     end
@@ -7494,18 +7494,18 @@ module \dec_sub19
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_in 3'000
     end
@@ -7513,18 +7513,18 @@ module \dec_sub19
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_out 3'000
     end
@@ -7532,18 +7532,18 @@ module \dec_sub19
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \ldst_len 4'0000
     end
@@ -7551,18 +7551,18 @@ module \dec_sub19
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \upd 2'00
     end
@@ -7570,18 +7570,18 @@ module \dec_sub19
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rc_sel 2'00
     end
@@ -7589,18 +7589,18 @@ module \dec_sub19
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_in 2'00
     end
@@ -7608,18 +7608,18 @@ module \dec_sub19
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01101101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'01101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \asmcode 8'01101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \asmcode 8'01110111
     end
@@ -7627,18 +7627,18 @@ module \dec_sub19
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_a 1'0
     end
@@ -7646,18 +7646,18 @@ module \dec_sub19
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_out 1'0
     end
@@ -7665,18 +7665,18 @@ module \dec_sub19
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_out 1'0
     end
@@ -7684,18 +7684,18 @@ module \dec_sub19
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \br 1'0
     end
@@ -7703,18 +7703,18 @@ module \dec_sub19
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn_ext 1'0
     end
@@ -7722,18 +7722,18 @@ module \dec_sub19
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rsrv 1'0
     end
@@ -7741,18 +7741,18 @@ module \dec_sub19
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \is_32b 1'0
     end
@@ -7760,18 +7760,18 @@ module \dec_sub19
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn 1'0
     end
@@ -7779,18 +7779,18 @@ module \dec_sub19
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \lk 1'0
     end
@@ -7798,18 +7798,18 @@ module \dec_sub19
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgl_pipe 1'0
     end
@@ -7819,7 +7819,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub22"
 module \dec_sub22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -7833,7 +7833,7 @@ module \dec_sub22
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -7865,7 +7865,7 @@ module \dec_sub22
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -7940,7 +7940,7 @@ module \dec_sub22
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -7948,7 +7948,7 @@ module \dec_sub22
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -7965,20 +7965,20 @@ module \dec_sub22
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -7988,7 +7988,7 @@ module \dec_sub22
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -7996,13 +7996,13 @@ module \dec_sub22
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -8010,44 +8010,44 @@ module \dec_sub22
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -8056,51 +8056,51 @@ module \dec_sub22
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \function_unit 11'00000000010
     end
@@ -8108,51 +8108,51 @@ module \dec_sub22
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \form 5'01000
     end
@@ -8160,51 +8160,51 @@ module \dec_sub22
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \internal_op 7'0000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \internal_op 7'0100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \internal_op 7'0000001
     end
@@ -8212,51 +8212,51 @@ module \dec_sub22
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in1_sel 3'000
     end
@@ -8264,51 +8264,51 @@ module \dec_sub22
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in2_sel 4'0000
     end
@@ -8316,51 +8316,51 @@ module \dec_sub22
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in3_sel 2'00
     end
@@ -8368,51 +8368,51 @@ module \dec_sub22
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \out_sel 2'00
     end
@@ -8420,51 +8420,51 @@ module \dec_sub22
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_in 3'000
     end
@@ -8472,51 +8472,51 @@ module \dec_sub22
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_out 3'000
     end
@@ -8524,51 +8524,51 @@ module \dec_sub22
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \ldst_len 4'0000
     end
@@ -8576,51 +8576,51 @@ module \dec_sub22
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \upd 2'00
     end
@@ -8628,51 +8628,51 @@ module \dec_sub22
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rc_sel 2'00
     end
@@ -8680,51 +8680,51 @@ module \dec_sub22
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_in 2'00
     end
@@ -8732,51 +8732,51 @@ module \dec_sub22
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'00101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'00101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \asmcode 8'00110000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'00110001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \asmcode 8'01001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \asmcode 8'01011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'01100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \asmcode 8'10100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \asmcode 8'10101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \asmcode 8'10101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \asmcode 8'10110000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \asmcode 8'10110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'10110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \asmcode 8'11000101
     end
@@ -8784,51 +8784,51 @@ module \dec_sub22
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_a 1'0
     end
@@ -8836,51 +8836,51 @@ module \dec_sub22
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_out 1'0
     end
@@ -8888,51 +8888,51 @@ module \dec_sub22
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_out 1'0
     end
@@ -8940,51 +8940,51 @@ module \dec_sub22
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \br 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \br 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \br 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \br 1'0
     end
@@ -8992,51 +8992,51 @@ module \dec_sub22
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn_ext 1'0
     end
@@ -9044,51 +9044,51 @@ module \dec_sub22
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rsrv 1'0
     end
@@ -9096,51 +9096,51 @@ module \dec_sub22
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \is_32b 1'0
     end
@@ -9148,51 +9148,51 @@ module \dec_sub22
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn 1'0
     end
@@ -9200,51 +9200,51 @@ module \dec_sub22
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \lk 1'0
     end
@@ -9252,51 +9252,51 @@ module \dec_sub22
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgl_pipe 1'1
     end
@@ -9306,7 +9306,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub9"
 module \dec_sub9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -9320,7 +9320,7 @@ module \dec_sub9
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -9352,7 +9352,7 @@ module \dec_sub9
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -9427,7 +9427,7 @@ module \dec_sub9
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -9435,7 +9435,7 @@ module \dec_sub9
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -9452,20 +9452,20 @@ module \dec_sub9
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -9475,7 +9475,7 @@ module \dec_sub9
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -9483,13 +9483,13 @@ module \dec_sub9
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -9497,44 +9497,44 @@ module \dec_sub9
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -9543,54 +9543,54 @@ module \dec_sub9
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \function_unit 11'00100000000
     end
@@ -9598,54 +9598,54 @@ module \dec_sub9
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \form 5'10001
     end
@@ -9653,54 +9653,54 @@ module \dec_sub9
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \internal_op 7'0101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \internal_op 7'0101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \internal_op 7'0110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \internal_op 7'0110010
     end
@@ -9708,54 +9708,54 @@ module \dec_sub9
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in1_sel 3'001
     end
@@ -9763,54 +9763,54 @@ module \dec_sub9
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in2_sel 4'0001
     end
@@ -9818,54 +9818,54 @@ module \dec_sub9
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in3_sel 2'00
     end
@@ -9873,54 +9873,54 @@ module \dec_sub9
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \out_sel 2'01
     end
@@ -9928,54 +9928,54 @@ module \dec_sub9
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_in 3'000
     end
@@ -9983,54 +9983,54 @@ module \dec_sub9
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_out 3'001
     end
@@ -10038,54 +10038,54 @@ module \dec_sub9
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \ldst_len 4'0000
     end
@@ -10093,54 +10093,54 @@ module \dec_sub9
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \upd 2'00
     end
@@ -10148,54 +10148,54 @@ module \dec_sub9
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rc_sel 2'10
     end
@@ -10203,54 +10203,54 @@ module \dec_sub9
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_in 2'00
     end
@@ -10258,54 +10258,54 @@ module \dec_sub9
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \asmcode 8'00110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \asmcode 8'00110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \asmcode 8'00110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \asmcode 8'00110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \asmcode 8'00111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \asmcode 8'00111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \asmcode 8'00110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \asmcode 8'00111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \asmcode 8'01110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \asmcode 8'01110000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'01111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \asmcode 8'01111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'01111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'01111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \asmcode 8'01111101
     end
@@ -10313,54 +10313,54 @@ module \dec_sub9
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_a 1'0
     end
@@ -10368,54 +10368,54 @@ module \dec_sub9
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_out 1'0
     end
@@ -10423,54 +10423,54 @@ module \dec_sub9
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_out 1'0
     end
@@ -10478,54 +10478,54 @@ module \dec_sub9
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \br 1'0
     end
@@ -10533,54 +10533,54 @@ module \dec_sub9
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn_ext 1'0
     end
@@ -10588,54 +10588,54 @@ module \dec_sub9
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rsrv 1'0
     end
@@ -10643,54 +10643,54 @@ module \dec_sub9
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \is_32b 1'0
     end
@@ -10698,54 +10698,54 @@ module \dec_sub9
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn 1'1
     end
@@ -10753,54 +10753,54 @@ module \dec_sub9
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \lk 1'0
     end
@@ -10808,54 +10808,54 @@ module \dec_sub9
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgl_pipe 1'0
     end
@@ -10865,7 +10865,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub11"
 module \dec_sub11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -10879,7 +10879,7 @@ module \dec_sub11
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -10911,7 +10911,7 @@ module \dec_sub11
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -10986,7 +10986,7 @@ module \dec_sub11
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -10994,7 +10994,7 @@ module \dec_sub11
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -11011,20 +11011,20 @@ module \dec_sub11
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -11034,7 +11034,7 @@ module \dec_sub11
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -11042,13 +11042,13 @@ module \dec_sub11
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -11056,44 +11056,44 @@ module \dec_sub11
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -11102,54 +11102,54 @@ module \dec_sub11
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \function_unit 11'01000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \function_unit 11'00100000000
     end
@@ -11157,54 +11157,54 @@ module \dec_sub11
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \form 5'10001
     end
@@ -11212,54 +11212,54 @@ module \dec_sub11
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \internal_op 7'0011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \internal_op 7'0011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \internal_op 7'0101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \internal_op 7'0101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \internal_op 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \internal_op 7'0110010
     end
@@ -11267,54 +11267,54 @@ module \dec_sub11
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in1_sel 3'001
     end
@@ -11322,54 +11322,54 @@ module \dec_sub11
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in2_sel 4'0001
     end
@@ -11377,54 +11377,54 @@ module \dec_sub11
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in3_sel 2'00
     end
@@ -11432,54 +11432,54 @@ module \dec_sub11
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \out_sel 2'01
     end
@@ -11487,54 +11487,54 @@ module \dec_sub11
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_in 3'000
     end
@@ -11542,54 +11542,54 @@ module \dec_sub11
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_out 3'001
     end
@@ -11597,54 +11597,54 @@ module \dec_sub11
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \ldst_len 4'0000
     end
@@ -11652,54 +11652,54 @@ module \dec_sub11
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \upd 2'00
     end
@@ -11707,54 +11707,54 @@ module \dec_sub11
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rc_sel 2'10
     end
@@ -11762,54 +11762,54 @@ module \dec_sub11
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_in 2'00
     end
@@ -11817,54 +11817,54 @@ module \dec_sub11
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \asmcode 8'00111110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \asmcode 8'00111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \asmcode 8'00111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \asmcode 8'00111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \asmcode 8'01000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \asmcode 8'01000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \asmcode 8'00111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \asmcode 8'01000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \asmcode 8'01110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \asmcode 8'01110001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'01111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \asmcode 8'01111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'01111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'01111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \asmcode 8'10000000
     end
@@ -11872,54 +11872,54 @@ module \dec_sub11
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_a 1'0
     end
@@ -11927,54 +11927,54 @@ module \dec_sub11
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_out 1'0
     end
@@ -11982,54 +11982,54 @@ module \dec_sub11
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_out 1'0
     end
@@ -12037,54 +12037,54 @@ module \dec_sub11
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \br 1'0
     end
@@ -12092,54 +12092,54 @@ module \dec_sub11
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn_ext 1'0
     end
@@ -12147,54 +12147,54 @@ module \dec_sub11
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rsrv 1'0
     end
@@ -12202,54 +12202,54 @@ module \dec_sub11
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \is_32b 1'1
     end
@@ -12257,54 +12257,54 @@ module \dec_sub11
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn 1'1
     end
@@ -12312,54 +12312,54 @@ module \dec_sub11
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \lk 1'0
     end
@@ -12367,54 +12367,54 @@ module \dec_sub11
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgl_pipe 1'0
     end
@@ -12424,7 +12424,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub27"
 module \dec_sub27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -12438,7 +12438,7 @@ module \dec_sub27
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -12470,7 +12470,7 @@ module \dec_sub27
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -12545,7 +12545,7 @@ module \dec_sub27
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -12553,7 +12553,7 @@ module \dec_sub27
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -12570,20 +12570,20 @@ module \dec_sub27
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -12593,7 +12593,7 @@ module \dec_sub27
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -12601,13 +12601,13 @@ module \dec_sub27
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -12615,44 +12615,44 @@ module \dec_sub27
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -12661,18 +12661,18 @@ module \dec_sub27
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00000001000
     end
@@ -12680,18 +12680,18 @@ module \dec_sub27
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \form 5'10000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \form 5'10000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'01000
     end
@@ -12699,18 +12699,18 @@ module \dec_sub27
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \internal_op 7'0100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \internal_op 7'0111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0111101
     end
@@ -12718,18 +12718,18 @@ module \dec_sub27
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'000
     end
@@ -12737,18 +12737,18 @@ module \dec_sub27
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in2_sel 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
     end
@@ -12756,18 +12756,18 @@ module \dec_sub27
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'01
     end
@@ -12775,18 +12775,18 @@ module \dec_sub27
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'10
     end
@@ -12794,18 +12794,18 @@ module \dec_sub27
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
     end
@@ -12813,18 +12813,18 @@ module \dec_sub27
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'001
     end
@@ -12832,18 +12832,18 @@ module \dec_sub27
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
     end
@@ -12851,18 +12851,18 @@ module \dec_sub27
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
     end
@@ -12870,18 +12870,18 @@ module \dec_sub27
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'10
     end
@@ -12889,18 +12889,18 @@ module \dec_sub27
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
     end
@@ -12908,18 +12908,18 @@ module \dec_sub27
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \asmcode 8'01000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'10011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \asmcode 8'10011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'10100001
     end
@@ -12927,18 +12927,18 @@ module \dec_sub27
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
     end
@@ -12946,18 +12946,18 @@ module \dec_sub27
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
     end
@@ -12965,18 +12965,18 @@ module \dec_sub27
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
     end
@@ -12984,18 +12984,18 @@ module \dec_sub27
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
     end
@@ -13003,18 +13003,18 @@ module \dec_sub27
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
     end
@@ -13022,18 +13022,18 @@ module \dec_sub27
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
     end
@@ -13041,18 +13041,18 @@ module \dec_sub27
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'0
     end
@@ -13060,18 +13060,18 @@ module \dec_sub27
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
     end
@@ -13079,18 +13079,18 @@ module \dec_sub27
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
     end
@@ -13098,18 +13098,18 @@ module \dec_sub27
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'0
     end
@@ -13119,7 +13119,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub15"
 module \dec_sub15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -13133,7 +13133,7 @@ module \dec_sub15
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -13165,7 +13165,7 @@ module \dec_sub15
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -13240,7 +13240,7 @@ module \dec_sub15
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -13248,7 +13248,7 @@ module \dec_sub15
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -13265,20 +13265,20 @@ module \dec_sub15
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -13288,7 +13288,7 @@ module \dec_sub15
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -13296,13 +13296,13 @@ module \dec_sub15
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -13310,44 +13310,44 @@ module \dec_sub15
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -13356,102 +13356,102 @@ module \dec_sub15
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \function_unit 11'00001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \function_unit 11'00001000000
     end
@@ -13459,102 +13459,102 @@ module \dec_sub15
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \form 5'10010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \form 5'10010
     end
@@ -13562,102 +13562,102 @@ module \dec_sub15
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \internal_op 7'0100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \internal_op 7'0100011
     end
@@ -13665,102 +13665,102 @@ module \dec_sub15
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in1_sel 3'010
     end
@@ -13768,102 +13768,102 @@ module \dec_sub15
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in2_sel 4'0001
     end
@@ -13871,102 +13871,102 @@ module \dec_sub15
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in3_sel 2'00
     end
@@ -13974,102 +13974,102 @@ module \dec_sub15
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \out_sel 2'01
     end
@@ -14077,102 +14077,102 @@ module \dec_sub15
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_in 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_in 3'101
     end
@@ -14180,102 +14180,102 @@ module \dec_sub15
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_out 3'000
     end
@@ -14283,102 +14283,102 @@ module \dec_sub15
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \ldst_len 4'0000
     end
@@ -14386,102 +14386,102 @@ module \dec_sub15
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \upd 2'00
     end
@@ -14489,102 +14489,102 @@ module \dec_sub15
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rc_sel 2'00
     end
@@ -14592,102 +14592,102 @@ module \dec_sub15
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_in 2'00
     end
@@ -14695,102 +14695,102 @@ module \dec_sub15
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \asmcode 8'01001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \asmcode 8'01001010
     end
@@ -14798,102 +14798,102 @@ module \dec_sub15
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_a 1'0
     end
@@ -14901,102 +14901,102 @@ module \dec_sub15
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_out 1'0
     end
@@ -15004,102 +15004,102 @@ module \dec_sub15
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_out 1'0
     end
@@ -15107,102 +15107,102 @@ module \dec_sub15
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \br 1'0
     end
@@ -15210,102 +15210,102 @@ module \dec_sub15
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn_ext 1'0
     end
@@ -15313,102 +15313,102 @@ module \dec_sub15
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rsrv 1'0
     end
@@ -15416,102 +15416,102 @@ module \dec_sub15
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \is_32b 1'0
     end
@@ -15519,102 +15519,102 @@ module \dec_sub15
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn 1'0
     end
@@ -15622,102 +15622,102 @@ module \dec_sub15
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \lk 1'0
     end
@@ -15725,102 +15725,102 @@ module \dec_sub15
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01111
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgl_pipe 1'1
     end
@@ -15830,7 +15830,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub20"
 module \dec_sub20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -15844,7 +15844,7 @@ module \dec_sub20
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -15876,7 +15876,7 @@ module \dec_sub20
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -15951,7 +15951,7 @@ module \dec_sub20
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -15959,7 +15959,7 @@ module \dec_sub20
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -15976,20 +15976,20 @@ module \dec_sub20
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -15999,7 +15999,7 @@ module \dec_sub20
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -16007,13 +16007,13 @@ module \dec_sub20
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -16021,44 +16021,44 @@ module \dec_sub20
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -16067,24 +16067,24 @@ module \dec_sub20
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \function_unit 11'00000000100
     end
@@ -16092,24 +16092,24 @@ module \dec_sub20
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \form 5'01000
     end
@@ -16117,24 +16117,24 @@ module \dec_sub20
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \internal_op 7'0100110
     end
@@ -16142,24 +16142,24 @@ module \dec_sub20
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in1_sel 3'010
     end
@@ -16167,24 +16167,24 @@ module \dec_sub20
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in2_sel 4'0001
     end
@@ -16192,24 +16192,24 @@ module \dec_sub20
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in3_sel 2'01
     end
@@ -16217,24 +16217,24 @@ module \dec_sub20
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \out_sel 2'00
     end
@@ -16242,24 +16242,24 @@ module \dec_sub20
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_in 3'000
     end
@@ -16267,24 +16267,24 @@ module \dec_sub20
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_out 3'000
     end
@@ -16292,24 +16292,24 @@ module \dec_sub20
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \ldst_len 4'1000
     end
@@ -16317,24 +16317,24 @@ module \dec_sub20
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \upd 2'00
     end
@@ -16342,24 +16342,24 @@ module \dec_sub20
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rc_sel 2'00
     end
@@ -16367,24 +16367,24 @@ module \dec_sub20
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_in 2'00
     end
@@ -16392,24 +16392,24 @@ module \dec_sub20
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'01001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'01010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'01010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \asmcode 8'01011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \asmcode 8'10101001
     end
@@ -16417,24 +16417,24 @@ module \dec_sub20
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_a 1'0
     end
@@ -16442,24 +16442,24 @@ module \dec_sub20
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_out 1'0
     end
@@ -16467,24 +16467,24 @@ module \dec_sub20
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_out 1'0
     end
@@ -16492,24 +16492,24 @@ module \dec_sub20
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \br 1'1
     end
@@ -16517,24 +16517,24 @@ module \dec_sub20
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn_ext 1'0
     end
@@ -16542,24 +16542,24 @@ module \dec_sub20
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rsrv 1'0
     end
@@ -16567,24 +16567,24 @@ module \dec_sub20
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \is_32b 1'0
     end
@@ -16592,24 +16592,24 @@ module \dec_sub20
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn 1'0
     end
@@ -16617,24 +16617,24 @@ module \dec_sub20
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \lk 1'0
     end
@@ -16642,24 +16642,24 @@ module \dec_sub20
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgl_pipe 1'1
     end
@@ -16669,7 +16669,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub21"
 module \dec_sub21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -16683,7 +16683,7 @@ module \dec_sub21
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -16715,7 +16715,7 @@ module \dec_sub21
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -16790,7 +16790,7 @@ module \dec_sub21
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -16798,7 +16798,7 @@ module \dec_sub21
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -16815,20 +16815,20 @@ module \dec_sub21
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -16838,7 +16838,7 @@ module \dec_sub21
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -16846,13 +16846,13 @@ module \dec_sub21
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -16860,44 +16860,44 @@ module \dec_sub21
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -16906,45 +16906,45 @@ module \dec_sub21
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \function_unit 11'00000000100
     end
@@ -16952,45 +16952,45 @@ module \dec_sub21
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \form 5'01000
     end
@@ -16998,45 +16998,45 @@ module \dec_sub21
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \internal_op 7'0100110
     end
@@ -17044,45 +17044,45 @@ module \dec_sub21
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in1_sel 3'010
     end
@@ -17090,45 +17090,45 @@ module \dec_sub21
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in2_sel 4'0001
     end
@@ -17136,45 +17136,45 @@ module \dec_sub21
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \in3_sel 2'01
     end
@@ -17182,45 +17182,45 @@ module \dec_sub21
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \out_sel 2'00
     end
@@ -17228,45 +17228,45 @@ module \dec_sub21
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_in 3'000
     end
@@ -17274,45 +17274,45 @@ module \dec_sub21
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cr_out 3'000
     end
@@ -17320,45 +17320,45 @@ module \dec_sub21
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \ldst_len 4'0100
     end
@@ -17366,45 +17366,45 @@ module \dec_sub21
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \upd 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \upd 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \upd 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \upd 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \upd 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \upd 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \upd 2'10
     end
@@ -17412,45 +17412,45 @@ module \dec_sub21
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rc_sel 2'00
     end
@@ -17458,45 +17458,45 @@ module \dec_sub21
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_in 2'00
     end
@@ -17504,45 +17504,45 @@ module \dec_sub21
   end
   process $group_14
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_a 1'0
     end
@@ -17550,45 +17550,45 @@ module \dec_sub21
   end
   process $group_15
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \inv_out 1'0
     end
@@ -17596,45 +17596,45 @@ module \dec_sub21
   end
   process $group_16
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \cry_out 1'0
     end
@@ -17642,45 +17642,45 @@ module \dec_sub21
   end
   process $group_17
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \br 1'0
     end
@@ -17688,45 +17688,45 @@ module \dec_sub21
   end
   process $group_18
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn_ext 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn_ext 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn_ext 1'0
     end
@@ -17734,45 +17734,45 @@ module \dec_sub21
   end
   process $group_19
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \rsrv 1'0
     end
@@ -17780,45 +17780,45 @@ module \dec_sub21
   end
   process $group_20
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \is_32b 1'0
     end
@@ -17826,45 +17826,45 @@ module \dec_sub21
   end
   process $group_21
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgn 1'0
     end
@@ -17872,45 +17872,45 @@ module \dec_sub21
   end
   process $group_22
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \lk 1'0
     end
@@ -17918,45 +17918,45 @@ module \dec_sub21
   end
   process $group_23
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
         assign \sgl_pipe 1'1
     end
@@ -17964,39 +17964,39 @@ module \dec_sub21
   end
   process $group_24
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'01010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \asmcode 8'01100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \asmcode 8'01100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \asmcode 8'10101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'10101101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11100
     end
     sync init
@@ -18005,7 +18005,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub23"
 module \dec_sub23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -18019,7 +18019,7 @@ module \dec_sub23
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -18051,7 +18051,7 @@ module \dec_sub23
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -18126,7 +18126,7 @@ module \dec_sub23
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -18134,7 +18134,7 @@ module \dec_sub23
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -18151,20 +18151,20 @@ module \dec_sub23
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -18174,7 +18174,7 @@ module \dec_sub23
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -18182,13 +18182,13 @@ module \dec_sub23
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -18196,44 +18196,44 @@ module \dec_sub23
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -18242,48 +18242,48 @@ module \dec_sub23
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00000000100
     end
@@ -18291,48 +18291,48 @@ module \dec_sub23
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'01000
     end
@@ -18340,48 +18340,48 @@ module \dec_sub23
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0100110
     end
@@ -18389,48 +18389,48 @@ module \dec_sub23
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'010
     end
@@ -18438,48 +18438,48 @@ module \dec_sub23
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0001
     end
@@ -18487,48 +18487,48 @@ module \dec_sub23
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'01
     end
@@ -18536,48 +18536,48 @@ module \dec_sub23
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'00
     end
@@ -18585,48 +18585,48 @@ module \dec_sub23
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'000
     end
@@ -18634,48 +18634,48 @@ module \dec_sub23
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'000
     end
@@ -18683,48 +18683,48 @@ module \dec_sub23
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0100
     end
@@ -18732,48 +18732,48 @@ module \dec_sub23
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
     end
@@ -18781,48 +18781,48 @@ module \dec_sub23
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
     end
@@ -18830,48 +18830,48 @@ module \dec_sub23
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
     end
@@ -18879,48 +18879,48 @@ module \dec_sub23
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \asmcode 8'01001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'01010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \asmcode 8'01011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \asmcode 8'01011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \asmcode 8'01011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \asmcode 8'01100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'01101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'01101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'10100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \asmcode 8'10100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \asmcode 8'10110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \asmcode 8'10110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \asmcode 8'10111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'10111001
     end
@@ -18928,48 +18928,48 @@ module \dec_sub23
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
     end
@@ -18977,48 +18977,48 @@ module \dec_sub23
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
     end
@@ -19026,48 +19026,48 @@ module \dec_sub23
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
     end
@@ -19075,48 +19075,48 @@ module \dec_sub23
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
     end
@@ -19124,48 +19124,48 @@ module \dec_sub23
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn_ext 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn_ext 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
     end
@@ -19173,48 +19173,48 @@ module \dec_sub23
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
     end
@@ -19222,48 +19222,48 @@ module \dec_sub23
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
     end
@@ -19271,48 +19271,48 @@ module \dec_sub23
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
     end
@@ -19320,48 +19320,48 @@ module \dec_sub23
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
     end
@@ -19369,48 +19369,48 @@ module \dec_sub23
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'01100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'1
     end
@@ -19420,7 +19420,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub16"
 module \dec_sub16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -19434,7 +19434,7 @@ module \dec_sub16
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -19466,7 +19466,7 @@ module \dec_sub16
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -19541,7 +19541,7 @@ module \dec_sub16
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -19549,7 +19549,7 @@ module \dec_sub16
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -19566,20 +19566,20 @@ module \dec_sub16
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -19589,7 +19589,7 @@ module \dec_sub16
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -19597,13 +19597,13 @@ module \dec_sub16
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -19611,44 +19611,44 @@ module \dec_sub16
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -19657,9 +19657,9 @@ module \dec_sub16
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00001000000
     end
@@ -19667,9 +19667,9 @@ module \dec_sub16
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'01010
     end
@@ -19677,9 +19677,9 @@ module \dec_sub16
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0110000
     end
@@ -19687,9 +19687,9 @@ module \dec_sub16
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'100
     end
@@ -19697,9 +19697,9 @@ module \dec_sub16
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0000
     end
@@ -19707,9 +19707,9 @@ module \dec_sub16
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'00
     end
@@ -19717,9 +19717,9 @@ module \dec_sub16
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'00
     end
@@ -19727,9 +19727,9 @@ module \dec_sub16
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'110
     end
@@ -19737,9 +19737,9 @@ module \dec_sub16
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'100
     end
@@ -19747,9 +19747,9 @@ module \dec_sub16
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0000
     end
@@ -19757,9 +19757,9 @@ module \dec_sub16
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
     end
@@ -19767,9 +19767,9 @@ module \dec_sub16
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
     end
@@ -19777,9 +19777,9 @@ module \dec_sub16
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
     end
@@ -19787,9 +19787,9 @@ module \dec_sub16
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'01110100
     end
@@ -19797,9 +19797,9 @@ module \dec_sub16
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
     end
@@ -19807,9 +19807,9 @@ module \dec_sub16
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
     end
@@ -19817,9 +19817,9 @@ module \dec_sub16
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
     end
@@ -19827,9 +19827,9 @@ module \dec_sub16
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
     end
@@ -19837,9 +19837,9 @@ module \dec_sub16
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
     end
@@ -19847,9 +19847,9 @@ module \dec_sub16
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
     end
@@ -19857,9 +19857,9 @@ module \dec_sub16
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
     end
@@ -19867,9 +19867,9 @@ module \dec_sub16
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
     end
@@ -19877,9 +19877,9 @@ module \dec_sub16
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
     end
@@ -19887,9 +19887,9 @@ module \dec_sub16
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'0
     end
@@ -19899,7 +19899,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub18"
 module \dec_sub18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -19913,7 +19913,7 @@ module \dec_sub18
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -19945,7 +19945,7 @@ module \dec_sub18
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -20020,7 +20020,7 @@ module \dec_sub18
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -20028,7 +20028,7 @@ module \dec_sub18
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -20045,20 +20045,20 @@ module \dec_sub18
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -20068,7 +20068,7 @@ module \dec_sub18
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -20076,13 +20076,13 @@ module \dec_sub18
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -20090,44 +20090,44 @@ module \dec_sub18
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -20136,12 +20136,12 @@ module \dec_sub18
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \function_unit 11'00010000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00010000000
     end
@@ -20149,12 +20149,12 @@ module \dec_sub18
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'01000
     end
@@ -20162,12 +20162,12 @@ module \dec_sub18
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \internal_op 7'1001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'1001010
     end
@@ -20175,12 +20175,12 @@ module \dec_sub18
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'100
     end
@@ -20188,12 +20188,12 @@ module \dec_sub18
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0000
     end
@@ -20201,12 +20201,12 @@ module \dec_sub18
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'00
     end
@@ -20214,12 +20214,12 @@ module \dec_sub18
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'00
     end
@@ -20227,12 +20227,12 @@ module \dec_sub18
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'000
     end
@@ -20240,12 +20240,12 @@ module \dec_sub18
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'000
     end
@@ -20253,12 +20253,12 @@ module \dec_sub18
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0000
     end
@@ -20266,12 +20266,12 @@ module \dec_sub18
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
     end
@@ -20279,12 +20279,12 @@ module \dec_sub18
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'00
     end
@@ -20292,12 +20292,12 @@ module \dec_sub18
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'00
     end
@@ -20305,12 +20305,12 @@ module \dec_sub18
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \asmcode 8'01110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'01110101
     end
@@ -20318,12 +20318,12 @@ module \dec_sub18
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'0
     end
@@ -20331,12 +20331,12 @@ module \dec_sub18
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
     end
@@ -20344,12 +20344,12 @@ module \dec_sub18
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'0
     end
@@ -20357,12 +20357,12 @@ module \dec_sub18
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
     end
@@ -20370,12 +20370,12 @@ module \dec_sub18
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
     end
@@ -20383,12 +20383,12 @@ module \dec_sub18
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
     end
@@ -20396,12 +20396,12 @@ module \dec_sub18
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
     end
@@ -20409,12 +20409,12 @@ module \dec_sub18
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
     end
@@ -20422,12 +20422,12 @@ module \dec_sub18
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
     end
@@ -20435,12 +20435,12 @@ module \dec_sub18
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'1
     end
@@ -20450,7 +20450,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub8"
 module \dec_sub8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -20464,7 +20464,7 @@ module \dec_sub8
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -20496,7 +20496,7 @@ module \dec_sub8
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -20571,7 +20571,7 @@ module \dec_sub8
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -20579,7 +20579,7 @@ module \dec_sub8
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -20596,20 +20596,20 @@ module \dec_sub8
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -20619,7 +20619,7 @@ module \dec_sub8
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -20627,13 +20627,13 @@ module \dec_sub8
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -20641,44 +20641,44 @@ module \dec_sub8
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -20687,42 +20687,42 @@ module \dec_sub8
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \function_unit 11'00000000010
     end
@@ -20730,42 +20730,42 @@ module \dec_sub8
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \form 5'10001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \form 5'10001
     end
@@ -20773,42 +20773,42 @@ module \dec_sub8
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \internal_op 7'0000010
     end
@@ -20816,42 +20816,42 @@ module \dec_sub8
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in1_sel 3'001
     end
@@ -20859,42 +20859,42 @@ module \dec_sub8
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in2_sel 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in2_sel 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in2_sel 4'0000
     end
@@ -20902,42 +20902,42 @@ module \dec_sub8
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \in3_sel 2'00
     end
@@ -20945,42 +20945,42 @@ module \dec_sub8
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \out_sel 2'01
     end
@@ -20988,42 +20988,42 @@ module \dec_sub8
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_in 3'000
     end
@@ -21031,42 +21031,42 @@ module \dec_sub8
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cr_out 3'001
     end
@@ -21074,42 +21074,42 @@ module \dec_sub8
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \ldst_len 4'0000
     end
@@ -21117,42 +21117,42 @@ module \dec_sub8
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \upd 2'00
     end
@@ -21160,42 +21160,42 @@ module \dec_sub8
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rc_sel 2'10
     end
@@ -21203,42 +21203,42 @@ module \dec_sub8
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_in 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_in 2'10
     end
@@ -21246,42 +21246,42 @@ module \dec_sub8
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \asmcode 8'10000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \asmcode 8'10000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \asmcode 8'10111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \asmcode 8'11000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'10111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'10111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \asmcode 8'10111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \asmcode 8'10111110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \asmcode 8'11000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \asmcode 8'11000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \asmcode 8'11000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \asmcode 8'11000100
     end
@@ -21289,42 +21289,42 @@ module \dec_sub8
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_a 1'1
     end
@@ -21332,42 +21332,42 @@ module \dec_sub8
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \inv_out 1'0
     end
@@ -21375,42 +21375,42 @@ module \dec_sub8
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \cry_out 1'1
     end
@@ -21418,42 +21418,42 @@ module \dec_sub8
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \br 1'0
     end
@@ -21461,42 +21461,42 @@ module \dec_sub8
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn_ext 1'0
     end
@@ -21504,42 +21504,42 @@ module \dec_sub8
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \rsrv 1'0
     end
@@ -21547,42 +21547,42 @@ module \dec_sub8
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \is_32b 1'0
     end
@@ -21590,42 +21590,42 @@ module \dec_sub8
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgn 1'0
     end
@@ -21633,42 +21633,42 @@ module \dec_sub8
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \lk 1'0
     end
@@ -21676,42 +21676,42 @@ module \dec_sub8
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10110
         assign \sgl_pipe 1'0
     end
@@ -21721,7 +21721,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub24"
 module \dec_sub24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -21735,7 +21735,7 @@ module \dec_sub24
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -21767,7 +21767,7 @@ module \dec_sub24
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -21842,7 +21842,7 @@ module \dec_sub24
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -21850,7 +21850,7 @@ module \dec_sub24
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -21867,20 +21867,20 @@ module \dec_sub24
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -21890,7 +21890,7 @@ module \dec_sub24
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -21898,13 +21898,13 @@ module \dec_sub24
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -21912,44 +21912,44 @@ module \dec_sub24
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -21958,18 +21958,18 @@ module \dec_sub24
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \function_unit 11'00000001000
     end
@@ -21977,18 +21977,18 @@ module \dec_sub24
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \form 5'01000
     end
@@ -21996,18 +21996,18 @@ module \dec_sub24
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \internal_op 7'0111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \internal_op 7'0111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \internal_op 7'0111101
     end
@@ -22015,18 +22015,18 @@ module \dec_sub24
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in1_sel 3'000
     end
@@ -22034,18 +22034,18 @@ module \dec_sub24
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in2_sel 4'1011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in2_sel 4'0001
     end
@@ -22053,18 +22053,18 @@ module \dec_sub24
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \in3_sel 2'01
     end
@@ -22072,18 +22072,18 @@ module \dec_sub24
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \out_sel 2'10
     end
@@ -22091,18 +22091,18 @@ module \dec_sub24
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_in 3'000
     end
@@ -22110,18 +22110,18 @@ module \dec_sub24
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cr_out 3'001
     end
@@ -22129,18 +22129,18 @@ module \dec_sub24
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \ldst_len 4'0000
     end
@@ -22148,18 +22148,18 @@ module \dec_sub24
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \upd 2'00
     end
@@ -22167,18 +22167,18 @@ module \dec_sub24
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rc_sel 2'10
     end
@@ -22186,18 +22186,18 @@ module \dec_sub24
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_in 2'00
     end
@@ -22205,18 +22205,18 @@ module \dec_sub24
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'10011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \asmcode 8'10011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \asmcode 8'10100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \asmcode 8'10100010
     end
@@ -22224,18 +22224,18 @@ module \dec_sub24
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_a 1'0
     end
@@ -22243,18 +22243,18 @@ module \dec_sub24
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \inv_out 1'0
     end
@@ -22262,18 +22262,18 @@ module \dec_sub24
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \cry_out 1'0
     end
@@ -22281,18 +22281,18 @@ module \dec_sub24
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \br 1'0
     end
@@ -22300,18 +22300,18 @@ module \dec_sub24
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn_ext 1'0
     end
@@ -22319,18 +22319,18 @@ module \dec_sub24
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \rsrv 1'0
     end
@@ -22338,18 +22338,18 @@ module \dec_sub24
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \is_32b 1'1
     end
@@ -22357,18 +22357,18 @@ module \dec_sub24
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgn 1'0
     end
@@ -22376,18 +22376,18 @@ module \dec_sub24
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \lk 1'0
     end
@@ -22395,18 +22395,18 @@ module \dec_sub24
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'11001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'10000
         assign \sgl_pipe 1'0
     end
@@ -22416,7 +22416,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub4"
 module \dec_sub4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -22430,7 +22430,7 @@ module \dec_sub4
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -22462,7 +22462,7 @@ module \dec_sub4
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -22537,7 +22537,7 @@ module \dec_sub4
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -22545,7 +22545,7 @@ module \dec_sub4
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -22562,20 +22562,20 @@ module \dec_sub4
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -22585,7 +22585,7 @@ module \dec_sub4
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -22593,13 +22593,13 @@ module \dec_sub4
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -22607,44 +22607,44 @@ module \dec_sub4
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 5 \opcode_switch
   process $group_0
     assign \opcode_switch 5'00000
@@ -22653,12 +22653,12 @@ module \dec_sub4
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \function_unit 11'00010000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \function_unit 11'00010000000
     end
@@ -22666,12 +22666,12 @@ module \dec_sub4
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \form 5'01000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \form 5'01000
     end
@@ -22679,12 +22679,12 @@ module \dec_sub4
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \internal_op 7'0111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \internal_op 7'0111111
     end
@@ -22692,12 +22692,12 @@ module \dec_sub4
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in1_sel 3'001
     end
@@ -22705,12 +22705,12 @@ module \dec_sub4
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in2_sel 4'0001
     end
@@ -22718,12 +22718,12 @@ module \dec_sub4
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \in3_sel 2'00
     end
@@ -22731,12 +22731,12 @@ module \dec_sub4
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \out_sel 2'00
     end
@@ -22744,12 +22744,12 @@ module \dec_sub4
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_in 3'000
     end
@@ -22757,12 +22757,12 @@ module \dec_sub4
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cr_out 3'000
     end
@@ -22770,12 +22770,12 @@ module \dec_sub4
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \ldst_len 4'0000
     end
@@ -22783,12 +22783,12 @@ module \dec_sub4
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \upd 2'00
     end
@@ -22796,12 +22796,12 @@ module \dec_sub4
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rc_sel 2'00
     end
@@ -22809,12 +22809,12 @@ module \dec_sub4
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_in 2'00
     end
@@ -22822,12 +22822,12 @@ module \dec_sub4
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \asmcode 8'11000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \asmcode 8'11001000
     end
@@ -22835,12 +22835,12 @@ module \dec_sub4
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_a 1'0
     end
@@ -22848,12 +22848,12 @@ module \dec_sub4
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \inv_out 1'0
     end
@@ -22861,12 +22861,12 @@ module \dec_sub4
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \cry_out 1'0
     end
@@ -22874,12 +22874,12 @@ module \dec_sub4
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \br 1'0
     end
@@ -22887,12 +22887,12 @@ module \dec_sub4
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn_ext 1'0
     end
@@ -22900,12 +22900,12 @@ module \dec_sub4
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \rsrv 1'0
     end
@@ -22913,12 +22913,12 @@ module \dec_sub4
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \is_32b 1'1
     end
@@ -22926,12 +22926,12 @@ module \dec_sub4
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgn 1'0
     end
@@ -22939,12 +22939,12 @@ module \dec_sub4
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \lk 1'0
     end
@@ -22952,12 +22952,12 @@ module \dec_sub4
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 5'00000
         assign \sgl_pipe 1'1
     end
@@ -22967,7 +22967,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31"
 module \dec31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -22981,7 +22981,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -23013,7 +23013,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -23088,7 +23088,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -23096,7 +23096,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -23113,20 +23113,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -23136,7 +23136,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -23144,13 +23144,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -23158,44 +23158,44 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub10_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -23209,7 +23209,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub10_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -23241,7 +23241,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub10_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -23316,7 +23316,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub10_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -23324,7 +23324,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub10_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -23341,20 +23341,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub10_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub10_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub10_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -23364,7 +23364,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub10_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -23372,13 +23372,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub10_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub10_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -23386,42 +23386,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub10_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub10_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub10_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub10_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub10_asmcode
   cell \dec_sub10 \dec_sub10
     connect \opcode_in \dec_sub10_opcode_in
@@ -23450,7 +23450,7 @@ module \dec31
     connect \sgl_pipe \dec_sub10_sgl_pipe
     connect \asmcode \dec_sub10_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub28_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -23464,7 +23464,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub28_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -23496,7 +23496,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub28_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -23571,7 +23571,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub28_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -23579,7 +23579,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub28_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -23596,20 +23596,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub28_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub28_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub28_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -23619,7 +23619,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub28_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -23627,13 +23627,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub28_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub28_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -23641,42 +23641,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub28_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub28_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub28_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub28_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub28_asmcode
   cell \dec_sub28 \dec_sub28
     connect \opcode_in \dec_sub28_opcode_in
@@ -23705,7 +23705,7 @@ module \dec31
     connect \sgl_pipe \dec_sub28_sgl_pipe
     connect \asmcode \dec_sub28_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub0_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -23719,7 +23719,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub0_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -23751,7 +23751,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub0_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -23826,7 +23826,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub0_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -23834,7 +23834,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub0_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -23851,20 +23851,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub0_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub0_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub0_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -23874,7 +23874,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub0_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -23882,13 +23882,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub0_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub0_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -23896,42 +23896,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub0_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub0_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub0_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub0_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub0_asmcode
   cell \dec_sub0 \dec_sub0
     connect \opcode_in \dec_sub0_opcode_in
@@ -23960,7 +23960,7 @@ module \dec31
     connect \sgl_pipe \dec_sub0_sgl_pipe
     connect \asmcode \dec_sub0_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub26_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -23974,7 +23974,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub26_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -24006,7 +24006,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub26_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -24081,7 +24081,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub26_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -24089,7 +24089,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub26_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -24106,20 +24106,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub26_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub26_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub26_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -24129,7 +24129,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub26_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -24137,13 +24137,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub26_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub26_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -24151,42 +24151,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub26_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub26_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub26_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub26_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub26_asmcode
   cell \dec_sub26 \dec_sub26
     connect \opcode_in \dec_sub26_opcode_in
@@ -24215,7 +24215,7 @@ module \dec31
     connect \sgl_pipe \dec_sub26_sgl_pipe
     connect \asmcode \dec_sub26_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub19_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -24229,7 +24229,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub19_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -24261,7 +24261,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub19_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -24336,7 +24336,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub19_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -24344,7 +24344,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub19_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -24361,20 +24361,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub19_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub19_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub19_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -24384,7 +24384,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub19_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -24392,13 +24392,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub19_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub19_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -24406,42 +24406,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub19_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub19_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub19_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub19_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub19_asmcode
   cell \dec_sub19 \dec_sub19
     connect \opcode_in \dec_sub19_opcode_in
@@ -24470,7 +24470,7 @@ module \dec31
     connect \sgl_pipe \dec_sub19_sgl_pipe
     connect \asmcode \dec_sub19_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub22_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -24484,7 +24484,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub22_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -24516,7 +24516,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub22_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -24591,7 +24591,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub22_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -24599,7 +24599,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub22_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -24616,20 +24616,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub22_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub22_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub22_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -24639,7 +24639,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub22_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -24647,13 +24647,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub22_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub22_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -24661,42 +24661,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub22_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub22_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub22_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub22_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub22_asmcode
   cell \dec_sub22 \dec_sub22
     connect \opcode_in \dec_sub22_opcode_in
@@ -24725,7 +24725,7 @@ module \dec31
     connect \sgl_pipe \dec_sub22_sgl_pipe
     connect \asmcode \dec_sub22_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub9_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -24739,7 +24739,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub9_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -24771,7 +24771,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub9_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -24846,7 +24846,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub9_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -24854,7 +24854,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub9_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -24871,20 +24871,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub9_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub9_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub9_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -24894,7 +24894,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub9_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -24902,13 +24902,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub9_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub9_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -24916,42 +24916,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub9_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub9_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub9_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub9_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub9_asmcode
   cell \dec_sub9 \dec_sub9
     connect \opcode_in \dec_sub9_opcode_in
@@ -24980,7 +24980,7 @@ module \dec31
     connect \sgl_pipe \dec_sub9_sgl_pipe
     connect \asmcode \dec_sub9_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub11_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -24994,7 +24994,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub11_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -25026,7 +25026,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub11_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -25101,7 +25101,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub11_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -25109,7 +25109,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub11_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -25126,20 +25126,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub11_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub11_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub11_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -25149,7 +25149,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub11_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -25157,13 +25157,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub11_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub11_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -25171,42 +25171,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub11_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub11_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub11_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub11_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub11_asmcode
   cell \dec_sub11 \dec_sub11
     connect \opcode_in \dec_sub11_opcode_in
@@ -25235,7 +25235,7 @@ module \dec31
     connect \sgl_pipe \dec_sub11_sgl_pipe
     connect \asmcode \dec_sub11_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub27_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -25249,7 +25249,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub27_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -25281,7 +25281,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub27_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -25356,7 +25356,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub27_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -25364,7 +25364,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub27_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -25381,20 +25381,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub27_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub27_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub27_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -25404,7 +25404,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub27_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -25412,13 +25412,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub27_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub27_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -25426,42 +25426,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub27_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub27_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub27_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub27_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub27_asmcode
   cell \dec_sub27 \dec_sub27
     connect \opcode_in \dec_sub27_opcode_in
@@ -25490,7 +25490,7 @@ module \dec31
     connect \sgl_pipe \dec_sub27_sgl_pipe
     connect \asmcode \dec_sub27_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub15_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -25504,7 +25504,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub15_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -25536,7 +25536,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub15_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -25611,7 +25611,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub15_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -25619,7 +25619,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub15_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -25636,20 +25636,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub15_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub15_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub15_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -25659,7 +25659,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub15_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -25667,13 +25667,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub15_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub15_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -25681,42 +25681,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub15_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub15_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub15_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub15_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub15_asmcode
   cell \dec_sub15 \dec_sub15
     connect \opcode_in \dec_sub15_opcode_in
@@ -25745,7 +25745,7 @@ module \dec31
     connect \sgl_pipe \dec_sub15_sgl_pipe
     connect \asmcode \dec_sub15_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub20_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -25759,7 +25759,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub20_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -25791,7 +25791,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub20_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -25866,7 +25866,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub20_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -25874,7 +25874,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub20_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -25891,20 +25891,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub20_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub20_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub20_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -25914,7 +25914,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub20_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -25922,13 +25922,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub20_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub20_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -25936,42 +25936,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub20_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub20_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub20_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub20_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub20_asmcode
   cell \dec_sub20 \dec_sub20
     connect \opcode_in \dec_sub20_opcode_in
@@ -26000,7 +26000,7 @@ module \dec31
     connect \sgl_pipe \dec_sub20_sgl_pipe
     connect \asmcode \dec_sub20_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub21_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -26014,7 +26014,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub21_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -26046,7 +26046,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub21_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -26121,7 +26121,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub21_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -26129,7 +26129,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub21_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -26146,20 +26146,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub21_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub21_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub21_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -26169,7 +26169,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub21_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -26177,13 +26177,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub21_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub21_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -26191,42 +26191,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub21_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub21_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub21_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub21_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub21_asmcode
   cell \dec_sub21 \dec_sub21
     connect \opcode_in \dec_sub21_opcode_in
@@ -26255,7 +26255,7 @@ module \dec31
     connect \sgl_pipe \dec_sub21_sgl_pipe
     connect \asmcode \dec_sub21_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub23_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -26269,7 +26269,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub23_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -26301,7 +26301,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub23_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -26376,7 +26376,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub23_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -26384,7 +26384,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub23_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -26401,20 +26401,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub23_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub23_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub23_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -26424,7 +26424,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub23_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -26432,13 +26432,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub23_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub23_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -26446,42 +26446,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub23_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub23_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub23_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub23_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub23_asmcode
   cell \dec_sub23 \dec_sub23
     connect \opcode_in \dec_sub23_opcode_in
@@ -26510,7 +26510,7 @@ module \dec31
     connect \sgl_pipe \dec_sub23_sgl_pipe
     connect \asmcode \dec_sub23_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub16_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -26524,7 +26524,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub16_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -26556,7 +26556,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub16_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -26631,7 +26631,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub16_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -26639,7 +26639,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub16_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -26656,20 +26656,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub16_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub16_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub16_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -26679,7 +26679,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub16_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -26687,13 +26687,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub16_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub16_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -26701,42 +26701,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub16_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub16_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub16_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub16_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub16_asmcode
   cell \dec_sub16 \dec_sub16
     connect \opcode_in \dec_sub16_opcode_in
@@ -26765,7 +26765,7 @@ module \dec31
     connect \sgl_pipe \dec_sub16_sgl_pipe
     connect \asmcode \dec_sub16_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub18_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -26779,7 +26779,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub18_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -26811,7 +26811,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub18_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -26886,7 +26886,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub18_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -26894,7 +26894,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub18_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -26911,20 +26911,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub18_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub18_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub18_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -26934,7 +26934,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub18_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -26942,13 +26942,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub18_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub18_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -26956,42 +26956,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub18_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub18_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub18_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub18_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub18_asmcode
   cell \dec_sub18 \dec_sub18
     connect \opcode_in \dec_sub18_opcode_in
@@ -27020,7 +27020,7 @@ module \dec31
     connect \sgl_pipe \dec_sub18_sgl_pipe
     connect \asmcode \dec_sub18_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub8_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -27034,7 +27034,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub8_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -27066,7 +27066,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub8_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -27141,7 +27141,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub8_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -27149,7 +27149,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub8_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -27166,20 +27166,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub8_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub8_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub8_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -27189,7 +27189,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub8_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -27197,13 +27197,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub8_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub8_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -27211,42 +27211,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub8_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub8_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub8_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub8_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub8_asmcode
   cell \dec_sub8 \dec_sub8
     connect \opcode_in \dec_sub8_opcode_in
@@ -27275,7 +27275,7 @@ module \dec31
     connect \sgl_pipe \dec_sub8_sgl_pipe
     connect \asmcode \dec_sub8_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub24_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -27289,7 +27289,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub24_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -27321,7 +27321,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub24_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -27396,7 +27396,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub24_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -27404,7 +27404,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub24_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -27421,20 +27421,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub24_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub24_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub24_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -27444,7 +27444,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub24_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -27452,13 +27452,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub24_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub24_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -27466,42 +27466,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub24_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub24_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub24_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub24_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub24_asmcode
   cell \dec_sub24 \dec_sub24
     connect \opcode_in \dec_sub24_opcode_in
@@ -27530,7 +27530,7 @@ module \dec31
     connect \sgl_pipe \dec_sub24_sgl_pipe
     connect \asmcode \dec_sub24_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec_sub4_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -27544,7 +27544,7 @@ module \dec31
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec_sub4_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -27576,7 +27576,7 @@ module \dec31
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec_sub4_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -27651,7 +27651,7 @@ module \dec31
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec_sub4_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -27659,7 +27659,7 @@ module \dec31
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec_sub4_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -27676,20 +27676,20 @@ module \dec31
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec_sub4_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec_sub4_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec_sub4_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -27699,7 +27699,7 @@ module \dec31
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec_sub4_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -27707,13 +27707,13 @@ module \dec31
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec_sub4_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec_sub4_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -27721,42 +27721,42 @@ module \dec31
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec_sub4_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_sub4_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_sub4_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec_sub4_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec_sub4_asmcode
   cell \dec_sub4 \dec_sub4
     connect \opcode_in \dec_sub4_opcode_in
@@ -27785,14 +27785,14 @@ module \dec31
     connect \sgl_pipe \dec_sub4_sgl_pipe
     connect \asmcode \dec_sub4_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 10 \opcode_switch
   process $group_0
     assign \opcode_switch 10'0000000000
     assign \opcode_switch \opcode_in [10:1]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:271"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
   wire width 5 \opc_in
   process $group_1
     assign \opc_in 5'00000
@@ -27891,60 +27891,60 @@ module \dec31
   end
   process $group_20
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \function_unit \dec_sub10_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \function_unit \dec_sub28_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \function_unit \dec_sub0_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \function_unit \dec_sub26_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \function_unit \dec_sub19_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \function_unit \dec_sub22_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \function_unit \dec_sub9_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \function_unit \dec_sub11_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \function_unit \dec_sub27_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \function_unit \dec_sub15_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \function_unit \dec_sub20_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \function_unit \dec_sub21_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \function_unit \dec_sub23_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \function_unit \dec_sub16_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \function_unit \dec_sub18_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \function_unit \dec_sub8_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \function_unit \dec_sub24_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \function_unit \dec_sub4_function_unit
     end
@@ -27952,60 +27952,60 @@ module \dec31
   end
   process $group_21
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \form \dec_sub10_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \form \dec_sub28_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \form \dec_sub0_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \form \dec_sub26_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \form \dec_sub19_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \form \dec_sub22_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \form \dec_sub9_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \form \dec_sub11_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \form \dec_sub27_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \form \dec_sub15_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \form \dec_sub20_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \form \dec_sub21_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \form \dec_sub23_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \form \dec_sub16_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \form \dec_sub18_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \form \dec_sub8_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \form \dec_sub24_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \form \dec_sub4_form
     end
@@ -28013,60 +28013,60 @@ module \dec31
   end
   process $group_22
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \internal_op \dec_sub10_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \internal_op \dec_sub28_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \internal_op \dec_sub0_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \internal_op \dec_sub26_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \internal_op \dec_sub19_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \internal_op \dec_sub22_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \internal_op \dec_sub9_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \internal_op \dec_sub11_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \internal_op \dec_sub27_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \internal_op \dec_sub15_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \internal_op \dec_sub20_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \internal_op \dec_sub21_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \internal_op \dec_sub23_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \internal_op \dec_sub16_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \internal_op \dec_sub18_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \internal_op \dec_sub8_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \internal_op \dec_sub24_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \internal_op \dec_sub4_internal_op
     end
@@ -28074,60 +28074,60 @@ module \dec31
   end
   process $group_23
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \in1_sel \dec_sub10_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \in1_sel \dec_sub28_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \in1_sel \dec_sub0_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \in1_sel \dec_sub26_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \in1_sel \dec_sub19_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \in1_sel \dec_sub22_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \in1_sel \dec_sub9_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \in1_sel \dec_sub11_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \in1_sel \dec_sub27_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \in1_sel \dec_sub15_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \in1_sel \dec_sub20_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \in1_sel \dec_sub21_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \in1_sel \dec_sub23_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \in1_sel \dec_sub16_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \in1_sel \dec_sub18_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \in1_sel \dec_sub8_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \in1_sel \dec_sub24_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \in1_sel \dec_sub4_in1_sel
     end
@@ -28135,60 +28135,60 @@ module \dec31
   end
   process $group_24
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \in2_sel \dec_sub10_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \in2_sel \dec_sub28_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \in2_sel \dec_sub0_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \in2_sel \dec_sub26_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \in2_sel \dec_sub19_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \in2_sel \dec_sub22_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \in2_sel \dec_sub9_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \in2_sel \dec_sub11_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \in2_sel \dec_sub27_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \in2_sel \dec_sub15_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \in2_sel \dec_sub20_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \in2_sel \dec_sub21_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \in2_sel \dec_sub23_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \in2_sel \dec_sub16_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \in2_sel \dec_sub18_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \in2_sel \dec_sub8_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \in2_sel \dec_sub24_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \in2_sel \dec_sub4_in2_sel
     end
@@ -28196,60 +28196,60 @@ module \dec31
   end
   process $group_25
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \in3_sel \dec_sub10_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \in3_sel \dec_sub28_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \in3_sel \dec_sub0_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \in3_sel \dec_sub26_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \in3_sel \dec_sub19_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \in3_sel \dec_sub22_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \in3_sel \dec_sub9_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \in3_sel \dec_sub11_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \in3_sel \dec_sub27_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \in3_sel \dec_sub15_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \in3_sel \dec_sub20_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \in3_sel \dec_sub21_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \in3_sel \dec_sub23_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \in3_sel \dec_sub16_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \in3_sel \dec_sub18_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \in3_sel \dec_sub8_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \in3_sel \dec_sub24_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \in3_sel \dec_sub4_in3_sel
     end
@@ -28257,60 +28257,60 @@ module \dec31
   end
   process $group_26
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \out_sel \dec_sub10_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \out_sel \dec_sub28_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \out_sel \dec_sub0_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \out_sel \dec_sub26_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \out_sel \dec_sub19_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \out_sel \dec_sub22_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \out_sel \dec_sub9_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \out_sel \dec_sub11_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \out_sel \dec_sub27_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \out_sel \dec_sub15_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \out_sel \dec_sub20_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \out_sel \dec_sub21_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \out_sel \dec_sub23_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \out_sel \dec_sub16_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \out_sel \dec_sub18_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \out_sel \dec_sub8_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \out_sel \dec_sub24_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \out_sel \dec_sub4_out_sel
     end
@@ -28318,60 +28318,60 @@ module \dec31
   end
   process $group_27
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \cr_in \dec_sub10_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \cr_in \dec_sub28_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \cr_in \dec_sub0_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \cr_in \dec_sub26_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \cr_in \dec_sub19_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \cr_in \dec_sub22_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \cr_in \dec_sub9_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \cr_in \dec_sub11_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \cr_in \dec_sub27_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \cr_in \dec_sub15_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \cr_in \dec_sub20_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \cr_in \dec_sub21_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \cr_in \dec_sub23_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \cr_in \dec_sub16_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \cr_in \dec_sub18_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \cr_in \dec_sub8_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \cr_in \dec_sub24_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \cr_in \dec_sub4_cr_in
     end
@@ -28379,60 +28379,60 @@ module \dec31
   end
   process $group_28
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \cr_out \dec_sub10_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \cr_out \dec_sub28_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \cr_out \dec_sub0_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \cr_out \dec_sub26_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \cr_out \dec_sub19_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \cr_out \dec_sub22_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \cr_out \dec_sub9_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \cr_out \dec_sub11_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \cr_out \dec_sub27_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \cr_out \dec_sub15_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \cr_out \dec_sub20_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \cr_out \dec_sub21_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \cr_out \dec_sub23_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \cr_out \dec_sub16_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \cr_out \dec_sub18_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \cr_out \dec_sub8_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \cr_out \dec_sub24_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \cr_out \dec_sub4_cr_out
     end
@@ -28440,60 +28440,60 @@ module \dec31
   end
   process $group_29
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \rc_sel \dec_sub10_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \rc_sel \dec_sub28_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \rc_sel \dec_sub0_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \rc_sel \dec_sub26_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \rc_sel \dec_sub19_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \rc_sel \dec_sub22_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \rc_sel \dec_sub9_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \rc_sel \dec_sub11_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \rc_sel \dec_sub27_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \rc_sel \dec_sub15_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \rc_sel \dec_sub20_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \rc_sel \dec_sub21_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \rc_sel \dec_sub23_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \rc_sel \dec_sub16_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \rc_sel \dec_sub18_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \rc_sel \dec_sub8_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \rc_sel \dec_sub24_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \rc_sel \dec_sub4_rc_sel
     end
@@ -28501,60 +28501,60 @@ module \dec31
   end
   process $group_30
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \ldst_len \dec_sub10_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \ldst_len \dec_sub28_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \ldst_len \dec_sub0_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \ldst_len \dec_sub26_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \ldst_len \dec_sub19_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \ldst_len \dec_sub22_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \ldst_len \dec_sub9_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \ldst_len \dec_sub11_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \ldst_len \dec_sub27_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \ldst_len \dec_sub15_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \ldst_len \dec_sub20_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \ldst_len \dec_sub21_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \ldst_len \dec_sub23_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \ldst_len \dec_sub16_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \ldst_len \dec_sub18_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \ldst_len \dec_sub8_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \ldst_len \dec_sub24_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \ldst_len \dec_sub4_ldst_len
     end
@@ -28562,60 +28562,60 @@ module \dec31
   end
   process $group_31
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \upd \dec_sub10_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \upd \dec_sub28_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \upd \dec_sub0_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \upd \dec_sub26_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \upd \dec_sub19_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \upd \dec_sub22_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \upd \dec_sub9_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \upd \dec_sub11_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \upd \dec_sub27_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \upd \dec_sub15_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \upd \dec_sub20_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \upd \dec_sub21_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \upd \dec_sub23_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \upd \dec_sub16_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \upd \dec_sub18_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \upd \dec_sub8_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \upd \dec_sub24_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \upd \dec_sub4_upd
     end
@@ -28623,60 +28623,60 @@ module \dec31
   end
   process $group_32
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \cry_in \dec_sub10_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \cry_in \dec_sub28_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \cry_in \dec_sub0_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \cry_in \dec_sub26_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \cry_in \dec_sub19_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \cry_in \dec_sub22_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \cry_in \dec_sub9_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \cry_in \dec_sub11_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \cry_in \dec_sub27_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \cry_in \dec_sub15_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \cry_in \dec_sub20_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \cry_in \dec_sub21_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \cry_in \dec_sub23_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \cry_in \dec_sub16_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \cry_in \dec_sub18_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \cry_in \dec_sub8_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \cry_in \dec_sub24_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \cry_in \dec_sub4_cry_in
     end
@@ -28684,60 +28684,60 @@ module \dec31
   end
   process $group_33
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \inv_a \dec_sub10_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \inv_a \dec_sub28_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \inv_a \dec_sub0_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \inv_a \dec_sub26_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \inv_a \dec_sub19_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \inv_a \dec_sub22_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \inv_a \dec_sub9_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \inv_a \dec_sub11_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \inv_a \dec_sub27_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \inv_a \dec_sub15_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \inv_a \dec_sub20_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \inv_a \dec_sub21_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \inv_a \dec_sub23_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \inv_a \dec_sub16_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \inv_a \dec_sub18_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \inv_a \dec_sub8_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \inv_a \dec_sub24_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \inv_a \dec_sub4_inv_a
     end
@@ -28745,60 +28745,60 @@ module \dec31
   end
   process $group_34
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \inv_out \dec_sub10_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \inv_out \dec_sub28_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \inv_out \dec_sub0_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \inv_out \dec_sub26_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \inv_out \dec_sub19_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \inv_out \dec_sub22_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \inv_out \dec_sub9_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \inv_out \dec_sub11_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \inv_out \dec_sub27_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \inv_out \dec_sub15_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \inv_out \dec_sub20_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \inv_out \dec_sub21_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \inv_out \dec_sub23_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \inv_out \dec_sub16_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \inv_out \dec_sub18_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \inv_out \dec_sub8_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \inv_out \dec_sub24_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \inv_out \dec_sub4_inv_out
     end
@@ -28806,60 +28806,60 @@ module \dec31
   end
   process $group_35
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \cry_out \dec_sub10_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \cry_out \dec_sub28_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \cry_out \dec_sub0_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \cry_out \dec_sub26_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \cry_out \dec_sub19_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \cry_out \dec_sub22_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \cry_out \dec_sub9_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \cry_out \dec_sub11_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \cry_out \dec_sub27_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \cry_out \dec_sub15_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \cry_out \dec_sub20_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \cry_out \dec_sub21_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \cry_out \dec_sub23_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \cry_out \dec_sub16_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \cry_out \dec_sub18_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \cry_out \dec_sub8_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \cry_out \dec_sub24_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \cry_out \dec_sub4_cry_out
     end
@@ -28867,60 +28867,60 @@ module \dec31
   end
   process $group_36
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \br \dec_sub10_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \br \dec_sub28_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \br \dec_sub0_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \br \dec_sub26_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \br \dec_sub19_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \br \dec_sub22_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \br \dec_sub9_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \br \dec_sub11_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \br \dec_sub27_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \br \dec_sub15_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \br \dec_sub20_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \br \dec_sub21_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \br \dec_sub23_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \br \dec_sub16_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \br \dec_sub18_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \br \dec_sub8_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \br \dec_sub24_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \br \dec_sub4_br
     end
@@ -28928,60 +28928,60 @@ module \dec31
   end
   process $group_37
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \sgn_ext \dec_sub10_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \sgn_ext \dec_sub28_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \sgn_ext \dec_sub0_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \sgn_ext \dec_sub26_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \sgn_ext \dec_sub19_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \sgn_ext \dec_sub22_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \sgn_ext \dec_sub9_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \sgn_ext \dec_sub11_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \sgn_ext \dec_sub27_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \sgn_ext \dec_sub15_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \sgn_ext \dec_sub20_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \sgn_ext \dec_sub21_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \sgn_ext \dec_sub23_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \sgn_ext \dec_sub16_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \sgn_ext \dec_sub18_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \sgn_ext \dec_sub8_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \sgn_ext \dec_sub24_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \sgn_ext \dec_sub4_sgn_ext
     end
@@ -28989,60 +28989,60 @@ module \dec31
   end
   process $group_38
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \rsrv \dec_sub10_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \rsrv \dec_sub28_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \rsrv \dec_sub0_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \rsrv \dec_sub26_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \rsrv \dec_sub19_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \rsrv \dec_sub22_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \rsrv \dec_sub9_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \rsrv \dec_sub11_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \rsrv \dec_sub27_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \rsrv \dec_sub15_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \rsrv \dec_sub20_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \rsrv \dec_sub21_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \rsrv \dec_sub23_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \rsrv \dec_sub16_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \rsrv \dec_sub18_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \rsrv \dec_sub8_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \rsrv \dec_sub24_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \rsrv \dec_sub4_rsrv
     end
@@ -29050,60 +29050,60 @@ module \dec31
   end
   process $group_39
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \is_32b \dec_sub10_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \is_32b \dec_sub28_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \is_32b \dec_sub0_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \is_32b \dec_sub26_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \is_32b \dec_sub19_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \is_32b \dec_sub22_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \is_32b \dec_sub9_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \is_32b \dec_sub11_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \is_32b \dec_sub27_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \is_32b \dec_sub15_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \is_32b \dec_sub20_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \is_32b \dec_sub21_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \is_32b \dec_sub23_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \is_32b \dec_sub16_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \is_32b \dec_sub18_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \is_32b \dec_sub8_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \is_32b \dec_sub24_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \is_32b \dec_sub4_is_32b
     end
@@ -29111,60 +29111,60 @@ module \dec31
   end
   process $group_40
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \sgn \dec_sub10_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \sgn \dec_sub28_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \sgn \dec_sub0_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \sgn \dec_sub26_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \sgn \dec_sub19_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \sgn \dec_sub22_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \sgn \dec_sub9_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \sgn \dec_sub11_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \sgn \dec_sub27_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \sgn \dec_sub15_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \sgn \dec_sub20_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \sgn \dec_sub21_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \sgn \dec_sub23_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \sgn \dec_sub16_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \sgn \dec_sub18_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \sgn \dec_sub8_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \sgn \dec_sub24_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \sgn \dec_sub4_sgn
     end
@@ -29172,60 +29172,60 @@ module \dec31
   end
   process $group_41
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \lk \dec_sub10_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \lk \dec_sub28_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \lk \dec_sub0_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \lk \dec_sub26_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \lk \dec_sub19_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \lk \dec_sub22_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \lk \dec_sub9_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \lk \dec_sub11_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \lk \dec_sub27_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \lk \dec_sub15_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \lk \dec_sub20_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \lk \dec_sub21_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \lk \dec_sub23_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \lk \dec_sub16_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \lk \dec_sub18_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \lk \dec_sub8_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \lk \dec_sub24_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \lk \dec_sub4_lk
     end
@@ -29233,60 +29233,60 @@ module \dec31
   end
   process $group_42
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \sgl_pipe \dec_sub10_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \sgl_pipe \dec_sub28_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \sgl_pipe \dec_sub0_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \sgl_pipe \dec_sub26_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \sgl_pipe \dec_sub19_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \sgl_pipe \dec_sub22_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \sgl_pipe \dec_sub9_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \sgl_pipe \dec_sub11_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \sgl_pipe \dec_sub27_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \sgl_pipe \dec_sub15_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \sgl_pipe \dec_sub20_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \sgl_pipe \dec_sub21_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \sgl_pipe \dec_sub23_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \sgl_pipe \dec_sub16_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \sgl_pipe \dec_sub18_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \sgl_pipe \dec_sub8_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \sgl_pipe \dec_sub24_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \sgl_pipe \dec_sub4_sgl_pipe
     end
@@ -29294,60 +29294,60 @@ module \dec31
   end
   process $group_43
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277"
     switch \opc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01010
         assign \asmcode \dec_sub10_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11100
         assign \asmcode \dec_sub28_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00000
         assign \asmcode \dec_sub0_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11010
         assign \asmcode \dec_sub26_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10011
         assign \asmcode \dec_sub19_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10110
         assign \asmcode \dec_sub22_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01001
         assign \asmcode \dec_sub9_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01011
         assign \asmcode \dec_sub11_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11011
         assign \asmcode \dec_sub27_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01111
         assign \asmcode \dec_sub15_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10100
         assign \asmcode \dec_sub20_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10101
         assign \asmcode \dec_sub21_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10111
         assign \asmcode \dec_sub23_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10000
         assign \asmcode \dec_sub16_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'10010
         assign \asmcode \dec_sub18_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'01000
         assign \asmcode \dec_sub8_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'11000
         assign \asmcode \dec_sub24_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287"
       case 5'00100
         assign \asmcode \dec_sub4_asmcode
     end
@@ -29357,7 +29357,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec58"
 module \dec58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -29371,7 +29371,7 @@ module \dec58
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -29403,7 +29403,7 @@ module \dec58
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -29478,7 +29478,7 @@ module \dec58
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -29486,7 +29486,7 @@ module \dec58
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -29503,20 +29503,20 @@ module \dec58
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -29526,7 +29526,7 @@ module \dec58
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -29534,13 +29534,13 @@ module \dec58
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -29548,44 +29548,44 @@ module \dec58
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 2 \opcode_switch
   process $group_0
     assign \opcode_switch 2'00
@@ -29594,15 +29594,15 @@ module \dec58
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \function_unit 11'00000000100
     end
@@ -29610,15 +29610,15 @@ module \dec58
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \form 5'00101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \form 5'00101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \form 5'00101
     end
@@ -29626,15 +29626,15 @@ module \dec58
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \internal_op 7'0100101
     end
@@ -29642,15 +29642,15 @@ module \dec58
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \in1_sel 3'010
     end
@@ -29658,15 +29658,15 @@ module \dec58
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \in2_sel 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \in2_sel 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \in2_sel 4'1000
     end
@@ -29674,15 +29674,15 @@ module \dec58
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \in3_sel 2'00
     end
@@ -29690,15 +29690,15 @@ module \dec58
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \out_sel 2'01
     end
@@ -29706,15 +29706,15 @@ module \dec58
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \cr_in 3'000
     end
@@ -29722,15 +29722,15 @@ module \dec58
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \cr_out 3'000
     end
@@ -29738,15 +29738,15 @@ module \dec58
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \ldst_len 4'0100
     end
@@ -29754,15 +29754,15 @@ module \dec58
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \upd 2'00
     end
@@ -29770,15 +29770,15 @@ module \dec58
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \rc_sel 2'00
     end
@@ -29786,15 +29786,15 @@ module \dec58
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \cry_in 2'00
     end
@@ -29802,15 +29802,15 @@ module \dec58
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \asmcode 8'01010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \asmcode 8'01010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \asmcode 8'01100001
     end
@@ -29818,15 +29818,15 @@ module \dec58
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \inv_a 1'0
     end
@@ -29834,15 +29834,15 @@ module \dec58
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \inv_out 1'0
     end
@@ -29850,15 +29850,15 @@ module \dec58
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \cry_out 1'0
     end
@@ -29866,15 +29866,15 @@ module \dec58
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \br 1'0
     end
@@ -29882,15 +29882,15 @@ module \dec58
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \sgn_ext 1'1
     end
@@ -29898,15 +29898,15 @@ module \dec58
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \rsrv 1'0
     end
@@ -29914,15 +29914,15 @@ module \dec58
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \is_32b 1'0
     end
@@ -29930,15 +29930,15 @@ module \dec58
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \sgn 1'0
     end
@@ -29946,15 +29946,15 @@ module \dec58
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \lk 1'0
     end
@@ -29962,15 +29962,15 @@ module \dec58
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'10
         assign \sgl_pipe 1'1
     end
@@ -29980,7 +29980,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec62"
 module \dec62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 input 0 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -29994,7 +29994,7 @@ module \dec62
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 1 \function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -30026,7 +30026,7 @@ module \dec62
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 2 \form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -30101,7 +30101,7 @@ module \dec62
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 3 \internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -30109,7 +30109,7 @@ module \dec62
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 4 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -30126,20 +30126,20 @@ module \dec62
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 5 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 6 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 7 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -30149,7 +30149,7 @@ module \dec62
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -30157,13 +30157,13 @@ module \dec62
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 10 \rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -30171,44 +30171,44 @@ module \dec62
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 11 \ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 12 \upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 13 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 15 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 20 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 23 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 24 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 2 \opcode_switch
   process $group_0
     assign \opcode_switch 2'00
@@ -30217,12 +30217,12 @@ module \dec62
   end
   process $group_1
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \function_unit 11'00000000100
     end
@@ -30230,12 +30230,12 @@ module \dec62
   end
   process $group_2
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \form 5'00101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \form 5'00101
     end
@@ -30243,12 +30243,12 @@ module \dec62
   end
   process $group_3
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \internal_op 7'0100110
     end
@@ -30256,12 +30256,12 @@ module \dec62
   end
   process $group_4
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \in1_sel 3'010
     end
@@ -30269,12 +30269,12 @@ module \dec62
   end
   process $group_5
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \in2_sel 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \in2_sel 4'1000
     end
@@ -30282,12 +30282,12 @@ module \dec62
   end
   process $group_6
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \in3_sel 2'01
     end
@@ -30295,12 +30295,12 @@ module \dec62
   end
   process $group_7
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \out_sel 2'00
     end
@@ -30308,12 +30308,12 @@ module \dec62
   end
   process $group_8
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cr_in 3'000
     end
@@ -30321,12 +30321,12 @@ module \dec62
   end
   process $group_9
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cr_out 3'000
     end
@@ -30334,12 +30334,12 @@ module \dec62
   end
   process $group_10
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \ldst_len 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \ldst_len 4'1000
     end
@@ -30347,12 +30347,12 @@ module \dec62
   end
   process $group_11
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \upd 2'01
     end
@@ -30360,12 +30360,12 @@ module \dec62
   end
   process $group_12
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \rc_sel 2'00
     end
@@ -30373,12 +30373,12 @@ module \dec62
   end
   process $group_13
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cry_in 2'00
     end
@@ -30386,12 +30386,12 @@ module \dec62
   end
   process $group_14
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \asmcode 8'10101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \asmcode 8'10101011
     end
@@ -30399,12 +30399,12 @@ module \dec62
   end
   process $group_15
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \inv_a 1'0
     end
@@ -30412,12 +30412,12 @@ module \dec62
   end
   process $group_16
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \inv_out 1'0
     end
@@ -30425,12 +30425,12 @@ module \dec62
   end
   process $group_17
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \cry_out 1'0
     end
@@ -30438,12 +30438,12 @@ module \dec62
   end
   process $group_18
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \br 1'0
     end
@@ -30451,12 +30451,12 @@ module \dec62
   end
   process $group_19
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \sgn_ext 1'0
     end
@@ -30464,12 +30464,12 @@ module \dec62
   end
   process $group_20
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \rsrv 1'0
     end
@@ -30477,12 +30477,12 @@ module \dec62
   end
   process $group_21
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \is_32b 1'0
     end
@@ -30490,12 +30490,12 @@ module \dec62
   end
   process $group_22
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \sgn 1'0
     end
@@ -30503,12 +30503,12 @@ module \dec62
   end
   process $group_23
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \lk 1'0
     end
@@ -30516,12 +30516,12 @@ module \dec62
   end
   process $group_24
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'00
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 2'01
         assign \sgl_pipe 1'1
     end
@@ -30531,11 +30531,11 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec"
 module \dec
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 input 0 \bigendian
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
   wire width 32 input 1 \raw_opcode_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 output 2 \opcode_in
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -30543,7 +30543,7 @@ module \dec
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 3 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -30560,26 +30560,26 @@ module \dec
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 4 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 5 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 6 \out_sel
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 7 \rc_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -30589,7 +30589,7 @@ module \dec
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 8 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -30597,7 +30597,7 @@ module \dec
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 9 \cr_out
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -30672,7 +30672,7 @@ module \dec
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 10 \internal_op
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -30686,7 +30686,7 @@ module \dec
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 11 \function_unit
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -30694,38 +30694,38 @@ module \dec
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 12 \ldst_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 13 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 14 \inv_out
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 output 15 \cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 16 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 17 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 18 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 19 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 output 20 \LK
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 21 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 22 \sgn_ext
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 23 \upd
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -30757,63 +30757,63 @@ module \dec
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 24 \form
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 25 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 26 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 27 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 28 \RS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 29 \RT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 30 \RA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 31 \RB
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 16 output 32 \SI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 16 output 33 \UI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 34 \SH32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 6 output 35 \sh
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 24 output 36 \LI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 output 37 \Rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 output 38 \OE
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 14 output 39 \BD
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 40 \BB
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 41 \BA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 42 \BT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 43 \BO
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 44 \BI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 14 output 45 \DS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 output 46 \BC
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 10 output 47 \SPR
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 output 48 \X_BF
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 output 49 \X_BFA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 output 50 \XL_BT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 output 51 \XL_XO
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec19_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -30827,7 +30827,7 @@ module \dec
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec19_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -30859,7 +30859,7 @@ module \dec
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec19_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -30934,7 +30934,7 @@ module \dec
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec19_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -30942,7 +30942,7 @@ module \dec
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec19_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -30959,20 +30959,20 @@ module \dec
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec19_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec19_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec19_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -30982,7 +30982,7 @@ module \dec
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec19_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -30990,13 +30990,13 @@ module \dec
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec19_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec19_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -31004,42 +31004,42 @@ module \dec
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec19_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec19_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec19_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec19_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec19_asmcode
   cell \dec19 \dec19
     connect \opcode_in \dec19_opcode_in
@@ -31068,7 +31068,7 @@ module \dec
     connect \sgl_pipe \dec19_sgl_pipe
     connect \asmcode \dec19_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec30_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -31082,7 +31082,7 @@ module \dec
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec30_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -31114,7 +31114,7 @@ module \dec
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec30_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -31189,7 +31189,7 @@ module \dec
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec30_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -31197,7 +31197,7 @@ module \dec
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec30_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -31214,20 +31214,20 @@ module \dec
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec30_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec30_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec30_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -31237,7 +31237,7 @@ module \dec
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec30_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -31245,13 +31245,13 @@ module \dec
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec30_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec30_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -31259,42 +31259,42 @@ module \dec
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec30_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec30_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec30_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec30_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec30_asmcode
   cell \dec30 \dec30
     connect \opcode_in \dec30_opcode_in
@@ -31323,7 +31323,7 @@ module \dec
     connect \sgl_pipe \dec30_sgl_pipe
     connect \asmcode \dec30_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec31_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -31337,7 +31337,7 @@ module \dec
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec31_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -31369,7 +31369,7 @@ module \dec
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec31_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -31444,7 +31444,7 @@ module \dec
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec31_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -31452,7 +31452,7 @@ module \dec
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec31_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -31469,20 +31469,20 @@ module \dec
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec31_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec31_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec31_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -31492,7 +31492,7 @@ module \dec
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec31_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -31500,13 +31500,13 @@ module \dec
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec31_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec31_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -31514,42 +31514,42 @@ module \dec
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec31_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec31_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec31_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec31_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec31_asmcode
   cell \dec31 \dec31
     connect \opcode_in \dec31_opcode_in
@@ -31578,7 +31578,7 @@ module \dec
     connect \sgl_pipe \dec31_sgl_pipe
     connect \asmcode \dec31_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec58_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -31592,7 +31592,7 @@ module \dec
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec58_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -31624,7 +31624,7 @@ module \dec
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec58_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -31699,7 +31699,7 @@ module \dec
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec58_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -31707,7 +31707,7 @@ module \dec
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec58_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -31724,20 +31724,20 @@ module \dec
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec58_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec58_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec58_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -31747,7 +31747,7 @@ module \dec
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec58_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -31755,13 +31755,13 @@ module \dec
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec58_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec58_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -31769,42 +31769,42 @@ module \dec
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec58_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec58_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec58_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec58_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec58_asmcode
   cell \dec58 \dec58
     connect \opcode_in \dec58_opcode_in
@@ -31833,7 +31833,7 @@ module \dec
     connect \sgl_pipe \dec58_sgl_pipe
     connect \asmcode \dec58_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec62_opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -31847,7 +31847,7 @@ module \dec
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 \dec62_function_unit
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -31879,7 +31879,7 @@ module \dec
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 \dec62_form
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -31954,7 +31954,7 @@ module \dec
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 \dec62_internal_op
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -31962,7 +31962,7 @@ module \dec
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 \dec62_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -31979,20 +31979,20 @@ module \dec
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 \dec62_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 \dec62_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 \dec62_out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -32002,7 +32002,7 @@ module \dec
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 \dec62_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -32010,13 +32010,13 @@ module \dec
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 \dec62_cr_out
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 \dec62_rc_sel
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -32024,42 +32024,42 @@ module \dec
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 \dec62_ldst_len
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec62_upd
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec62_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 \dec62_sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 \dec62_asmcode
   cell \dec62 \dec62
     connect \opcode_in \dec62_opcode_in
@@ -32088,7 +32088,7 @@ module \dec
     connect \sgl_pipe \dec62_sgl_pipe
     connect \asmcode \dec62_asmcode
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 6 \opcode_switch
   process $group_0
     assign \opcode_switch 6'000000
@@ -32120,145 +32120,145 @@ module \dec
     assign \dec62_opcode_in \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270"
   wire width 32 \opcode_switch$1
   process $group_6
     assign \function_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \function_unit \dec19_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \function_unit \dec30_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \function_unit \dec31_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \function_unit \dec58_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \function_unit \dec62_function_unit
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \function_unit 11'00010000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \function_unit 11'00000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \function_unit 11'00000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \function_unit 11'00100000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \function_unit 11'00000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \function_unit 11'00000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \function_unit 11'00000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \function_unit 11'00010000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \function_unit 11'00010000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \function_unit 11'00000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \function_unit 11'00000010000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \function_unit 11'00000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \function_unit 11'00000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \function_unit 11'00000000000
     end
@@ -32266,141 +32266,141 @@ module \dec
   end
   process $group_7
     assign \form 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \form \dec19_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \form \dec30_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \form \dec31_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \form \dec58_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \form \dec62_form
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \form 5'00011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \form 5'00010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \form 5'00010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \form 5'00001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \form 5'00010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \form 5'10011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \form 5'10011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \form 5'10011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \form 5'00100
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \form 5'00000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \form 5'00100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \form 5'00000
     end
@@ -32408,141 +32408,141 @@ module \dec
   end
   process $group_8
     assign \internal_op 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \internal_op \dec19_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \internal_op \dec30_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \internal_op \dec31_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \internal_op \dec58_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \internal_op \dec62_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \internal_op 7'1001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \internal_op 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \internal_op 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \internal_op 7'0000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \internal_op 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \internal_op 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \internal_op 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \internal_op 7'0100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \internal_op 7'0110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \internal_op 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \internal_op 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \internal_op 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \internal_op 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \internal_op 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \internal_op 7'0100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \internal_op 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \internal_op 7'0111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \internal_op 7'0111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \internal_op 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \internal_op 7'1000011
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \internal_op 7'0000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \internal_op 7'0000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \internal_op 7'1000100
     end
@@ -32550,141 +32550,141 @@ module \dec
   end
   process $group_9
     assign \in1_sel 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \in1_sel \dec19_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \in1_sel \dec30_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \in1_sel \dec31_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \in1_sel \dec58_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \in1_sel \dec62_in1_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \in1_sel 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \in1_sel 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \in1_sel 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \in1_sel 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \in1_sel 3'100
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \in1_sel 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \in1_sel 3'000
     end
@@ -32692,141 +32692,141 @@ module \dec
   end
   process $group_10
     assign \in2_sel 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \in2_sel \dec19_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \in2_sel \dec30_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \in2_sel \dec31_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \in2_sel \dec58_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \in2_sel \dec62_in2_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \in2_sel 4'0101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \in2_sel 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \in2_sel 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \in2_sel 4'0110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \in2_sel 4'0111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \in2_sel 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \in2_sel 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \in2_sel 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \in2_sel 4'1011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \in2_sel 4'1011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \in2_sel 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \in2_sel 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \in2_sel 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \in2_sel 4'0100
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \in2_sel 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \in2_sel 4'0000
     end
@@ -32834,141 +32834,141 @@ module \dec
   end
   process $group_11
     assign \in3_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \in3_sel \dec19_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \in3_sel \dec30_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \in3_sel \dec31_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \in3_sel \dec58_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \in3_sel \dec62_in3_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \in3_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \in3_sel 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \in3_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \in3_sel 2'00
     end
@@ -32976,141 +32976,141 @@ module \dec
   end
   process $group_12
     assign \out_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \out_sel \dec19_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \out_sel \dec30_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \out_sel \dec31_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \out_sel \dec58_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \out_sel \dec62_out_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \out_sel 2'11
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \out_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \out_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \out_sel 2'10
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \out_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \out_sel 2'01
     end
@@ -33118,141 +33118,141 @@ module \dec
   end
   process $group_13
     assign \cr_in 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \cr_in \dec19_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \cr_in \dec30_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \cr_in \dec31_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \cr_in \dec58_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \cr_in \dec62_cr_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \cr_in 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \cr_in 3'000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \cr_in 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \cr_in 3'000
     end
@@ -33260,141 +33260,141 @@ module \dec
   end
   process $group_14
     assign \cr_out 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \cr_out \dec19_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \cr_out \dec30_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \cr_out \dec31_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \cr_out \dec58_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \cr_out \dec62_cr_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \cr_out 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \cr_out 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \cr_out 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \cr_out 3'000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \cr_out 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \cr_out 3'000
     end
@@ -33402,141 +33402,141 @@ module \dec
   end
   process $group_15
     assign \rc_sel 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \rc_sel \dec19_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \rc_sel \dec30_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \rc_sel \dec31_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \rc_sel \dec58_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \rc_sel \dec62_rc_sel
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \rc_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \rc_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \rc_sel 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \rc_sel 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \rc_sel 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \rc_sel 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \rc_sel 2'00
     end
@@ -33544,141 +33544,141 @@ module \dec
   end
   process $group_16
     assign \ldst_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \ldst_len \dec19_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \ldst_len \dec30_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \ldst_len \dec31_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \ldst_len \dec58_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \ldst_len \dec62_ldst_len
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \ldst_len 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \ldst_len 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \ldst_len 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \ldst_len 4'0000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \ldst_len 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \ldst_len 4'0000
     end
@@ -33686,141 +33686,141 @@ module \dec
   end
   process $group_17
     assign \upd 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \upd \dec19_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \upd \dec30_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \upd \dec31_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \upd \dec58_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \upd \dec62_upd
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \upd 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \upd 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \upd 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \upd 2'00
     end
@@ -33828,141 +33828,141 @@ module \dec
   end
   process $group_18
     assign \cry_in 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \cry_in \dec19_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \cry_in \dec30_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \cry_in \dec31_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \cry_in \dec58_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \cry_in \dec62_cry_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \cry_in 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \cry_in 2'00
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \cry_in 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \cry_in 2'00
     end
@@ -33970,141 +33970,141 @@ module \dec
   end
   process $group_19
     assign \inv_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \inv_a \dec19_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \inv_a \dec30_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \inv_a \dec31_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \inv_a \dec58_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \inv_a \dec62_inv_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \inv_a 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \inv_a 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \inv_a 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \inv_a 1'0
     end
@@ -34112,141 +34112,141 @@ module \dec
   end
   process $group_20
     assign \inv_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \inv_out \dec19_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \inv_out \dec30_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \inv_out \dec31_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \inv_out \dec58_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \inv_out \dec62_inv_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \inv_out 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \inv_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \inv_out 1'0
     end
@@ -34254,141 +34254,141 @@ module \dec
   end
   process $group_21
     assign \cry_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \cry_out \dec19_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \cry_out \dec30_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \cry_out \dec31_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \cry_out \dec58_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \cry_out \dec62_cry_out
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \cry_out 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \cry_out 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \cry_out 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \cry_out 1'0
     end
@@ -34396,141 +34396,141 @@ module \dec
   end
   process $group_22
     assign \br 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \br \dec19_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \br \dec30_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \br \dec31_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \br \dec58_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \br \dec62_br
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \br 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \br 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \br 1'0
     end
@@ -34538,141 +34538,141 @@ module \dec
   end
   process $group_23
     assign \sgn_ext 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \sgn_ext \dec19_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \sgn_ext \dec30_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \sgn_ext \dec31_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \sgn_ext \dec58_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \sgn_ext \dec62_sgn_ext
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \sgn_ext 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \sgn_ext 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \sgn_ext 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \sgn_ext 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \sgn_ext 1'0
     end
@@ -34680,141 +34680,141 @@ module \dec
   end
   process $group_24
     assign \rsrv 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \rsrv \dec19_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \rsrv \dec30_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \rsrv \dec31_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \rsrv \dec58_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \rsrv \dec62_rsrv
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \rsrv 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \rsrv 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \rsrv 1'0
     end
@@ -34822,141 +34822,141 @@ module \dec
   end
   process $group_25
     assign \is_32b 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \is_32b \dec19_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \is_32b \dec30_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \is_32b \dec31_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \is_32b \dec58_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \is_32b \dec62_is_32b
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \is_32b 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \is_32b 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \is_32b 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \is_32b 1'0
     end
@@ -34964,141 +34964,141 @@ module \dec
   end
   process $group_26
     assign \sgn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \sgn \dec19_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \sgn \dec30_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \sgn \dec31_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \sgn \dec58_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \sgn \dec62_sgn
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \sgn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \sgn 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \sgn 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \sgn 1'0
     end
@@ -35106,141 +35106,141 @@ module \dec
   end
   process $group_27
     assign \lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \lk \dec19_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \lk \dec30_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \lk \dec31_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \lk \dec58_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \lk \dec62_lk
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \lk 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \lk 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \lk 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \lk 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \lk 1'0
     end
@@ -35248,141 +35248,141 @@ module \dec
   end
   process $group_28
     assign \sgl_pipe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \sgl_pipe \dec19_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \sgl_pipe \dec30_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \sgl_pipe \dec31_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \sgl_pipe \dec58_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \sgl_pipe \dec62_sgl_pipe
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \sgl_pipe 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \sgl_pipe 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \sgl_pipe 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \sgl_pipe 1'1
     end
@@ -35390,140 +35390,140 @@ module \dec
   end
   process $group_29
     assign \asmcode 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'010011
         assign \asmcode \dec19_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011110
         assign \asmcode \dec30_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'011111
         assign \asmcode \dec31_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111010
         assign \asmcode \dec58_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312"
       case 6'111110
         assign \asmcode \dec62_asmcode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001100
         assign \asmcode 8'00000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001101
         assign \asmcode 8'00001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001110
         assign \asmcode 8'00000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001111
         assign \asmcode 8'00001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011100
         assign \asmcode 8'00010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011101
         assign \asmcode 8'00010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010010
         assign \asmcode 8'00010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010000
         assign \asmcode 8'00010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001011
         assign \asmcode 8'00011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001010
         assign \asmcode 8'00011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100010
         assign \asmcode 8'01001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100011
         assign \asmcode 8'01001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101010
         assign \asmcode 8'01010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101011
         assign \asmcode 8'01011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101000
         assign \asmcode 8'01011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101001
         assign \asmcode 8'01011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100000
         assign \asmcode 8'01100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100001
         assign \asmcode 8'01100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000111
         assign \asmcode 8'01111110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011000
         assign \asmcode 8'10001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011001
         assign \asmcode 8'10001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010100
         assign \asmcode 8'10010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010101
         assign \asmcode 8'10010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'010111
         assign \asmcode 8'10011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100110
         assign \asmcode 8'10100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100111
         assign \asmcode 8'10100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101100
         assign \asmcode 8'10101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'101101
         assign \asmcode 8'10110001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100100
         assign \asmcode 8'10110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'100101
         assign \asmcode 8'10110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'001000
         assign \asmcode 8'10111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000010
         assign \asmcode 8'11000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'000011
         assign \asmcode 8'11001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011010
         assign \asmcode 8'11001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 6'011011
         assign \asmcode 8'11001100
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
     switch \opcode_switch$1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000000---------------0100000000-
         assign \asmcode 8'00010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'01100000000000000000000000000000
         assign \asmcode 8'10000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301"
       case 32'000001---------------0000000011-
         assign \asmcode 8'10011010
     end
@@ -35534,9 +35534,9 @@ module \dec
     assign \opcode_switch$1 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:361"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:364"
   wire width 32 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:361"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:364"
   cell $mux $3
     parameter \WIDTH 32
     connect \A \raw_opcode_in
@@ -35579,7 +35579,7 @@ module \dec
     assign \UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 \L
   process $group_38
     assign \L 1'0
@@ -35596,14 +35596,14 @@ module \dec
     assign \sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \MB32
   process $group_41
     assign \MB32 5'00000
     assign \MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \ME32
   process $group_42
     assign \ME32 5'00000
@@ -35620,7 +35620,7 @@ module \dec
     assign \LK { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 \AA
   process $group_45
     assign \AA 1'0
@@ -35634,7 +35634,7 @@ module \dec
   end
   process $group_47
     assign \OE 1'0
-    assign \OE { \opcode_in [0] }
+    assign \OE { \opcode_in [10] }
     sync init
   end
   process $group_48
@@ -35642,14 +35642,14 @@ module \dec
     assign \BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 3 \BF
   process $group_49
     assign \BF 3'000
     assign \BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 10 \CR
   process $group_50
     assign \CR 10'0000000000
@@ -35671,7 +35671,7 @@ module \dec
     assign \BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 8 \FXM
   process $group_54
     assign \FXM 8'00000000
@@ -35688,14 +35688,14 @@ module \dec
     assign \BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 2 \BH
   process $group_57
     assign \BH 2'00
     assign \BH { \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 16 \D
   process $group_58
     assign \D 16'0000000000000000
@@ -35707,7 +35707,7 @@ module \dec
     assign \DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \TO
   process $group_60
     assign \TO 5'00000
@@ -35719,21 +35719,21 @@ module \dec
     assign \BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \SH
   process $group_62
     assign \SH 5'00000
     assign \SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \ME
   process $group_63
     assign \ME 5'00000
     assign \ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \MB
   process $group_64
     assign \MB 5'00000
@@ -35745,7 +35745,7 @@ module \dec
     assign \SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_A
   process $group_66
     assign \X_A 1'0
@@ -35762,735 +35762,735 @@ module \dec
     assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_BO
   process $group_69
     assign \X_BO 5'00000
     assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \X_CT
   process $group_70
     assign \X_CT 4'0000
     assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 7 \X_DCMX
   process $group_71
     assign \X_DCMX 7'0000000
     assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \X_DRM
   process $group_72
     assign \X_DRM 3'000
     assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_E
   process $group_73
     assign \X_E 1'0
     assign \X_E { \opcode_in [15] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \X_E_1
   process $group_74
     assign \X_E_1 4'0000
     assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \X_EO
   process $group_75
     assign \X_EO 2'00
     assign \X_EO { \opcode_in [20] \opcode_in [19] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_EO_1
   process $group_76
     assign \X_EO_1 5'00000
     assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_EX
   process $group_77
     assign \X_EX 1'0
     assign \X_EX { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FC
   process $group_78
     assign \X_FC 5'00000
     assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRA
   process $group_79
     assign \X_FRA 5'00000
     assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRAp
   process $group_80
     assign \X_FRAp 5'00000
     assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRB
   process $group_81
     assign \X_FRB 5'00000
     assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRBp
   process $group_82
     assign \X_FRBp 5'00000
     assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRS
   process $group_83
     assign \X_FRS 5'00000
     assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRSp
   process $group_84
     assign \X_FRSp 5'00000
     assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRT
   process $group_85
     assign \X_FRT 5'00000
     assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_FRTp
   process $group_86
     assign \X_FRTp 5'00000
     assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \X_IH
   process $group_87
     assign \X_IH 3'000
     assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 8 \X_IMM8
   process $group_88
     assign \X_IMM8 8'00000000
     assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \X_L
   process $group_89
     assign \X_L 2'00
     assign \X_L { \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_L_1
   process $group_90
     assign \X_L_1 1'0
     assign \X_L_1 { \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_L_2
   process $group_91
     assign \X_L_2 1'0
     assign \X_L_2 { \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \X_L_3
   process $group_92
     assign \X_L_3 2'00
     assign \X_L_3 { \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_MO
   process $group_93
     assign \X_MO 5'00000
     assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_NB
   process $group_94
     assign \X_NB 5'00000
     assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_PRS
   process $group_95
     assign \X_PRS 1'0
     assign \X_PRS { \opcode_in [17] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_R
   process $group_96
     assign \X_R 1'0
     assign \X_R { \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_R_1
   process $group_97
     assign \X_R_1 1'0
     assign \X_R_1 { \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_RA
   process $group_98
     assign \X_RA 5'00000
     assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_RB
   process $group_99
     assign \X_RB 5'00000
     assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_Rc
   process $group_100
     assign \X_Rc 1'0
     assign \X_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \X_RIC
   process $group_101
     assign \X_RIC 2'00
     assign \X_RIC { \opcode_in [19] \opcode_in [18] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \X_RM
   process $group_102
     assign \X_RM 2'00
     assign \X_RM { \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_RO
   process $group_103
     assign \X_RO 1'0
     assign \X_RO { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_RS
   process $group_104
     assign \X_RS 5'00000
     assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_RSp
   process $group_105
     assign \X_RSp 5'00000
     assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_RT
   process $group_106
     assign \X_RT 5'00000
     assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_RTp
   process $group_107
     assign \X_RTp 5'00000
     assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_S
   process $group_108
     assign \X_S 5'00000
     assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_SH
   process $group_109
     assign \X_SH 5'00000
     assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_SI
   process $group_110
     assign \X_SI 5'00000
     assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \X_SP
   process $group_111
     assign \X_SP 2'00
     assign \X_SP { \opcode_in [20] \opcode_in [19] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \X_SR
   process $group_112
     assign \X_SR 4'0000
     assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_SX
   process $group_113
     assign \X_SX 1'0
     assign \X_SX { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \X_SX_S
   process $group_114
     assign \X_SX_S 6'000000
     assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_T
   process $group_115
     assign \X_T 5'00000
     assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \X_TBR
   process $group_116
     assign \X_TBR 10'0000000000
     assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_TH
   process $group_117
     assign \X_TH 5'00000
     assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_TO
   process $group_118
     assign \X_TO 5'00000
     assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_TX
   process $group_119
     assign \X_TX 1'0
     assign \X_TX { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \X_TX_T
   process $group_120
     assign \X_TX_T 6'000000
     assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \X_U
   process $group_121
     assign \X_U 4'0000
     assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_UIM
   process $group_122
     assign \X_UIM 5'00000
     assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_VRS
   process $group_123
     assign \X_VRS 5'00000
     assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \X_VRT
   process $group_124
     assign \X_VRT 5'00000
     assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \X_W
   process $group_125
     assign \X_W 1'0
     assign \X_W { \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \X_WC
   process $group_126
     assign \X_WC 2'00
     assign \X_WC { \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \X_XO
   process $group_127
     assign \X_XO 10'0000000000
     assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 8 \X_XO_1
   process $group_128
     assign \X_XO_1 8'00000000
     assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \B_AA
   process $group_129
     assign \B_AA 1'0
     assign \B_AA { \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 14 \B_BD
   process $group_130
     assign \B_BD 14'00000000000000
     assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \B_BI
   process $group_131
     assign \B_BI 5'00000
     assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \B_BO
   process $group_132
     assign \B_BO 5'00000
     assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \B_LK
   process $group_133
     assign \B_LK 1'0
     assign \B_LK { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \I_AA
   process $group_134
     assign \I_AA 1'0
     assign \I_AA { \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 24 \I_LI
   process $group_135
     assign \I_LI 24'000000000000000000000000
     assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \I_LK
   process $group_136
     assign \I_LK 1'0
     assign \I_LK { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX3_AX
   process $group_137
     assign \XX3_AX 1'0
     assign \XX3_AX { \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX3_A
   process $group_138
     assign \XX3_A 5'00000
     assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX3_AX_A
   process $group_139
     assign \XX3_AX_A 6'000000
     assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \XX3_BF
   process $group_140
     assign \XX3_BF 3'000
     assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX3_BX
   process $group_141
     assign \XX3_BX 1'0
     assign \XX3_BX { \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX3_B
   process $group_142
     assign \XX3_B 5'00000
     assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX3_BX_B
   process $group_143
     assign \XX3_BX_B 6'000000
     assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \XX3_DM
   process $group_144
     assign \XX3_DM 2'00
     assign \XX3_DM { \opcode_in [9] \opcode_in [8] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX3_Rc
   process $group_145
     assign \XX3_Rc 1'0
     assign \XX3_Rc { \opcode_in [10] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \XX3_SHW
   process $group_146
     assign \XX3_SHW 2'00
     assign \XX3_SHW { \opcode_in [9] \opcode_in [8] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX3_TX
   process $group_147
     assign \XX3_TX 1'0
     assign \XX3_TX { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX3_T
   process $group_148
     assign \XX3_T 5'00000
     assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX3_TX_T
   process $group_149
     assign \XX3_TX_T 6'000000
     assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \XX3_XO
   process $group_150
     assign \XX3_XO 4'0000
     assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 8 \XX3_XO_1
   process $group_151
     assign \XX3_XO_1 8'00000000
     assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 9 \XX3_XO_2
   process $group_152
     assign \XX3_XO_2 9'000000000
     assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX4_AX
   process $group_153
     assign \XX4_AX 1'0
     assign \XX4_AX { \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX4_A
   process $group_154
     assign \XX4_A 5'00000
     assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX4_AX_A
   process $group_155
     assign \XX4_AX_A 6'000000
     assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX4_BX
   process $group_156
     assign \XX4_BX 1'0
     assign \XX4_BX { \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX4_B
   process $group_157
     assign \XX4_B 5'00000
     assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX4_BX_B
   process $group_158
     assign \XX4_BX_B 6'000000
     assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX4_CX
   process $group_159
     assign \XX4_CX 1'0
     assign \XX4_CX { \opcode_in [3] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX4_C
   process $group_160
     assign \XX4_C 5'00000
     assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX4_CX_C
   process $group_161
     assign \XX4_CX_C 6'000000
     assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX4_TX
   process $group_162
     assign \XX4_TX 1'0
     assign \XX4_TX { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX4_T
   process $group_163
     assign \XX4_T 5'00000
     assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX4_TX_T
   process $group_164
     assign \XX4_TX_T 6'000000
     assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \XX4_XO
   process $group_165
     assign \XX4_XO 2'00
     assign \XX4_XO { \opcode_in [5] \opcode_in [4] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XL_BA
   process $group_166
     assign \XL_BA 5'00000
     assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XL_BB
   process $group_167
     assign \XL_BB 5'00000
     assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \XL_BF
   process $group_168
     assign \XL_BF 3'000
     assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \XL_BFA
   process $group_169
     assign \XL_BFA 3'000
     assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \XL_BH
   process $group_170
     assign \XL_BH 2'00
     assign \XL_BH { \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XL_BI
   process $group_171
     assign \XL_BI 5'00000
     assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XL_BO
   process $group_172
     assign \XL_BO 5'00000
     assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XL_BO_1
   process $group_173
     assign \XL_BO_1 5'00000
@@ -36502,21 +36502,21 @@ module \dec
     assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XL_LK
   process $group_175
     assign \XL_LK 1'0
     assign \XL_LK { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 15 \XL_OC
   process $group_176
     assign \XL_OC 15'000000000000000
     assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XL_S
   process $group_177
     assign \XL_S 1'0
@@ -36528,1253 +36528,1253 @@ module \dec
     assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_BC
   process $group_179
     assign \A_BC 5'00000
     assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_FRA
   process $group_180
     assign \A_FRA 5'00000
     assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_FRB
   process $group_181
     assign \A_FRB 5'00000
     assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_FRC
   process $group_182
     assign \A_FRC 5'00000
     assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_FRT
   process $group_183
     assign \A_FRT 5'00000
     assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_RA
   process $group_184
     assign \A_RA 5'00000
     assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_RB
   process $group_185
     assign \A_RB 5'00000
     assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \A_Rc
   process $group_186
     assign \A_Rc 1'0
     assign \A_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_RT
   process $group_187
     assign \A_RT 5'00000
     assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \A_XO
   process $group_188
     assign \A_XO 5'00000
     assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \D_BF
   process $group_189
     assign \D_BF 3'000
     assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 16 \D_D
   process $group_190
     assign \D_D 16'0000000000000000
     assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \D_FRS
   process $group_191
     assign \D_FRS 5'00000
     assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \D_FRT
   process $group_192
     assign \D_FRT 5'00000
     assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \D_L
   process $group_193
     assign \D_L 1'0
     assign \D_L { \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \D_RA
   process $group_194
     assign \D_RA 5'00000
     assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \D_RS
   process $group_195
     assign \D_RS 5'00000
     assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \D_RT
   process $group_196
     assign \D_RT 5'00000
     assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 16 \D_SI
   process $group_197
     assign \D_SI 16'0000000000000000
     assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \D_TO
   process $group_198
     assign \D_TO 5'00000
     assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 16 \D_UI
   process $group_199
     assign \D_UI 16'0000000000000000
     assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \XX2_BF
   process $group_200
     assign \XX2_BF 3'000
     assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX2_BX
   process $group_201
     assign \XX2_BX 1'0
     assign \XX2_BX { \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX2_B
   process $group_202
     assign \XX2_B 5'00000
     assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX2_BX_B
   process $group_203
     assign \XX2_BX_B 6'000000
     assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX2_dc
   process $group_204
     assign \XX2_dc 1'0
     assign \XX2_dc { \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX2_dm
   process $group_205
     assign \XX2_dm 1'0
     assign \XX2_dm { \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX2_dx
   process $group_206
     assign \XX2_dx 5'00000
     assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 7 \XX2_dc_dm_dx
   process $group_207
     assign \XX2_dc_dm_dx 7'0000000
     assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 7 \XX2_DCMX
   process $group_208
     assign \XX2_DCMX 7'0000000
     assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX2_EO
   process $group_209
     assign \XX2_EO 5'00000
     assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX2_RT
   process $group_210
     assign \XX2_RT 5'00000
     assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XX2_TX
   process $group_211
     assign \XX2_TX 1'0
     assign \XX2_TX { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XX2_T
   process $group_212
     assign \XX2_T 5'00000
     assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XX2_TX_T
   process $group_213
     assign \XX2_TX_T 6'000000
     assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \XX2_UIM
   process $group_214
     assign \XX2_UIM 4'0000
     assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \XX2_UIM_1
   process $group_215
     assign \XX2_UIM_1 2'00
     assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 7 \XX2_XO
   process $group_216
     assign \XX2_XO 7'0000000
     assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 9 \XX2_XO_1
   process $group_217
     assign \XX2_XO_1 9'000000000
     assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \Z22_BF
   process $group_218
     assign \Z22_BF 3'000
     assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \Z22_DCM
   process $group_219
     assign \Z22_DCM 6'000000
     assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \Z22_DGM
   process $group_220
     assign \Z22_DGM 6'000000
     assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z22_FRA
   process $group_221
     assign \Z22_FRA 5'00000
     assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z22_FRAp
   process $group_222
     assign \Z22_FRAp 5'00000
     assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z22_FRT
   process $group_223
     assign \Z22_FRT 5'00000
     assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z22_FRTp
   process $group_224
     assign \Z22_FRTp 5'00000
     assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \Z22_Rc
   process $group_225
     assign \Z22_Rc 1'0
     assign \Z22_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \Z22_SH
   process $group_226
     assign \Z22_SH 6'000000
     assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 9 \Z22_XO
   process $group_227
     assign \Z22_XO 9'000000000
     assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \EVS_BFA
   process $group_228
     assign \EVS_BFA 3'000
     assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \XFX_BHRBE
   process $group_229
     assign \XFX_BHRBE 10'0000000000
     assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XFX_DUI
   process $group_230
     assign \XFX_DUI 5'00000
     assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \XFX_DUIS
   process $group_231
     assign \XFX_DUIS 10'0000000000
     assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 8 \XFX_FXM
   process $group_232
     assign \XFX_FXM 8'00000000
     assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XFX_RS
   process $group_233
     assign \XFX_RS 5'00000
     assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XFX_RT
   process $group_234
     assign \XFX_RT 5'00000
     assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \XFX_SPR
   process $group_235
     assign \XFX_SPR 10'0000000000
     assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \XFX_XO
   process $group_236
     assign \XFX_XO 10'0000000000
     assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \DX_d0
   process $group_237
     assign \DX_d0 10'0000000000
     assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DX_d1
   process $group_238
     assign \DX_d1 5'00000
     assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \DX_d2
   process $group_239
     assign \DX_d2 1'0
     assign \DX_d2 { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 16 \DX_d0_d1_d2
   process $group_240
     assign \DX_d0_d1_d2 16'0000000000000000
     assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DX_RT
   process $group_241
     assign \DX_RT 5'00000
     assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DX_XO
   process $group_242
     assign \DX_XO 5'00000
     assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 12 \DQ_DQ
   process $group_243
     assign \DQ_DQ 12'000000000000
     assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \DQ_PT
   process $group_244
     assign \DQ_PT 4'0000
     assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DQ_RA
   process $group_245
     assign \DQ_RA 5'00000
     assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DQ_RTp
   process $group_246
     assign \DQ_RTp 5'00000
     assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \DQ_SX
   process $group_247
     assign \DQ_SX 1'0
     assign \DQ_SX { \opcode_in [3] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DQ_S
   process $group_248
     assign \DQ_S 5'00000
     assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \DQ_SX_S
   process $group_249
     assign \DQ_SX_S 6'000000
     assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \DQ_TX
   process $group_250
     assign \DQ_TX 1'0
     assign \DQ_TX { \opcode_in [3] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DQ_T
   process $group_251
     assign \DQ_T 5'00000
     assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \DQ_TX_T
   process $group_252
     assign \DQ_TX_T 6'000000
     assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \DQ_XO
   process $group_253
     assign \DQ_XO 3'000
     assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 14 \DS_DS
   process $group_254
     assign \DS_DS 14'00000000000000
     assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_FRSp
   process $group_255
     assign \DS_FRSp 5'00000
     assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_FRTp
   process $group_256
     assign \DS_FRTp 5'00000
     assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_RA
   process $group_257
     assign \DS_RA 5'00000
     assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_RS
   process $group_258
     assign \DS_RS 5'00000
     assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_RSp
   process $group_259
     assign \DS_RSp 5'00000
     assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_RT
   process $group_260
     assign \DS_RT 5'00000
     assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_VRS
   process $group_261
     assign \DS_VRS 5'00000
     assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DS_VRT
   process $group_262
     assign \DS_VRT 5'00000
     assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \DS_XO
   process $group_263
     assign \DS_XO 2'00
     assign \DS_XO { \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_EO
   process $group_264
     assign \VX_EO 5'00000
     assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \VX_PS
   process $group_265
     assign \VX_PS 1'0
     assign \VX_PS { \opcode_in [9] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_RA
   process $group_266
     assign \VX_RA 5'00000
     assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_RT
   process $group_267
     assign \VX_RT 5'00000
     assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_SIM
   process $group_268
     assign \VX_SIM 5'00000
     assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_UIM
   process $group_269
     assign \VX_UIM 5'00000
     assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \VX_UIM_1
   process $group_270
     assign \VX_UIM_1 4'0000
     assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \VX_UIM_2
   process $group_271
     assign \VX_UIM_2 3'000
     assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \VX_UIM_3
   process $group_272
     assign \VX_UIM_3 2'00
     assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_VRA
   process $group_273
     assign \VX_VRA 5'00000
     assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_VRB
   process $group_274
     assign \VX_VRB 5'00000
     assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VX_VRT
   process $group_275
     assign \VX_VRT 5'00000
     assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \VX_XO
   process $group_276
     assign \VX_XO 10'0000000000
     assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 11 \VX_XO_1
   process $group_277
     assign \VX_XO_1 11'00000000000
     assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 8 \XFL_FLM
   process $group_278
     assign \XFL_FLM 8'00000000
     assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XFL_FRB
   process $group_279
     assign \XFL_FRB 5'00000
     assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XFL_L
   process $group_280
     assign \XFL_L 1'0
     assign \XFL_L { \opcode_in [25] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XFL_Rc
   process $group_281
     assign \XFL_Rc 1'0
     assign \XFL_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XFL_W
   process $group_282
     assign \XFL_W 1'0
     assign \XFL_W { \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \XFL_XO
   process $group_283
     assign \XFL_XO 10'0000000000
     assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z23_FRA
   process $group_284
     assign \Z23_FRA 5'00000
     assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z23_FRAp
   process $group_285
     assign \Z23_FRAp 5'00000
     assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z23_FRB
   process $group_286
     assign \Z23_FRB 5'00000
     assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z23_FRBp
   process $group_287
     assign \Z23_FRBp 5'00000
     assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z23_FRT
   process $group_288
     assign \Z23_FRT 5'00000
     assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z23_FRTp
   process $group_289
     assign \Z23_FRTp 5'00000
     assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \Z23_R
   process $group_290
     assign \Z23_R 1'0
     assign \Z23_R { \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \Z23_Rc
   process $group_291
     assign \Z23_Rc 1'0
     assign \Z23_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \Z23_RMC
   process $group_292
     assign \Z23_RMC 2'00
     assign \Z23_RMC { \opcode_in [10] \opcode_in [9] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \Z23_TE
   process $group_293
     assign \Z23_TE 5'00000
     assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 8 \Z23_XO
   process $group_294
     assign \Z23_XO 8'00000000
     assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \MDS_IB
   process $group_295
     assign \MDS_IB 5'00000
     assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \MDS_IS
   process $group_296
     assign \MDS_IS 5'00000
     assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \MDS_mb
   process $group_297
     assign \MDS_mb 6'000000
     assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \MDS_me
   process $group_298
     assign \MDS_me 6'000000
     assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \MDS_RA
   process $group_299
     assign \MDS_RA 5'00000
     assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \MDS_RB
   process $group_300
     assign \MDS_RB 5'00000
     assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \MDS_Rc
   process $group_301
     assign \MDS_Rc 1'0
     assign \MDS_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \MDS_RS
   process $group_302
     assign \MDS_RS 5'00000
     assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \MDS_XBI
   process $group_303
     assign \MDS_XBI 4'0000
     assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \MDS_XBI_1
   process $group_304
     assign \MDS_XBI_1 4'0000
     assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \MDS_XO
   process $group_305
     assign \MDS_XO 4'0000
     assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 7 \SC_LEV
   process $group_306
     assign \SC_LEV 7'0000000
     assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \SC_XO
   process $group_307
     assign \SC_XO 1'0
     assign \SC_XO { \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \SC_XO_1
   process $group_308
     assign \SC_XO_1 2'00
     assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \M_MB
   process $group_309
     assign \M_MB 5'00000
     assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \M_ME
   process $group_310
     assign \M_ME 5'00000
     assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \M_RA
   process $group_311
     assign \M_RA 5'00000
     assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \M_RB
   process $group_312
     assign \M_RB 5'00000
     assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \M_Rc
   process $group_313
     assign \M_Rc 1'0
     assign \M_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \M_RS
   process $group_314
     assign \M_RS 5'00000
     assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \M_SH
   process $group_315
     assign \M_SH 5'00000
     assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \MD_mb
   process $group_316
     assign \MD_mb 6'000000
     assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \MD_me
   process $group_317
     assign \MD_me 6'000000
     assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \MD_RA
   process $group_318
     assign \MD_RA 5'00000
     assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \MD_Rc
   process $group_319
     assign \MD_Rc 1'0
     assign \MD_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \MD_RS
   process $group_320
     assign \MD_RS 5'00000
     assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \MD_sh
   process $group_321
     assign \MD_sh 6'000000
     assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \MD_XO
   process $group_322
     assign \MD_XO 3'000
     assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \all_OPCD
   process $group_323
     assign \all_OPCD 6'000000
     assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \all_PO
   process $group_324
     assign \all_PO 6'000000
     assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XO_OE
   process $group_325
     assign \XO_OE 1'0
     assign \XO_OE { \opcode_in [10] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XO_RA
   process $group_326
     assign \XO_RA 5'00000
     assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XO_RB
   process $group_327
     assign \XO_RB 5'00000
     assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XO_Rc
   process $group_328
     assign \XO_Rc 1'0
     assign \XO_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XO_RT
   process $group_329
     assign \XO_RT 5'00000
     assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 9 \XO_XO
   process $group_330
     assign \XO_XO 9'000000000
     assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DQE_RA
   process $group_331
     assign \DQE_RA 5'00000
     assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \DQE_RT
   process $group_332
     assign \DQE_RT 5'00000
     assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 2 \DQE_XO
   process $group_333
     assign \DQE_XO 2'00
     assign \DQE_XO { \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \TX_RA
   process $group_334
     assign \TX_RA 5'00000
     assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \TX_UI
   process $group_335
     assign \TX_UI 5'00000
     assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \TX_XBI
   process $group_336
     assign \TX_XBI 4'0000
     assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \TX_XO
   process $group_337
     assign \TX_XO 6'000000
     assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_RA
   process $group_338
     assign \VA_RA 5'00000
     assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_RB
   process $group_339
     assign \VA_RB 5'00000
     assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_RC
   process $group_340
     assign \VA_RC 5'00000
     assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_RT
   process $group_341
     assign \VA_RT 5'00000
     assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 4 \VA_SHB
   process $group_342
     assign \VA_SHB 4'0000
     assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_VRA
   process $group_343
     assign \VA_VRA 5'00000
     assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_VRB
   process $group_344
     assign \VA_VRB 5'00000
     assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_VRC
   process $group_345
     assign \VA_VRC 5'00000
     assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VA_VRT
   process $group_346
     assign \VA_VRT 5'00000
     assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \VA_XO
   process $group_347
     assign \VA_XO 6'000000
     assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XS_RA
   process $group_348
     assign \XS_RA 5'00000
     assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \XS_Rc
   process $group_349
     assign \XS_Rc 1'0
     assign \XS_Rc { \opcode_in [0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \XS_RS
   process $group_350
     assign \XS_RS 5'00000
     assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 6 \XS_sh
   process $group_351
     assign \XS_sh 6'000000
     assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 9 \XS_XO
   process $group_352
     assign \XS_XO 9'000000000
     assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 1 \VC_Rc
   process $group_353
     assign \VC_Rc 1'0
     assign \VC_Rc { \opcode_in [10] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VC_VRA
   process $group_354
     assign \VC_VRA 5'00000
     assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VC_VRB
   process $group_355
     assign \VC_VRB 5'00000
     assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \VC_VRT
   process $group_356
     assign \VC_VRT 5'00000
     assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \VC_XO
   process $group_357
     assign \VC_XO 10'0000000000
@@ -37785,7 +37785,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_a.sprmap"
 module \sprmap
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
   wire width 10 input 0 \spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -37898,340 +37898,340 @@ module \sprmap
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 output 1 \spr_o
   process $group_0
     assign \spr_o 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
     switch \spr_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000000001
         assign \spr_o 10'0000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000000011
         assign \spr_o 10'0000000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000001000
         assign \spr_o 10'0000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000001001
         assign \spr_o 10'0000000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000001101
         assign \spr_o 10'0000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010001
         assign \spr_o 10'0000000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010010
         assign \spr_o 10'0000000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010011
         assign \spr_o 10'0000000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010110
         assign \spr_o 10'0000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011010
         assign \spr_o 10'0000001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011011
         assign \spr_o 10'0000001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011100
         assign \spr_o 10'0000001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011101
         assign \spr_o 10'0000001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000110000
         assign \spr_o 10'0000001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000111101
         assign \spr_o 10'0000001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000000
         assign \spr_o 10'0000001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000001
         assign \spr_o 10'0000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000010
         assign \spr_o 10'0000010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000011
         assign \spr_o 10'0000010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010001000
         assign \spr_o 10'0000010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010010000
         assign \spr_o 10'0000010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011000
         assign \spr_o 10'0000010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011001
         assign \spr_o 10'0000010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011101
         assign \spr_o 10'0000010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011110
         assign \spr_o 10'0000011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011111
         assign \spr_o 10'0000011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010110000
         assign \spr_o 10'0000011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010110100
         assign \spr_o 10'0000011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111010
         assign \spr_o 10'0000011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111011
         assign \spr_o 10'0000011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111100
         assign \spr_o 10'0000011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111110
         assign \spr_o 10'0000011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100000000
         assign \spr_o 10'0000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100000011
         assign \spr_o 10'0000100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100001100
         assign \spr_o 10'0000100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100001101
         assign \spr_o 10'0000100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010000
         assign \spr_o 10'0000100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010001
         assign \spr_o 10'0000100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010010
         assign \spr_o 10'0000100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010011
         assign \spr_o 10'0000100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011011
         assign \spr_o 10'0000101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011100
         assign \spr_o 10'0000101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011101
         assign \spr_o 10'0000101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011110
         assign \spr_o 10'0000101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011111
         assign \spr_o 10'0000101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110000
         assign \spr_o 10'0000101101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110001
         assign \spr_o 10'0000101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110010
         assign \spr_o 10'0000101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110011
         assign \spr_o 10'0000110000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110100
         assign \spr_o 10'0000110001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110101
         assign \spr_o 10'0000110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110110
         assign \spr_o 10'0000110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111001
         assign \spr_o 10'0000110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111010
         assign \spr_o 10'0000110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111011
         assign \spr_o 10'0000110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111110
         assign \spr_o 10'0000110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111111
         assign \spr_o 10'0000111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010000
         assign \spr_o 10'0000111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010001
         assign \spr_o 10'0000111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010010
         assign \spr_o 10'0000111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010011
         assign \spr_o 10'0000111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101011101
         assign \spr_o 10'0000111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0110111110
         assign \spr_o 10'0000111110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0111010000
         assign \spr_o 10'0000111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000000
         assign \spr_o 10'0001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000001
         assign \spr_o 10'0001000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000010
         assign \spr_o 10'0001000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000011
         assign \spr_o 10'0001000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000100
         assign \spr_o 10'0001000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000101
         assign \spr_o 10'0001000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000110
         assign \spr_o 10'0001000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000111
         assign \spr_o 10'0001000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001000
         assign \spr_o 10'0001001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001011
         assign \spr_o 10'0001001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001100
         assign \spr_o 10'0001001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001101
         assign \spr_o 10'0001001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001110
         assign \spr_o 10'0001001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010000
         assign \spr_o 10'0001001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010001
         assign \spr_o 10'0001001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010010
         assign \spr_o 10'0001001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010011
         assign \spr_o 10'0001010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010100
         assign \spr_o 10'0001010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010101
         assign \spr_o 10'0001010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010110
         assign \spr_o 10'0001010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010111
         assign \spr_o 10'0001010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011000
         assign \spr_o 10'0001010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011011
         assign \spr_o 10'0001010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011100
         assign \spr_o 10'0001010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011101
         assign \spr_o 10'0001011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011110
         assign \spr_o 10'0001011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100000
         assign \spr_o 10'0001011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100001
         assign \spr_o 10'0001011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100010
         assign \spr_o 10'0001011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100011
         assign \spr_o 10'0001011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100100
         assign \spr_o 10'0001011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100101
         assign \spr_o 10'0001011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100110
         assign \spr_o 10'0001100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101000
         assign \spr_o 10'0001100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101001
         assign \spr_o 10'0001100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101010
         assign \spr_o 10'0001100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101011
         assign \spr_o 10'0001100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101111
         assign \spr_o 10'0001100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100110000
         assign \spr_o 10'0001100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100110111
         assign \spr_o 10'0001100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1101010000
         assign \spr_o 10'0001101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1101010001
         assign \spr_o 10'0001101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1101010111
         assign \spr_o 10'0001101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1110000000
         assign \spr_o 10'0001101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1110000010
         assign \spr_o 10'0001101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1111111111
         assign \spr_o 10'0001101101
     end
@@ -38247,7 +38247,7 @@ module \dec_a
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
   wire width 3 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -38322,13 +38322,13 @@ module \dec_a
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 input 1 \internal_op
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 2 \reg_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \reg_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
   wire width 1 output 4 \immz_out
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -38441,25 +38441,25 @@ module \dec_a
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 5 \spr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 6 \spr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 7 \fast_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 8 \fast_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 9 \RS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 10 \RA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 11 \BO
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 10 input 12 \SPR
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 input 13 \XL_XO
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
   wire width 10 \sprmap_spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -38572,22 +38572,22 @@ module \dec_a
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 \sprmap_spr_o
   cell \sprmap \sprmap
     connect \spr_i \sprmap_spr_i
     connect \spr_o \sprmap_spr_o
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89"
   wire width 5 \ra
   process $group_0
     assign \ra 5'00000
     assign \ra \RA
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
   cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38598,9 +38598,9 @@ module \dec_a
     connect \B 3'001
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38611,9 +38611,9 @@ module \dec_a
     connect \B 3'010
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $ne $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -38624,9 +38624,9 @@ module \dec_a
     connect \B 5'00000
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $and $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38637,9 +38637,9 @@ module \dec_a
     connect \B $5
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38650,9 +38650,9 @@ module \dec_a
     connect \B $7
     connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
   cell $eq $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38665,23 +38665,23 @@ module \dec_a
   end
   process $group_1
     assign \reg_a 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
     switch { $9 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
       case 1'1
         assign \reg_a \ra
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
     switch { $11 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
       case 1'1
         assign \reg_a \RS
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
   cell $eq $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38692,9 +38692,9 @@ module \dec_a
     connect \B 3'001
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   cell $eq $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38705,9 +38705,9 @@ module \dec_a
     connect \B 3'010
     connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $ne $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -38718,9 +38718,9 @@ module \dec_a
     connect \B 5'00000
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $and $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38731,9 +38731,9 @@ module \dec_a
     connect \B $17
     connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $or $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38744,9 +38744,9 @@ module \dec_a
     connect \B $19
     connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
   cell $eq $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38759,23 +38759,23 @@ module \dec_a
   end
   process $group_2
     assign \reg_a_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
     switch { $21 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
       case 1'1
         assign \reg_a_ok 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
     switch { $23 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
       case 1'1
         assign \reg_a_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
   wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
   cell $eq $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38786,9 +38786,9 @@ module \dec_a
     connect \B 3'010
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
   wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
   cell $eq $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -38799,9 +38799,9 @@ module \dec_a
     connect \B 5'00000
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
   wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
   cell $and $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38814,17 +38814,17 @@ module \dec_a
   end
   process $group_3
     assign \immz_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
     switch { $29 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
       case 1'1
         assign \immz_out 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
   cell $not $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38832,9 +38832,9 @@ module \dec_a
     connect \A \BO [2]
     connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38842,9 +38842,9 @@ module \dec_a
     connect \A \XL_XO [5]
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   cell $and $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38855,61 +38855,61 @@ module \dec_a
     connect \B $33
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
   wire width 10 \spr
   process $group_4
     assign \fast_a 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
         switch { $31 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
           case 1'1
             assign \fast_a 3'010
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
         switch { $35 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
           case 1'1
             assign \fast_a 3'010
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
           case 10'0000001001
             assign \fast_a 3'010
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
           case 10'0000001000
             assign \fast_a 3'011
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
           case 10'1100101111
             assign \fast_a 3'100
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
           case 10'0000011010
             assign \fast_a 3'101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
           case 10'0000011011
             assign \fast_a 3'110
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
           case
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
   cell $not $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38917,9 +38917,9 @@ module \dec_a
     connect \A \BO [2]
     connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38927,9 +38927,9 @@ module \dec_a
     connect \A \XL_XO [5]
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
   cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38942,49 +38942,49 @@ module \dec_a
   end
   process $group_5
     assign \fast_a_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
         switch { $37 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
           case 1'1
             assign \fast_a_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
         switch { $41 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
           case 1'1
             assign \fast_a_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
           case 10'0000001001
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
           case 10'0000001000
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
           case 10'1100101111
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
           case 10'0000011010
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
           case 10'0000011011
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
           case
         end
     end
@@ -38992,15 +38992,15 @@ module \dec_a
   end
   process $group_6
     assign \spr 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
         assign \spr { \SPR [4:0] \SPR [9:5] }
@@ -39009,32 +39009,32 @@ module \dec_a
   end
   process $group_7
     assign \sprmap_spr_i 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
-          case 10'0000001001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
-          case 10'0000001000
+          case 10'0000001001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
-          case 10'1100101111
+          case 10'0000001000
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
-          case 10'0000011010
+          case 10'1100101111
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
-          case 10'0000011011
+          case 10'0000011010
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          case 10'0000011011
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
           case
             assign \sprmap_spr_i \spr
         end
@@ -39043,32 +39043,32 @@ module \dec_a
   end
   process $group_8
     assign \spr_a 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
-          case 10'0000001001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
-          case 10'0000001000
+          case 10'0000001001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
-          case 10'1100101111
+          case 10'0000001000
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
-          case 10'0000011010
+          case 10'1100101111
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
-          case 10'0000011011
+          case 10'0000011010
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          case 10'0000011011
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
           case
             assign \spr_a \sprmap_spr_o
         end
@@ -39077,32 +39077,32 @@ module \dec_a
   end
   process $group_9
     assign \spr_a_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
-          case 10'0000001001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
-          case 10'0000001000
+          case 10'0000001001
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
-          case 10'1100101111
+          case 10'0000001000
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
-          case 10'0000011010
+          case 10'1100101111
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
-          case 10'0000011011
+          case 10'0000011010
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          case 10'0000011011
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
           case
             assign \spr_a_ok 1'1
         end
@@ -39128,7 +39128,7 @@ module \dec_b
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
   wire width 4 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -39203,80 +39203,80 @@ module \dec_b
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 input 1 \internal_op
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 2 \reg_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \reg_b_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 4 \imm_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \imm_b_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 6 \fast_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 7 \fast_b_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 8 \RS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 9 \RB
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 16 input 10 \SI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 16 input 11 \UI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 12 \SH32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 6 input 13 \sh
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 24 input 14 \LI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 14 input 15 \BD
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 14 input 16 \DS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 input 17 \XL_XO
   process $group_0
     assign \reg_b 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
         assign \reg_b \RB
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
         assign \reg_b \RS
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
       attribute \nmigen.decoding "CONST_UI_HI/4"
       case 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
       attribute \nmigen.decoding "CONST_SI_HI/5"
       case 4'0101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
     end
@@ -39284,52 +39284,52 @@ module \dec_b
   end
   process $group_1
     assign \reg_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
         assign \reg_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
         assign \reg_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
       attribute \nmigen.decoding "CONST_UI_HI/4"
       case 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
       attribute \nmigen.decoding "CONST_SI_HI/5"
       case 4'0101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 64 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   cell $pos $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39337,11 +39337,11 @@ module \dec_b
     connect \A \UI
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
   wire width 64 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
   wire width 47 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
   cell $sshl $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39352,7 +39352,7 @@ module \dec_b
     connect \B 5'10000
     connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
   cell $pos $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 47
@@ -39360,11 +39360,11 @@ module \dec_b
     connect \A $4
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
   wire width 64 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
   wire width 47 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
   cell $sshl $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39375,7 +39375,7 @@ module \dec_b
     connect \B 5'10000
     connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
   cell $pos $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 47
@@ -39383,11 +39383,11 @@ module \dec_b
     connect \A $8
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39399,11 +39399,11 @@ module \dec_b
     connect \Y $12
   end
   connect $11 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39415,11 +39415,11 @@ module \dec_b
     connect \Y $15
   end
   connect $14 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39431,11 +39431,11 @@ module \dec_b
     connect \Y $18
   end
   connect $17 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39447,11 +39447,11 @@ module \dec_b
     connect \Y $21
   end
   connect $20 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39463,11 +39463,11 @@ module \dec_b
     connect \Y $24
   end
   connect $23 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39479,11 +39479,11 @@ module \dec_b
     connect \Y $27
   end
   connect $26 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39495,11 +39495,11 @@ module \dec_b
     connect \Y $30
   end
   connect $29 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   wire width 47 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
   cell $sshl $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39511,11 +39511,11 @@ module \dec_b
     connect \Y $33
   end
   connect $32 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
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@@ -39527,11 +39527,11 @@ module \dec_b
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
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     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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   end
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39607,11 +39607,11 @@ module \dec_b
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   end
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
@@ -39623,11 +39623,11 @@ module \dec_b
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   end
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
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     parameter \A_SIGNED 0
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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     parameter \A_SIGNED 0
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:200"
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     parameter \A_SIGNED 0
     parameter \A_WIDTH 14
@@ -39949,7 +39949,7 @@ module \dec_b
     connect \B 2'10
     connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
   cell $pos $117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 17
@@ -39957,11 +39957,11 @@ module \dec_b
     connect \A $115
     connect \Y $114
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
   wire width 64 $118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
   wire width 17 $119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
   cell $sshl $120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 14
@@ -39972,7 +39972,7 @@ module \dec_b
     connect \B 2'10
     connect \Y $119
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
   cell $pos $121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 17
@@ -39980,9 +39980,9 @@ module \dec_b
     connect \A $119
     connect \Y $118
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
   wire width 64 $122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
   cell $not $123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -39990,9 +39990,9 @@ module \dec_b
     connect \A 64'0000000000000000000000000000000000000000000000000000000000000000
     connect \Y $122
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 64 $124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   cell $pos $125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -40000,9 +40000,9 @@ module \dec_b
     connect \A \sh
     connect \Y $124
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 64 $126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   cell $pos $127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -40012,52 +40012,52 @@ module \dec_b
   end
   process $group_2
     assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
         assign \imm_b $1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
         assign \imm_b { { \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] } \SI }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
       attribute \nmigen.decoding "CONST_UI_HI/4"
       case 4'0100
         assign \imm_b $3
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
       attribute \nmigen.decoding "CONST_SI_HI/5"
       case 4'0101
         assign \imm_b $7
         assign \imm_b { { $14 [31:0] [31] $17 [31:0] [31] $20 [31:0] [31] $23 [31:0] [31] $26 [31:0] [31] $29 [31:0] [31] $32 [31:0] [31] $35 [31:0] [31] $38 [31:0] [31] $41 [31:0] [31] $44 [31:0] [31] $47 [31:0] [31] $50 [31:0] [31] $53 [31:0] [31] $56 [31:0] [31] $59 [31:0] [31] $62 [31:0] [31] $65 [31:0] [31] $68 [31:0] [31] $71 [31:0] [31] $74 [31:0] [31] $77 [31:0] [31] $80 [31:0] [31] $83 [31:0] [31] $86 [31:0] [31] $89 [31:0] [31] $92 [31:0] [31] $95 [31:0] [31] $98 [31:0] [31] $101 [31:0] [31] $104 [31:0] [31] $107 [31:0] [31] } $11 [31:0] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
         assign \imm_b $110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
         assign \imm_b $114
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
         assign \imm_b $118
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
         assign \imm_b $122
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
         assign \imm_b $124
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
         assign \imm_b $126
@@ -40066,60 +40066,60 @@ module \dec_b
   end
   process $group_3
     assign \imm_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
       attribute \nmigen.decoding "CONST_UI_HI/4"
       case 4'0100
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
       attribute \nmigen.decoding "CONST_SI_HI/5"
       case 4'0101
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
         assign \imm_b_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
   wire width 1 $128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
   cell $eq $129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -40130,9 +40130,9 @@ module \dec_b
     connect \B 7'0001000
     connect \Y $128
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
   wire width 1 $130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
   cell $not $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -40142,25 +40142,25 @@ module \dec_b
   end
   process $group_4
     assign \fast_b 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
     switch { $128 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
         switch { \XL_XO [5] $130 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
           case 2'-1
             assign \fast_b 3'011
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232"
           case 2'1-
             assign \fast_b 3'100
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
   wire width 1 $132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
   cell $eq $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -40171,9 +40171,9 @@ module \dec_b
     connect \B 7'0001000
     connect \Y $132
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
   wire width 1 $134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
   cell $not $135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -40183,16 +40183,16 @@ module \dec_b
   end
   process $group_5
     assign \fast_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
     switch { $132 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
         switch { \XL_XO [5] $134 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
           case 2'-1
             assign \fast_b_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232"
           case 2'1-
             assign \fast_b_ok 1'1
         end
@@ -40207,25 +40207,25 @@ module \dec_c
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247"
   wire width 2 input 0 \sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 1 \reg_c
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \reg_c_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 3 \RS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 4 \RB
   process $group_0
     assign \reg_c 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
       attribute \nmigen.decoding "RB/2"
       case 2'10
         assign \reg_c \RB
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
       attribute \nmigen.decoding "RS/1"
       case 2'01
         assign \reg_c \RS
@@ -40234,13 +40234,13 @@ module \dec_c
   end
   process $group_1
     assign \reg_c_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
       attribute \nmigen.decoding "RB/2"
       case 2'10
         assign \reg_c_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
       attribute \nmigen.decoding "RS/1"
       case 2'01
         assign \reg_c_ok 1'1
@@ -40251,7 +40251,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o.sprmap"
 module \sprmap$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
   wire width 10 input 0 \spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -40364,340 +40364,340 @@ module \sprmap$1
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 output 1 \spr_o
   process $group_0
     assign \spr_o 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
     switch \spr_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000000001
         assign \spr_o 10'0000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000000011
         assign \spr_o 10'0000000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000001000
         assign \spr_o 10'0000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000001001
         assign \spr_o 10'0000000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000001101
         assign \spr_o 10'0000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010001
         assign \spr_o 10'0000000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010010
         assign \spr_o 10'0000000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010011
         assign \spr_o 10'0000000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000010110
         assign \spr_o 10'0000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011010
         assign \spr_o 10'0000001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011011
         assign \spr_o 10'0000001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011100
         assign \spr_o 10'0000001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000011101
         assign \spr_o 10'0000001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000110000
         assign \spr_o 10'0000001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0000111101
         assign \spr_o 10'0000001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000000
         assign \spr_o 10'0000001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000001
         assign \spr_o 10'0000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000010
         assign \spr_o 10'0000010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010000011
         assign \spr_o 10'0000010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010001000
         assign \spr_o 10'0000010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010010000
         assign \spr_o 10'0000010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011000
         assign \spr_o 10'0000010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011001
         assign \spr_o 10'0000010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011101
         assign \spr_o 10'0000010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011110
         assign \spr_o 10'0000011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010011111
         assign \spr_o 10'0000011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010110000
         assign \spr_o 10'0000011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010110100
         assign \spr_o 10'0000011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111010
         assign \spr_o 10'0000011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111011
         assign \spr_o 10'0000011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111100
         assign \spr_o 10'0000011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0010111110
         assign \spr_o 10'0000011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100000000
         assign \spr_o 10'0000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100000011
         assign \spr_o 10'0000100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100001100
         assign \spr_o 10'0000100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100001101
         assign \spr_o 10'0000100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010000
         assign \spr_o 10'0000100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010001
         assign \spr_o 10'0000100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010010
         assign \spr_o 10'0000100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100010011
         assign \spr_o 10'0000100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011011
         assign \spr_o 10'0000101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011100
         assign \spr_o 10'0000101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011101
         assign \spr_o 10'0000101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011110
         assign \spr_o 10'0000101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100011111
         assign \spr_o 10'0000101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110000
         assign \spr_o 10'0000101101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110001
         assign \spr_o 10'0000101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110010
         assign \spr_o 10'0000101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110011
         assign \spr_o 10'0000110000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110100
         assign \spr_o 10'0000110001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110101
         assign \spr_o 10'0000110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100110110
         assign \spr_o 10'0000110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111001
         assign \spr_o 10'0000110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111010
         assign \spr_o 10'0000110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111011
         assign \spr_o 10'0000110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111110
         assign \spr_o 10'0000110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0100111111
         assign \spr_o 10'0000111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010000
         assign \spr_o 10'0000111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010001
         assign \spr_o 10'0000111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010010
         assign \spr_o 10'0000111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101010011
         assign \spr_o 10'0000111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0101011101
         assign \spr_o 10'0000111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0110111110
         assign \spr_o 10'0000111110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'0111010000
         assign \spr_o 10'0000111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000000
         assign \spr_o 10'0001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000001
         assign \spr_o 10'0001000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000010
         assign \spr_o 10'0001000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000011
         assign \spr_o 10'0001000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000100
         assign \spr_o 10'0001000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000101
         assign \spr_o 10'0001000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000110
         assign \spr_o 10'0001000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100000111
         assign \spr_o 10'0001000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001000
         assign \spr_o 10'0001001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001011
         assign \spr_o 10'0001001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001100
         assign \spr_o 10'0001001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001101
         assign \spr_o 10'0001001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100001110
         assign \spr_o 10'0001001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010000
         assign \spr_o 10'0001001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010001
         assign \spr_o 10'0001001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010010
         assign \spr_o 10'0001001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010011
         assign \spr_o 10'0001010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010100
         assign \spr_o 10'0001010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010101
         assign \spr_o 10'0001010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010110
         assign \spr_o 10'0001010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100010111
         assign \spr_o 10'0001010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011000
         assign \spr_o 10'0001010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011011
         assign \spr_o 10'0001010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011100
         assign \spr_o 10'0001010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011101
         assign \spr_o 10'0001011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100011110
         assign \spr_o 10'0001011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100000
         assign \spr_o 10'0001011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100001
         assign \spr_o 10'0001011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100010
         assign \spr_o 10'0001011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100011
         assign \spr_o 10'0001011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100100
         assign \spr_o 10'0001011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100101
         assign \spr_o 10'0001011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100100110
         assign \spr_o 10'0001100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101000
         assign \spr_o 10'0001100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101001
         assign \spr_o 10'0001100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101010
         assign \spr_o 10'0001100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101011
         assign \spr_o 10'0001100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100101111
         assign \spr_o 10'0001100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100110000
         assign \spr_o 10'0001100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1100110111
         assign \spr_o 10'0001100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1101010000
         assign \spr_o 10'0001101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1101010001
         assign \spr_o 10'0001101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1101010111
         assign \spr_o 10'0001101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1110000000
         assign \spr_o 10'0001101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1110000010
         assign \spr_o 10'0001101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
       case 10'1111111111
         assign \spr_o 10'0001101101
     end
@@ -40712,7 +40712,7 @@ module \dec_o
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
   wire width 2 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -40787,11 +40787,11 @@ module \dec_o
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 input 1 \internal_op
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 2 \reg_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \reg_o_ok
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -40904,23 +40904,23 @@ module \dec_o
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 4 \spr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \spr_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 6 \fast_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 7 \fast_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 8 \RT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 9 \RA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 10 \BO
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 10 input 11 \SPR
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
   wire width 10 \sprmap_spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -41033,7 +41033,7 @@ module \dec_o
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 \sprmap_spr_o
   cell \sprmap$1 \sprmap
     connect \spr_i \sprmap_spr_i
@@ -41041,17 +41041,17 @@ module \dec_o
   end
   process $group_0
     assign \reg_o 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
         assign \reg_o \RT
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
         assign \reg_o \RA
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
     end
@@ -41059,44 +41059,44 @@ module \dec_o
   end
   process $group_1
     assign \reg_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
         assign \reg_o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
         assign \reg_o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297"
   wire width 10 \spr
   process $group_2
     assign \spr 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
         assign \spr { \SPR [4:0] \SPR [9:5] }
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41107,9 +41107,9 @@ module \dec_o
     connect \B 7'0110001
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
   cell $not $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -41119,66 +41119,66 @@ module \dec_o
   end
   process $group_3
     assign \fast_o 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
         switch { $1 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
               case 10'0000001001
                 assign \fast_o 3'010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
               case 10'0000001000
                 assign \fast_o 3'011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
               case 10'1100101111
                 assign \fast_o 3'100
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
               case 10'0000011010
                 assign \fast_o 3'101
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
               case 10'0000011011
                 assign \fast_o 3'110
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case
             end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
       attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8"
       case 7'0000111, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
         switch { $3 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
           case 1'1
             assign \fast_o 3'010
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o 3'101
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   cell $eq $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41189,9 +41189,9 @@ module \dec_o
     connect \B 7'0110001
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
   cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -41201,66 +41201,66 @@ module \dec_o
   end
   process $group_4
     assign \fast_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
         switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
               case 10'0000001001
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
               case 10'0000001000
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
               case 10'1100101111
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
               case 10'0000011010
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
               case 10'0000011011
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case
             end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
       attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8"
       case 7'0000111, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
         switch { $7 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
           case 1'1
             assign \fast_o_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   cell $eq $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41273,36 +41273,36 @@ module \dec_o
   end
   process $group_5
     assign \sprmap_spr_i 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
         switch { $9 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
               case 10'0000001001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
               case 10'0000001000
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
               case 10'1100101111
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
               case 10'0000011010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
               case 10'0000011011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case
                 assign \sprmap_spr_i \spr
             end
@@ -41310,9 +41310,9 @@ module \dec_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   cell $eq $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41325,36 +41325,36 @@ module \dec_o
   end
   process $group_6
     assign \spr_o 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
         switch { $11 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
               case 10'0000001001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
               case 10'0000001000
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
               case 10'1100101111
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
               case 10'0000011010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
               case 10'0000011011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case
                 assign \spr_o \sprmap_spr_o
             end
@@ -41362,9 +41362,9 @@ module \dec_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
   cell $eq $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41377,36 +41377,36 @@ module \dec_o
   end
   process $group_7
     assign \spr_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
         switch { $13 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
               case 10'0000001001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
               case 10'0000001000
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
               case 10'1100101111
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
               case 10'0000011010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
               case 10'0000011011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case
                 assign \spr_o_ok 1'1
             end
@@ -41418,7 +41418,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o2"
 module \dec_o2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:353"
   wire width 1 input 0 \lk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -41493,28 +41493,28 @@ module \dec_o2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 input 1 \internal_op
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 2 \reg_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \reg_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 4 \fast_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \fast_o_ok
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 input 6 \upd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 7 \RA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
   cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -41525,9 +41525,9 @@ module \dec_o2
     connect \B 2'01
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 6 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   cell $pos $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -41538,9 +41538,9 @@ module \dec_o2
   process $group_0
     assign \reg_o 5'00000
     assign \reg_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
     switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
       case 1'1
         assign { \reg_o_ok \reg_o } $3
         assign \reg_o_ok 1'1
@@ -41549,18 +41549,18 @@ module \dec_o2
   end
   process $group_2
     assign \fast_o 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:370"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
       attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8"
       case 7'0000111, 7'0000110, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
         switch { \lk }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
           case 1'1
             assign \fast_o 3'011
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:379"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o 3'110
@@ -41569,18 +41569,18 @@ module \dec_o2
   end
   process $group_3
     assign \fast_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:370"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
       attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8"
       case 7'0000111, 7'0000110, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
         switch { \lk }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
           case 1'1
             assign \fast_o_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:379"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o_ok 1'1
@@ -41595,27 +41595,27 @@ module \dec_rc
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:387"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394"
   wire width 2 input 0 \sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 input 3 \Rc
   process $group_0
     assign \rc 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
       attribute \nmigen.decoding "RC/2"
       case 2'10
         assign \rc \Rc
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:400"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
       attribute \nmigen.decoding "ONE/1"
       case 2'01
         assign \rc 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
       attribute \nmigen.decoding "NONE/0"
       case 2'00
         assign \rc 1'0
@@ -41624,17 +41624,17 @@ module \dec_rc
   end
   process $group_1
     assign \rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
       attribute \nmigen.decoding "RC/2"
       case 2'10
         assign \rc_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:400"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
       attribute \nmigen.decoding "ONE/1"
       case 2'01
         assign \rc_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
       attribute \nmigen.decoding "NONE/0"
       case 2'00
         assign \rc_ok 1'1
@@ -41649,7 +41649,7 @@ module \dec_oe
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:431"
   wire width 2 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -41724,27 +41724,27 @@ module \dec_oe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 input 1 \internal_op
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 input 4 \OE
   process $group_0
     assign \oe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:435"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443"
       attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52"
       case 7'0110011, 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447"
       attribute \nmigen.decoding ""
       case
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449"
         switch \sel_in
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
           attribute \nmigen.decoding "RC/2"
           case 2'10
             assign \oe \OE
@@ -41754,17 +41754,17 @@ module \dec_oe
   end
   process $group_1
     assign \oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:435"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443"
       attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52"
       case 7'0110011, 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447"
       attribute \nmigen.decoding ""
       case
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449"
         switch \sel_in
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
           attribute \nmigen.decoding "RC/2"
           case 2'10
             assign \oe_ok 1'1
@@ -41784,63 +41784,63 @@ module \dec_cr_in
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
   wire width 3 input 0 \sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 1 \cr_bitfield
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \cr_bitfield_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 3 \cr_bitfield_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \cr_bitfield_b_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 5 \cr_bitfield_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 6 \cr_bitfield_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
   wire width 1 output 7 \whole_reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 8 \BB
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 9 \BA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 10 \BT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 11 \BI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 12 \BC
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 input 13 \X_BFA
   process $group_0
     assign \cr_bitfield_ok 1'0
     assign \cr_bitfield_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
       attribute \nmigen.decoding "BI/2"
       case 3'010
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BC/5"
       case 3'101
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41849,28 +41849,28 @@ module \dec_cr_in
   process $group_1
     assign \cr_bitfield_b_ok 1'0
     assign \cr_bitfield_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41879,27 +41879,27 @@ module \dec_cr_in
   process $group_2
     assign \whole_reg 1'0
     assign \whole_reg 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
         assign \whole_reg 1'1
@@ -41908,32 +41908,32 @@ module \dec_cr_in
   end
   process $group_3
     assign \cr_bitfield 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
       attribute \nmigen.decoding "BI/2"
       case 3'010
         assign \cr_bitfield \BI [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
         assign \cr_bitfield \X_BFA
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield \BA [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BC/5"
       case 3'101
         assign \cr_bitfield \BC [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41941,28 +41941,28 @@ module \dec_cr_in
   end
   process $group_4
     assign \cr_bitfield_b 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_b \BB [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41970,28 +41970,28 @@ module \dec_cr_in
   end
   process $group_5
     assign \cr_bitfield_o 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_o \BT [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41999,28 +41999,28 @@ module \dec_cr_in
   end
   process $group_6
     assign \cr_bitfield_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -42036,41 +42036,41 @@ module \dec_cr_out
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518"
   wire width 3 input 0 \sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517"
   wire width 1 input 1 \rc_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 2 \cr_bitfield
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \cr_bitfield_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
   wire width 1 output 4 \whole_reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 input 5 \X_BF
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 input 6 \XL_BT
   process $group_0
     assign \cr_bitfield_ok 1'0
     assign \cr_bitfield_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield_ok \rc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:535"
       attribute \nmigen.decoding "BF/2"
       case 3'010
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:538"
       attribute \nmigen.decoding "BT/3"
       case 3'011
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:541"
       attribute \nmigen.decoding "WHOLE_REG/4"
       case 3'100
     end
@@ -42079,21 +42079,21 @@ module \dec_cr_out
   process $group_1
     assign \whole_reg 1'0
     assign \whole_reg 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:535"
       attribute \nmigen.decoding "BF/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:538"
       attribute \nmigen.decoding "BT/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:541"
       attribute \nmigen.decoding "WHOLE_REG/4"
       case 3'100
         assign \whole_reg 1'1
@@ -42102,24 +42102,24 @@ module \dec_cr_out
   end
   process $group_2
     assign \cr_bitfield 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:535"
       attribute \nmigen.decoding "BF/2"
       case 3'010
         assign \cr_bitfield \X_BF
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:538"
       attribute \nmigen.decoding "BT/3"
       case 3'011
         assign \cr_bitfield \XL_BT [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:541"
       attribute \nmigen.decoding "WHOLE_REG/4"
       case 3'100
     end
@@ -42129,13 +42129,13 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2"
 module \pdecode2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 input 0 \bigendian
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
   wire width 32 input 1 \raw_opcode_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574"
   wire width 64 input 2 \msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
   wire width 64 input 3 \cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -42210,7 +42210,7 @@ module \pdecode2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
   wire width 7 output 4 \insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -42224,108 +42224,108 @@ module \pdecode2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40"
   wire width 11 output 5 \fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 6 \imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 7 \imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 8 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 9 \rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 10 \oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 11 \oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
-  wire width 1 output 12 \invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
+  wire width 1 output 12 \invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
   wire width 1 output 13 \zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
   wire width 1 output 14 \invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
   wire width 1 output 15 \write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
-  wire width 2 output 16 \input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+  wire width 2 output 16 \input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
   wire width 1 output 17 \output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
-  wire width 1 output 18 \is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
-  wire width 1 output 19 \is_signed
+  wire width 1 output 18 \is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+  wire width 1 output 19 \is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
   wire width 4 output 20 \data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
   wire width 32 output 21 \insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 22 \reg1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 23 \reg2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
   wire width 1 output 24 \xer_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
-  wire width 1 output 25 \read_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
+  wire width 1 output 25 \read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
   wire width 1 output 26 \write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \cr_in1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 28 \cr_in2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \cr_in2_ok$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
   wire width 64 output 30 \cia$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
   wire width 1 output 31 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 32 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
   wire width 64 output 34 \msr$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
-  wire width 5 output 35 \traptype
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+  wire width 5 output 35 \traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
   wire width 13 output 36 \trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 37 \spr1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
-  wire width 1 output 38 \input_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+  wire width 1 output 38 \input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
   wire width 1 output 39 \output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 40 \reg3_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
-  wire width 1 output 41 \byte_reverse
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+  wire width 1 output 41 \byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
   wire width 1 output 42 \sign_extend
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
   wire width 2 output 43 \ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 44 \reg1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 45 \reg2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 46 \reg3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 47 \cr_in1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 48 \cr_in2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 49 \cr_in2$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 50 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 51 \fast2
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -42438,17 +42438,17 @@ module \pdecode2
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 52 \spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 53 \rego
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 54 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 55 \cr_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 56 \fasto1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 57 \fasto2
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -42561,9 +42561,9 @@ module \pdecode2
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 58 \spro
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 output 59 \opcode_in
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -42571,7 +42571,7 @@ module \pdecode2
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 60 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -42588,26 +42588,26 @@ module \pdecode2
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 61 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 62 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 63 \out_sel
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 64 \rc_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -42617,7 +42617,7 @@ module \pdecode2
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 65 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -42625,7 +42625,7 @@ module \pdecode2
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 66 \cr_out$5
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -42700,7 +42700,7 @@ module \pdecode2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 67 \internal_op
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -42714,19 +42714,19 @@ module \pdecode2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 68 \function_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 69 \rego_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 70 \ea_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 71 \spro_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 72 \fasto1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 73 \fasto2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 74 \cr_out_ok
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -42734,27 +42734,27 @@ module \pdecode2
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 75 \ldst_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 76 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 77 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 78 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 79 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 80 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 81 \lk$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 82 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 83 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83"
   wire width 1 output 84 \xer_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
   wire width 8 output 85 \asmcode
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -42786,76 +42786,76 @@ module \pdecode2
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 86 \form
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 87 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 88 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 89 \asmcode$7
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_cry_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 \dec_LK
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 \dec_upd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_RS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_RT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_RA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_RB
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 16 \dec_SI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 16 \dec_UI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_SH32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 6 \dec_sh
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 24 \dec_LI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 \dec_Rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 \dec_OE
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 14 \dec_BD
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_BB
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_BA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_BT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_BO
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_BI
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 14 \dec_DS
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 \dec_BC
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 10 \dec_SPR
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \dec_X_BF
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 \dec_X_BFA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 5 \dec_XL_BT
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 \dec_XL_XO
   cell \dec \dec
     connect \bigendian \bigendian
@@ -42917,13 +42917,13 @@ module \pdecode2
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
   wire width 3 \dec_a_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_a_reg_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_a_reg_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
   wire width 1 \dec_a_immz_out
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -43036,13 +43036,13 @@ module \pdecode2
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 \dec_a_spr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_a_spr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_a_fast_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_a_fast_a_ok
   cell \dec_a \dec_a
     connect \sel_in \dec_a_sel_in
@@ -43075,19 +43075,19 @@ module \pdecode2
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
   wire width 4 \dec_b_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_b_reg_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_b_reg_b_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \dec_b_imm_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_b_imm_b_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_b_fast_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_b_fast_b_ok
   cell \dec_b \dec_b
     connect \sel_in \dec_b_sel_in
@@ -43113,11 +43113,11 @@ module \pdecode2
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247"
   wire width 2 \dec_c_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_c_reg_c
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_c_reg_c_ok
   cell \dec_c \dec_c
     connect \sel_in \dec_c_sel_in
@@ -43131,11 +43131,11 @@ module \pdecode2
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
   wire width 2 \dec_o_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_o_reg_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_o_reg_o_ok
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -43248,13 +43248,13 @@ module \pdecode2
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 \dec_o_spr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_o_spr_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_o_fast_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_o_fast_o_ok
   cell \dec_o \dec_o
     connect \sel_in \dec_o_sel_in
@@ -43270,15 +43270,15 @@ module \pdecode2
     connect \BO \dec_BO
     connect \SPR \dec_SPR
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:353"
   wire width 1 \dec_o2_lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_o2_reg_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_o2_reg_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_o2_fast_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_o2_fast_o_ok
   cell \dec_o2 \dec_o2
     connect \lk \dec_o2_lk
@@ -43294,11 +43294,11 @@ module \pdecode2
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:387"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394"
   wire width 2 \dec_rc_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_rc_rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_rc_rc_ok
   cell \dec_rc \dec_rc
     connect \sel_in \dec_rc_sel_in
@@ -43310,11 +43310,11 @@ module \pdecode2
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:431"
   wire width 2 \dec_oe_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_oe_oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_oe_oe_ok
   cell \dec_oe \dec_oe
     connect \sel_in \dec_oe_sel_in
@@ -43331,21 +43331,21 @@ module \pdecode2
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
   wire width 3 \dec_cr_in_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_cr_in_cr_bitfield
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_cr_in_cr_bitfield_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_cr_in_cr_bitfield_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_cr_in_cr_bitfield_b_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_cr_in_cr_bitfield_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_cr_in_cr_bitfield_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
   wire width 1 \dec_cr_in_whole_reg
   cell \dec_cr_in \dec_cr_in
     connect \sel_in \dec_cr_in_sel_in
@@ -43369,15 +43369,15 @@ module \pdecode2
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518"
   wire width 3 \dec_cr_out_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517"
   wire width 1 \dec_cr_out_rc_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_cr_out_cr_bitfield
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_cr_out_cr_bitfield_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
   wire width 1 \dec_cr_out_whole_reg
   cell \dec_cr_out \dec_cr_out
     connect \sel_in \dec_cr_out_sel_in
@@ -43388,9 +43388,9 @@ module \pdecode2
     connect \X_BF \dec_X_BF
     connect \XL_BT \dec_XL_BT
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
   wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
   cell $eq $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -43401,9 +43401,9 @@ module \pdecode2
     connect \B 7'0101110
     connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
   wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
   cell $eq $11
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -43414,9 +43414,9 @@ module \pdecode2
     connect \B 7'0110001
     connect \Y $10
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
   wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
   cell $eq $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -43429,9 +43429,9 @@ module \pdecode2
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:37"
   wire width 1 \is_priv_insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
   wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
   cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -43442,9 +43442,9 @@ module \pdecode2
     connect \B \msr [14]
     connect \Y $14
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
   wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
   cell $eq $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -43455,9 +43455,9 @@ module \pdecode2
     connect \B 7'0000000
     connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
   wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
   cell $eq $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -43468,9 +43468,9 @@ module \pdecode2
     connect \B 7'0111111
     connect \Y $18
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
   wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
   cell $eq $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -43481,9 +43481,9 @@ module \pdecode2
     connect \B 7'1001001
     connect \Y $20
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
   wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
   cell $or $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -43494,9 +43494,9 @@ module \pdecode2
     connect \B $20
     connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
   cell $eq $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -43605,9 +43605,9 @@ module \pdecode2
     assign \output_carry \cry_out
     assign \is_32bit \is_32b
     assign \is_signed \sgn
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:656"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:666"
     switch { \lk$6 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:656"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:666"
       case 1'1
         assign \lk \dec_LK
     end
@@ -43631,27 +43631,27 @@ module \pdecode2
       case
         assign \output_cr \cr_out$5 [0]
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
     switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
       case 1'1
         assign \xer_in 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
     switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
       case 1'1
         assign \xer_out 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
     switch { $12 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
       case 1'1
         assign \trapaddr 13'0000001110000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
     switch { $16 $14 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
       case 2'-1
         assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
         assign \insn \opcode_in
@@ -43661,7 +43661,7 @@ module \pdecode2
         assign \traptype 5'00010
         assign \msr$3 \msr
         assign \cia$2 \cia
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
       case 2'1-
         assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
         assign \insn \opcode_in
@@ -43672,18 +43672,18 @@ module \pdecode2
         assign \msr$3 \msr
         assign \cia$2 \cia
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
     switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
       case 1'1
         assign \fasto1 3'101
         assign \fasto1_ok 1'1
         assign \fasto2 3'110
         assign \fasto2_ok 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
     switch { $24 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
       case 1'1
         assign \fast1 3'101
         assign \fast1_ok 1'1
@@ -43692,63 +43692,63 @@ module \pdecode2
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:77"
   wire width 32 \insn_in
   process $group_1
     assign \insn_in 32'00000000000000000000000000000000
     assign \insn_in \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:167"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170"
   wire width 32 \insn_in$26
   process $group_2
     assign \insn_in$26 32'00000000000000000000000000000000
     assign \insn_in$26 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248"
   wire width 32 \insn_in$27
   process $group_3
     assign \insn_in$27 32'00000000000000000000000000000000
     assign \insn_in$27 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:272"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
   wire width 32 \insn_in$28
   process $group_4
     assign \insn_in$28 32'00000000000000000000000000000000
     assign \insn_in$28 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:348"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354"
   wire width 32 \insn_in$29
   process $group_5
     assign \insn_in$29 32'00000000000000000000000000000000
     assign \insn_in$29 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395"
   wire width 32 \insn_in$30
   process $group_6
     assign \insn_in$30 32'00000000000000000000000000000000
     assign \insn_in$30 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:424"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
   wire width 32 \insn_in$31
   process $group_7
     assign \insn_in$31 32'00000000000000000000000000000000
     assign \insn_in$31 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:458"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467"
   wire width 32 \insn_in$32
   process $group_8
     assign \insn_in$32 32'00000000000000000000000000000000
     assign \insn_in$32 \opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:510"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519"
   wire width 32 \insn_in$33
   process $group_9
     assign \insn_in$33 32'00000000000000000000000000000000
@@ -43780,7 +43780,7 @@ module \pdecode2
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:346"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352"
   wire width 2 \sel_in
   process $group_14
     assign \sel_in 2'00
@@ -43875,9 +43875,9 @@ module \n
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -43931,9 +43931,9 @@ module \n$3
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -43953,7 +43953,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.input"
 module \input
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -44028,8 +44028,8 @@ module \input
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -44042,53 +44042,53 @@ module \input
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 13 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 17 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 18 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 13 \alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 19 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 20 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 21 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 22 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 23 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -44163,8 +44163,8 @@ module \input
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 24 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 24 \alu_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -44177,51 +44177,51 @@ module \input
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 25 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 26 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 25 \alu_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 26 \alu_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \alu_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \alu_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \alu_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \alu_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \alu_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \alu_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \alu_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \alu_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \alu_op__write_cr0$13
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 36 \op__input_carry$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 38 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 40 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 41 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 36 \alu_op__input_carry$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \alu_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \alu_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \alu_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 40 \alu_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 41 \alu_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 42 \ra$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 43 \rb$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 output 44 \xer_so$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 output 45 \xer_ca$23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
   wire width 64 \a
@@ -44238,7 +44238,7 @@ module \input
   process $group_0
     assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
-    switch { \op__invert_a }
+    switch { \alu_op__invert_a }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
       case 1'1
         assign \a $24
@@ -44256,7 +44256,7 @@ module \input
   process $group_2
     assign \xer_ca$23 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
-    switch \op__input_carry
+    switch \alu_op__input_carry
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
       attribute \nmigen.decoding "ZERO/0"
       case 2'00
@@ -44275,7 +44275,7 @@ module \input
   process $group_3
     assign \xer_so$22 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
-    switch { \op__oe__oe_ok }
+    switch { \alu_op__oe__oe_ok }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
       case 1'1
         assign \xer_so$22 \xer_so
@@ -44288,25 +44288,25 @@ module \input
     sync init
   end
   process $group_5
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__input_carry$14 2'00
-    assign \op__output_carry$15 1'0
-    assign \op__is_32bit$16 1'0
-    assign \op__is_signed$17 1'0
-    assign \op__data_len$18 4'0000
-    assign \op__insn$19 32'00000000000000000000000000000000
-    assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__input_carry$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \alu_op__insn_type$2 7'0000000
+    assign \alu_op__fn_unit$3 11'00000000000
+    assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_op__imm_data__imm_ok$5 1'0
+    assign \alu_op__rc__rc$6 1'0
+    assign \alu_op__rc__rc_ok$7 1'0
+    assign \alu_op__oe__oe$8 1'0
+    assign \alu_op__oe__oe_ok$9 1'0
+    assign \alu_op__invert_a$10 1'0
+    assign \alu_op__zero_a$11 1'0
+    assign \alu_op__invert_out$12 1'0
+    assign \alu_op__write_cr0$13 1'0
+    assign \alu_op__input_carry$14 2'00
+    assign \alu_op__output_carry$15 1'0
+    assign \alu_op__is_32bit$16 1'0
+    assign \alu_op__is_signed$17 1'0
+    assign \alu_op__data_len$18 4'0000
+    assign \alu_op__insn$19 32'00000000000000000000000000000000
+    assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_a$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type }
     sync init
   end
   process $group_23
@@ -44318,7 +44318,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.main"
 module \main
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -44393,8 +44393,8 @@ module \main
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -44407,53 +44407,53 @@ module \main
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 13 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 17 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 18 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 13 \alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 19 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 20 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 21 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 22 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 23 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -44528,8 +44528,8 @@ module \main
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 24 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 24 \alu_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -44542,67 +44542,67 @@ module \main
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 25 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 26 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 25 \alu_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 26 \alu_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \alu_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \alu_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \alu_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \alu_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \alu_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \alu_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \alu_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \alu_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \alu_op__write_cr0$13
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 36 \op__input_carry$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 38 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 40 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 41 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 36 \alu_op__input_carry$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \alu_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \alu_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \alu_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 40 \alu_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 41 \alu_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 42 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 43 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 44 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 45 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 46 \xer_ca$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 47 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 48 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 49 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 50 \xer_so$21
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:39"
   wire width 1 \is_32bit
   process $group_0
     assign \is_32bit 1'0
-    assign \is_32bit \op__is_32bit
+    assign \is_32bit \alu_op__is_32bit
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:40"
@@ -44633,7 +44633,7 @@ module \main
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0000010
     connect \Y $24
   end
@@ -44646,7 +44646,7 @@ module \main
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0001010
     connect \Y $26
   end
@@ -44684,7 +44684,7 @@ module \main
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0000010
     connect \Y $30
   end
@@ -44697,7 +44697,7 @@ module \main
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0001010
     connect \Y $32
   end
@@ -44735,7 +44735,7 @@ module \main
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0000010
     connect \Y $36
   end
@@ -44748,7 +44748,7 @@ module \main
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0001010
     connect \Y $38
   end
@@ -44791,50 +44791,50 @@ module \main
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98"
   cell $eq $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \op__data_len
+    connect \A \alu_op__data_len
     connect \B 1'1
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
   cell $eq $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \op__data_len
+    connect \A \alu_op__data_len
     connect \B 2'10
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
   cell $eq $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \op__data_len
+    connect \A \alu_op__data_len
     connect \B 3'100
     connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110"
   wire width 8 \eqs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115"
   cell $reduce_or $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -44845,37 +44845,37 @@ module \main
   process $group_5
     assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
         assign \o \add_o [64:1]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \o \add_o [64:1]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98"
         switch { $45 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98"
           case 1'1
             assign \o { { \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] } \ra [7:0] }
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
         switch { $47 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
           case 1'1
             assign \o { { \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] } \ra [15:0] }
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
         switch { $49 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
           case 1'1
             assign \o { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] }
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
         assign \o [0] $51
@@ -44885,31 +44885,31 @@ module \main
   process $group_6
     assign \o_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
         assign \o_ok 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
         assign \o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
         assign \o_ok 1'0
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82"
   wire width 2 \ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84"
   wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84"
   cell $xor $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -44920,9 +44920,9 @@ module \main
     connect \B \rb [32]
     connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84"
   cell $xor $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -44936,19 +44936,19 @@ module \main
   process $group_7
     assign \ca 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \ca [0] \add_o [65]
         assign \ca [1] $55
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
     end
@@ -44957,18 +44957,18 @@ module \main
   process $group_8
     assign \xer_ca$20 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \xer_ca$20 \ca
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
     end
@@ -44977,24 +44977,24 @@ module \main
   process $group_9
     assign \xer_ca_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \xer_ca_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:88"
   wire width 2 \ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
   wire width 1 $57
@@ -45097,19 +45097,19 @@ module \main
   process $group_10
     assign \ov 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \ov [0] $63
         assign \ov [1] $71
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
     end
@@ -45118,18 +45118,18 @@ module \main
   process $group_11
     assign \xer_ov 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \xer_ov \ov
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
     end
@@ -45138,48 +45138,48 @@ module \main
   process $group_12
     assign \xer_ov_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
         assign \xer_ov_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:111"
   wire width 8 \src1
   process $group_13
     assign \src1 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
         assign \src1 \ra [7:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45190,9 +45190,9 @@ module \main
     connect \B \rb [7:0]
     connect \Y $73
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $76
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45203,9 +45203,9 @@ module \main
     connect \B \rb [15:8]
     connect \Y $75
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $78
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45216,9 +45216,9 @@ module \main
     connect \B \rb [23:16]
     connect \Y $77
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $80
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45229,9 +45229,9 @@ module \main
     connect \B \rb [31:24]
     connect \Y $79
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45242,9 +45242,9 @@ module \main
     connect \B \rb [39:32]
     connect \Y $81
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45255,9 +45255,9 @@ module \main
     connect \B \rb [47:40]
     connect \Y $83
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $86
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45268,9 +45268,9 @@ module \main
     connect \B \rb [55:48]
     connect \Y $85
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   wire width 1 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114"
   cell $eq $88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45284,17 +45284,17 @@ module \main
   process $group_14
     assign \eqs 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
         assign \eqs [0] $73
@@ -45308,9 +45308,9 @@ module \main
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117"
   wire width 1 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117"
   cell $reduce_or $90
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -45321,17 +45321,17 @@ module \main
   process $group_15
     assign \cr_a 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
         assign \cr_a { 1'0 $89 2'00 }
@@ -45341,17 +45341,17 @@ module \main
   process $group_16
     assign \cr_a_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
+    switch \alu_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64"
       attribute \nmigen.decoding "OP_CMP/10"
       case 7'0001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75"
       attribute \nmigen.decoding "OP_ADD/2"
       case 7'0000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97"
       attribute \nmigen.decoding "OP_EXTS/31"
       case 7'0011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109"
       attribute \nmigen.decoding "OP_CMPEQB/12"
       case 7'0001100
         assign \cr_a_ok 1'1
@@ -45369,32 +45369,32 @@ module \main
     sync init
   end
   process $group_19
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__input_carry$14 2'00
-    assign \op__output_carry$15 1'0
-    assign \op__is_32bit$16 1'0
-    assign \op__is_signed$17 1'0
-    assign \op__data_len$18 4'0000
-    assign \op__insn$19 32'00000000000000000000000000000000
-    assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__input_carry$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \alu_op__insn_type$2 7'0000000
+    assign \alu_op__fn_unit$3 11'00000000000
+    assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_op__imm_data__imm_ok$5 1'0
+    assign \alu_op__rc__rc$6 1'0
+    assign \alu_op__rc__rc_ok$7 1'0
+    assign \alu_op__oe__oe$8 1'0
+    assign \alu_op__oe__oe_ok$9 1'0
+    assign \alu_op__invert_a$10 1'0
+    assign \alu_op__zero_a$11 1'0
+    assign \alu_op__invert_out$12 1'0
+    assign \alu_op__write_cr0$13 1'0
+    assign \alu_op__input_carry$14 2'00
+    assign \alu_op__output_carry$15 1'0
+    assign \alu_op__is_32bit$16 1'0
+    assign \alu_op__is_signed$17 1'0
+    assign \alu_op__data_len$18 4'0000
+    assign \alu_op__insn$19 32'00000000000000000000000000000000
+    assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_a$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type }
     sync init
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.output"
 module \output
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -45469,8 +45469,8 @@ module \output
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -45483,57 +45483,57 @@ module \output
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 13 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 17 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 18 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 13 \alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 19 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 20 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 input 21 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 input 22 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 input 23 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 24 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 25 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -45608,8 +45608,8 @@ module \output
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 26 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 26 \alu_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -45622,63 +45622,63 @@ module \output
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 27 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 28 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 27 \alu_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 28 \alu_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \alu_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \alu_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \alu_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \alu_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \alu_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \alu_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \alu_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \alu_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \alu_op__write_cr0$13
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 38 \op__input_carry$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 40 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 41 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 42 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 43 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 38 \alu_op__input_carry$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \alu_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \alu_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 41 \alu_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 42 \alu_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 43 \alu_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 44 \o$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 45 \o_ok$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 46 \cr_a$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 47 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 48 \xer_ca$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 49 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 50 \xer_ov$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 51 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 52 \xer_so$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 53 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
   wire width 65 \o$26
@@ -45702,9 +45702,9 @@ module \output
     connect \A $28
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 65 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   cell $pos $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -45715,7 +45715,7 @@ module \output
   process $group_0
     assign \o$26 65'00000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
-    switch { \op__invert_out }
+    switch { \alu_op__invert_out }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
       case 1'1
         assign \o$26 $27
@@ -45739,7 +45739,7 @@ module \output
   end
   process $group_3
     assign \xer_ca_ok 1'0
-    assign \xer_ca_ok \op__output_carry
+    assign \xer_ca_ok \alu_op__output_carry
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
@@ -45753,7 +45753,7 @@ module \output
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0001010
     connect \Y $33
   end
@@ -45773,7 +45773,7 @@ module \output
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \alu_op__insn_type
     connect \B 7'0001100
     connect \Y $35
   end
@@ -45924,7 +45924,7 @@ module \output
   end
   process $group_14
     assign \cr_a_ok 1'0
-    assign \cr_a_ok \op__write_cr0
+    assign \cr_a_ok \alu_op__write_cr0
     sync init
   end
   process $group_15
@@ -45933,25 +45933,25 @@ module \output
     sync init
   end
   process $group_16
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__input_carry$14 2'00
-    assign \op__output_carry$15 1'0
-    assign \op__is_32bit$16 1'0
-    assign \op__is_signed$17 1'0
-    assign \op__data_len$18 4'0000
-    assign \op__insn$19 32'00000000000000000000000000000000
-    assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__input_carry$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \alu_op__insn_type$2 7'0000000
+    assign \alu_op__fn_unit$3 11'00000000000
+    assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_op__imm_data__imm_ok$5 1'0
+    assign \alu_op__rc__rc$6 1'0
+    assign \alu_op__rc__rc_ok$7 1'0
+    assign \alu_op__oe__oe$8 1'0
+    assign \alu_op__oe__oe_ok$9 1'0
+    assign \alu_op__invert_a$10 1'0
+    assign \alu_op__zero_a$11 1'0
+    assign \alu_op__invert_out$12 1'0
+    assign \alu_op__write_cr0$13 1'0
+    assign \alu_op__input_carry$14 2'00
+    assign \alu_op__output_carry$15 1'0
+    assign \alu_op__is_32bit$16 1'0
+    assign \alu_op__is_signed$17 1'0
+    assign \alu_op__data_len$18 4'0000
+    assign \alu_op__insn$19 32'00000000000000000000000000000000
+    assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_a$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28"
@@ -45965,8 +45965,8 @@ module \output
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \op__oe__oe
-    connect \B \op__oe__oe_ok
+    connect \A \alu_op__oe__oe
+    connect \B \alu_op__oe__oe_ok
     connect \Y $49
   end
   process $group_34
@@ -46051,7 +46051,7 @@ module \pipe
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -46126,8 +46126,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -46140,59 +46140,59 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 7 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 17 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 20 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 21 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 22 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 17 \alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 21 \alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 22 \alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 23 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 24 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 25 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 26 \xer_ca
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 27 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 28 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 29 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -46267,10 +46267,10 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 30 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 30 \alu_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -46283,117 +46283,117 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 31 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 32 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 38 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 40 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 41 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 31 \alu_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 32 \alu_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_op__imm_data__imm$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \alu_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__imm_data__imm_ok$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \alu_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__rc__rc$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \alu_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__rc__rc_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \alu_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__oe__oe$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \alu_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \alu_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__invert_a$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \alu_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__zero_a$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \alu_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__invert_out$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 41 \alu_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__write_cr0$13$next
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 42 \op__input_carry$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 43 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 44 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 45 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 46 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \op__data_len$18$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 47 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$19$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 42 \alu_op__input_carry$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \alu_op__input_carry$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 43 \alu_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__output_carry$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 44 \alu_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__is_32bit$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 45 \alu_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__is_signed$17$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 46 \alu_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \alu_op__data_len$18$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 47 \alu_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_op__insn$19$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 48 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 49 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 50 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 51 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 52 \xer_ca$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$20$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 53 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 54 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ov$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 55 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 56 \xer_so$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so$21$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 57 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$next
   cell \p$2 \p
     connect \p_valid_i \p_valid_i
@@ -46403,7 +46403,7 @@ module \pipe
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -46478,8 +46478,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -46492,53 +46492,53 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \input_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \input_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \input_alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \input_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \input_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid$22
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -46613,8 +46613,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_alu_op__insn_type$23
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -46627,101 +46627,101 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_a$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__zero_a$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_out$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__write_cr0$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_alu_op__fn_unit$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_alu_op__imm_data__imm$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__imm_data__imm_ok$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__rc__rc$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__rc__rc_ok$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__oe__oe$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__oe__oe_ok$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__invert_a$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__zero_a$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__invert_out$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__write_cr0$34
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \input_op__input_carry$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_carry$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \input_op__data_len$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_alu_op__input_carry$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__output_carry$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__is_32bit$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_alu_op__is_signed$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \input_alu_op__data_len$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_alu_op__insn$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \input_xer_so$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \input_xer_ca$44
   cell \input \input
     connect \muxid \input_muxid
-    connect \op__insn_type \input_op__insn_type
-    connect \op__fn_unit \input_op__fn_unit
-    connect \op__imm_data__imm \input_op__imm_data__imm
-    connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
-    connect \op__rc__rc \input_op__rc__rc
-    connect \op__rc__rc_ok \input_op__rc__rc_ok
-    connect \op__oe__oe \input_op__oe__oe
-    connect \op__oe__oe_ok \input_op__oe__oe_ok
-    connect \op__invert_a \input_op__invert_a
-    connect \op__zero_a \input_op__zero_a
-    connect \op__invert_out \input_op__invert_out
-    connect \op__write_cr0 \input_op__write_cr0
-    connect \op__input_carry \input_op__input_carry
-    connect \op__output_carry \input_op__output_carry
-    connect \op__is_32bit \input_op__is_32bit
-    connect \op__is_signed \input_op__is_signed
-    connect \op__data_len \input_op__data_len
-    connect \op__insn \input_op__insn
+    connect \alu_op__insn_type \input_alu_op__insn_type
+    connect \alu_op__fn_unit \input_alu_op__fn_unit
+    connect \alu_op__imm_data__imm \input_alu_op__imm_data__imm
+    connect \alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm_ok
+    connect \alu_op__rc__rc \input_alu_op__rc__rc
+    connect \alu_op__rc__rc_ok \input_alu_op__rc__rc_ok
+    connect \alu_op__oe__oe \input_alu_op__oe__oe
+    connect \alu_op__oe__oe_ok \input_alu_op__oe__oe_ok
+    connect \alu_op__invert_a \input_alu_op__invert_a
+    connect \alu_op__zero_a \input_alu_op__zero_a
+    connect \alu_op__invert_out \input_alu_op__invert_out
+    connect \alu_op__write_cr0 \input_alu_op__write_cr0
+    connect \alu_op__input_carry \input_alu_op__input_carry
+    connect \alu_op__output_carry \input_alu_op__output_carry
+    connect \alu_op__is_32bit \input_alu_op__is_32bit
+    connect \alu_op__is_signed \input_alu_op__is_signed
+    connect \alu_op__data_len \input_alu_op__data_len
+    connect \alu_op__insn \input_alu_op__insn
     connect \ra \input_ra
     connect \rb \input_rb
     connect \xer_so \input_xer_so
     connect \xer_ca \input_xer_ca
     connect \muxid$1 \input_muxid$22
-    connect \op__insn_type$2 \input_op__insn_type$23
-    connect \op__fn_unit$3 \input_op__fn_unit$24
-    connect \op__imm_data__imm$4 \input_op__imm_data__imm$25
-    connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$26
-    connect \op__rc__rc$6 \input_op__rc__rc$27
-    connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$28
-    connect \op__oe__oe$8 \input_op__oe__oe$29
-    connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$30
-    connect \op__invert_a$10 \input_op__invert_a$31
-    connect \op__zero_a$11 \input_op__zero_a$32
-    connect \op__invert_out$12 \input_op__invert_out$33
-    connect \op__write_cr0$13 \input_op__write_cr0$34
-    connect \op__input_carry$14 \input_op__input_carry$35
-    connect \op__output_carry$15 \input_op__output_carry$36
-    connect \op__is_32bit$16 \input_op__is_32bit$37
-    connect \op__is_signed$17 \input_op__is_signed$38
-    connect \op__data_len$18 \input_op__data_len$39
-    connect \op__insn$19 \input_op__insn$40
+    connect \alu_op__insn_type$2 \input_alu_op__insn_type$23
+    connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24
+    connect \alu_op__imm_data__imm$4 \input_alu_op__imm_data__imm$25
+    connect \alu_op__imm_data__imm_ok$5 \input_alu_op__imm_data__imm_ok$26
+    connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27
+    connect \alu_op__rc__rc_ok$7 \input_alu_op__rc__rc_ok$28
+    connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29
+    connect \alu_op__oe__oe_ok$9 \input_alu_op__oe__oe_ok$30
+    connect \alu_op__invert_a$10 \input_alu_op__invert_a$31
+    connect \alu_op__zero_a$11 \input_alu_op__zero_a$32
+    connect \alu_op__invert_out$12 \input_alu_op__invert_out$33
+    connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34
+    connect \alu_op__input_carry$14 \input_alu_op__input_carry$35
+    connect \alu_op__output_carry$15 \input_alu_op__output_carry$36
+    connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37
+    connect \alu_op__is_signed$17 \input_alu_op__is_signed$38
+    connect \alu_op__data_len$18 \input_alu_op__data_len$39
+    connect \alu_op__insn$19 \input_alu_op__insn$40
     connect \ra$20 \input_ra$41
     connect \rb$21 \input_rb$42
     connect \xer_so$22 \input_xer_so$43
     connect \xer_ca$23 \input_xer_ca$44
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -46796,8 +46796,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -46810,53 +46810,53 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \main_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \main_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \main_alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \main_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \main_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid$45
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -46931,8 +46931,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_alu_op__insn_type$46
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -46945,105 +46945,105 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc_ok$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe_ok$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_a$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__zero_a$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_out$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__write_cr0$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_alu_op__fn_unit$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_alu_op__imm_data__imm$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__imm_data__imm_ok$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__rc__rc$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__rc__rc_ok$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__oe__oe$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__oe__oe_ok$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__invert_a$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__zero_a$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__invert_out$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__write_cr0$57
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \main_op__input_carry$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_carry$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_signed$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \main_op__data_len$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_alu_op__input_carry$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__output_carry$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__is_32bit$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_alu_op__is_signed$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \main_alu_op__data_len$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_alu_op__insn$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \main_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \main_xer_ca$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \main_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_xer_so$65
   cell \main \main
     connect \muxid \main_muxid
-    connect \op__insn_type \main_op__insn_type
-    connect \op__fn_unit \main_op__fn_unit
-    connect \op__imm_data__imm \main_op__imm_data__imm
-    connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
-    connect \op__rc__rc \main_op__rc__rc
-    connect \op__rc__rc_ok \main_op__rc__rc_ok
-    connect \op__oe__oe \main_op__oe__oe
-    connect \op__oe__oe_ok \main_op__oe__oe_ok
-    connect \op__invert_a \main_op__invert_a
-    connect \op__zero_a \main_op__zero_a
-    connect \op__invert_out \main_op__invert_out
-    connect \op__write_cr0 \main_op__write_cr0
-    connect \op__input_carry \main_op__input_carry
-    connect \op__output_carry \main_op__output_carry
-    connect \op__is_32bit \main_op__is_32bit
-    connect \op__is_signed \main_op__is_signed
-    connect \op__data_len \main_op__data_len
-    connect \op__insn \main_op__insn
+    connect \alu_op__insn_type \main_alu_op__insn_type
+    connect \alu_op__fn_unit \main_alu_op__fn_unit
+    connect \alu_op__imm_data__imm \main_alu_op__imm_data__imm
+    connect \alu_op__imm_data__imm_ok \main_alu_op__imm_data__imm_ok
+    connect \alu_op__rc__rc \main_alu_op__rc__rc
+    connect \alu_op__rc__rc_ok \main_alu_op__rc__rc_ok
+    connect \alu_op__oe__oe \main_alu_op__oe__oe
+    connect \alu_op__oe__oe_ok \main_alu_op__oe__oe_ok
+    connect \alu_op__invert_a \main_alu_op__invert_a
+    connect \alu_op__zero_a \main_alu_op__zero_a
+    connect \alu_op__invert_out \main_alu_op__invert_out
+    connect \alu_op__write_cr0 \main_alu_op__write_cr0
+    connect \alu_op__input_carry \main_alu_op__input_carry
+    connect \alu_op__output_carry \main_alu_op__output_carry
+    connect \alu_op__is_32bit \main_alu_op__is_32bit
+    connect \alu_op__is_signed \main_alu_op__is_signed
+    connect \alu_op__data_len \main_alu_op__data_len
+    connect \alu_op__insn \main_alu_op__insn
     connect \ra \main_ra
     connect \rb \main_rb
     connect \xer_so \main_xer_so
     connect \xer_ca \main_xer_ca
     connect \muxid$1 \main_muxid$45
-    connect \op__insn_type$2 \main_op__insn_type$46
-    connect \op__fn_unit$3 \main_op__fn_unit$47
-    connect \op__imm_data__imm$4 \main_op__imm_data__imm$48
-    connect \op__imm_data__imm_ok$5 \main_op__imm_data__imm_ok$49
-    connect \op__rc__rc$6 \main_op__rc__rc$50
-    connect \op__rc__rc_ok$7 \main_op__rc__rc_ok$51
-    connect \op__oe__oe$8 \main_op__oe__oe$52
-    connect \op__oe__oe_ok$9 \main_op__oe__oe_ok$53
-    connect \op__invert_a$10 \main_op__invert_a$54
-    connect \op__zero_a$11 \main_op__zero_a$55
-    connect \op__invert_out$12 \main_op__invert_out$56
-    connect \op__write_cr0$13 \main_op__write_cr0$57
-    connect \op__input_carry$14 \main_op__input_carry$58
-    connect \op__output_carry$15 \main_op__output_carry$59
-    connect \op__is_32bit$16 \main_op__is_32bit$60
-    connect \op__is_signed$17 \main_op__is_signed$61
-    connect \op__data_len$18 \main_op__data_len$62
-    connect \op__insn$19 \main_op__insn$63
+    connect \alu_op__insn_type$2 \main_alu_op__insn_type$46
+    connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47
+    connect \alu_op__imm_data__imm$4 \main_alu_op__imm_data__imm$48
+    connect \alu_op__imm_data__imm_ok$5 \main_alu_op__imm_data__imm_ok$49
+    connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50
+    connect \alu_op__rc__rc_ok$7 \main_alu_op__rc__rc_ok$51
+    connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52
+    connect \alu_op__oe__oe_ok$9 \main_alu_op__oe__oe_ok$53
+    connect \alu_op__invert_a$10 \main_alu_op__invert_a$54
+    connect \alu_op__zero_a$11 \main_alu_op__zero_a$55
+    connect \alu_op__invert_out$12 \main_alu_op__invert_out$56
+    connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57
+    connect \alu_op__input_carry$14 \main_alu_op__input_carry$58
+    connect \alu_op__output_carry$15 \main_alu_op__output_carry$59
+    connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60
+    connect \alu_op__is_signed$17 \main_alu_op__is_signed$61
+    connect \alu_op__data_len$18 \main_alu_op__data_len$62
+    connect \alu_op__insn$19 \main_alu_op__insn$63
     connect \o \main_o
     connect \o_ok \main_o_ok
     connect \cr_a \main_cr_a
@@ -47054,7 +47054,7 @@ module \pipe
     connect \xer_ov_ok \main_xer_ov_ok
     connect \xer_so$21 \main_xer_so$65
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -47129,8 +47129,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -47143,57 +47143,57 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \output_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \output_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid$66
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -47268,8 +47268,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_alu_op__insn_type$67
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -47282,84 +47282,84 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_a$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__zero_a$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_out$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__write_cr0$78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_alu_op__fn_unit$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_alu_op__imm_data__imm$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__imm_data__imm_ok$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__rc__rc$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__rc__rc_ok$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__oe__oe$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__oe__oe_ok$74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__invert_a$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__zero_a$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__invert_out$77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__write_cr0$78
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \output_op__input_carry$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_carry$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \output_op__data_len$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_alu_op__input_carry$79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__output_carry$80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__is_32bit$81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_alu_op__is_signed$82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_alu_op__data_len$83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_alu_op__insn$84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ca$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ov$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_so$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_so_ok
   cell \output \output
     connect \muxid \output_muxid
-    connect \op__insn_type \output_op__insn_type
-    connect \op__fn_unit \output_op__fn_unit
-    connect \op__imm_data__imm \output_op__imm_data__imm
-    connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
-    connect \op__rc__rc \output_op__rc__rc
-    connect \op__rc__rc_ok \output_op__rc__rc_ok
-    connect \op__oe__oe \output_op__oe__oe
-    connect \op__oe__oe_ok \output_op__oe__oe_ok
-    connect \op__invert_a \output_op__invert_a
-    connect \op__zero_a \output_op__zero_a
-    connect \op__invert_out \output_op__invert_out
-    connect \op__write_cr0 \output_op__write_cr0
-    connect \op__input_carry \output_op__input_carry
-    connect \op__output_carry \output_op__output_carry
-    connect \op__is_32bit \output_op__is_32bit
-    connect \op__is_signed \output_op__is_signed
-    connect \op__data_len \output_op__data_len
-    connect \op__insn \output_op__insn
+    connect \alu_op__insn_type \output_alu_op__insn_type
+    connect \alu_op__fn_unit \output_alu_op__fn_unit
+    connect \alu_op__imm_data__imm \output_alu_op__imm_data__imm
+    connect \alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm_ok
+    connect \alu_op__rc__rc \output_alu_op__rc__rc
+    connect \alu_op__rc__rc_ok \output_alu_op__rc__rc_ok
+    connect \alu_op__oe__oe \output_alu_op__oe__oe
+    connect \alu_op__oe__oe_ok \output_alu_op__oe__oe_ok
+    connect \alu_op__invert_a \output_alu_op__invert_a
+    connect \alu_op__zero_a \output_alu_op__zero_a
+    connect \alu_op__invert_out \output_alu_op__invert_out
+    connect \alu_op__write_cr0 \output_alu_op__write_cr0
+    connect \alu_op__input_carry \output_alu_op__input_carry
+    connect \alu_op__output_carry \output_alu_op__output_carry
+    connect \alu_op__is_32bit \output_alu_op__is_32bit
+    connect \alu_op__is_signed \output_alu_op__is_signed
+    connect \alu_op__data_len \output_alu_op__data_len
+    connect \alu_op__insn \output_alu_op__insn
     connect \o \output_o
     connect \o_ok \output_o_ok
     connect \cr_a \output_cr_a
@@ -47367,24 +47367,24 @@ module \pipe
     connect \xer_ov \output_xer_ov
     connect \xer_so \output_xer_so
     connect \muxid$1 \output_muxid$66
-    connect \op__insn_type$2 \output_op__insn_type$67
-    connect \op__fn_unit$3 \output_op__fn_unit$68
-    connect \op__imm_data__imm$4 \output_op__imm_data__imm$69
-    connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$70
-    connect \op__rc__rc$6 \output_op__rc__rc$71
-    connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$72
-    connect \op__oe__oe$8 \output_op__oe__oe$73
-    connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$74
-    connect \op__invert_a$10 \output_op__invert_a$75
-    connect \op__zero_a$11 \output_op__zero_a$76
-    connect \op__invert_out$12 \output_op__invert_out$77
-    connect \op__write_cr0$13 \output_op__write_cr0$78
-    connect \op__input_carry$14 \output_op__input_carry$79
-    connect \op__output_carry$15 \output_op__output_carry$80
-    connect \op__is_32bit$16 \output_op__is_32bit$81
-    connect \op__is_signed$17 \output_op__is_signed$82
-    connect \op__data_len$18 \output_op__data_len$83
-    connect \op__insn$19 \output_op__insn$84
+    connect \alu_op__insn_type$2 \output_alu_op__insn_type$67
+    connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$68
+    connect \alu_op__imm_data__imm$4 \output_alu_op__imm_data__imm$69
+    connect \alu_op__imm_data__imm_ok$5 \output_alu_op__imm_data__imm_ok$70
+    connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$71
+    connect \alu_op__rc__rc_ok$7 \output_alu_op__rc__rc_ok$72
+    connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$73
+    connect \alu_op__oe__oe_ok$9 \output_alu_op__oe__oe_ok$74
+    connect \alu_op__invert_a$10 \output_alu_op__invert_a$75
+    connect \alu_op__zero_a$11 \output_alu_op__zero_a$76
+    connect \alu_op__invert_out$12 \output_alu_op__invert_out$77
+    connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$78
+    connect \alu_op__input_carry$14 \output_alu_op__input_carry$79
+    connect \alu_op__output_carry$15 \output_alu_op__output_carry$80
+    connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$81
+    connect \alu_op__is_signed$17 \output_alu_op__is_signed$82
+    connect \alu_op__data_len$18 \output_alu_op__data_len$83
+    connect \alu_op__insn$19 \output_alu_op__insn$84
     connect \o$20 \output_o$85
     connect \o_ok$21 \output_o_ok$86
     connect \cr_a$22 \output_cr_a$87
@@ -47402,25 +47402,25 @@ module \pipe
     sync init
   end
   process $group_1
-    assign \input_op__insn_type 7'0000000
-    assign \input_op__fn_unit 11'00000000000
-    assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_op__imm_data__imm_ok 1'0
-    assign \input_op__rc__rc 1'0
-    assign \input_op__rc__rc_ok 1'0
-    assign \input_op__oe__oe 1'0
-    assign \input_op__oe__oe_ok 1'0
-    assign \input_op__invert_a 1'0
-    assign \input_op__zero_a 1'0
-    assign \input_op__invert_out 1'0
-    assign \input_op__write_cr0 1'0
-    assign \input_op__input_carry 2'00
-    assign \input_op__output_carry 1'0
-    assign \input_op__is_32bit 1'0
-    assign \input_op__is_signed 1'0
-    assign \input_op__data_len 4'0000
-    assign \input_op__insn 32'00000000000000000000000000000000
-    assign { \input_op__insn \input_op__data_len \input_op__is_signed \input_op__is_32bit \input_op__output_carry \input_op__input_carry \input_op__write_cr0 \input_op__invert_out \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \input_alu_op__insn_type 7'0000000
+    assign \input_alu_op__fn_unit 11'00000000000
+    assign \input_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_alu_op__imm_data__imm_ok 1'0
+    assign \input_alu_op__rc__rc 1'0
+    assign \input_alu_op__rc__rc_ok 1'0
+    assign \input_alu_op__oe__oe 1'0
+    assign \input_alu_op__oe__oe_ok 1'0
+    assign \input_alu_op__invert_a 1'0
+    assign \input_alu_op__zero_a 1'0
+    assign \input_alu_op__invert_out 1'0
+    assign \input_alu_op__write_cr0 1'0
+    assign \input_alu_op__input_carry 2'00
+    assign \input_alu_op__output_carry 1'0
+    assign \input_alu_op__is_32bit 1'0
+    assign \input_alu_op__is_signed 1'0
+    assign \input_alu_op__data_len 4'0000
+    assign \input_alu_op__insn 32'00000000000000000000000000000000
+    assign { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_a { \input_alu_op__oe__oe_ok \input_alu_op__oe__oe } { \input_alu_op__rc__rc_ok \input_alu_op__rc__rc } { \input_alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm } \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type }
     sync init
   end
   process $group_19
@@ -47449,25 +47449,25 @@ module \pipe
     sync init
   end
   process $group_24
-    assign \main_op__insn_type 7'0000000
-    assign \main_op__fn_unit 11'00000000000
-    assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_op__imm_data__imm_ok 1'0
-    assign \main_op__rc__rc 1'0
-    assign \main_op__rc__rc_ok 1'0
-    assign \main_op__oe__oe 1'0
-    assign \main_op__oe__oe_ok 1'0
-    assign \main_op__invert_a 1'0
-    assign \main_op__zero_a 1'0
-    assign \main_op__invert_out 1'0
-    assign \main_op__write_cr0 1'0
-    assign \main_op__input_carry 2'00
-    assign \main_op__output_carry 1'0
-    assign \main_op__is_32bit 1'0
-    assign \main_op__is_signed 1'0
-    assign \main_op__data_len 4'0000
-    assign \main_op__insn 32'00000000000000000000000000000000
-    assign { \main_op__insn \main_op__data_len \main_op__is_signed \main_op__is_32bit \main_op__output_carry \main_op__input_carry \main_op__write_cr0 \main_op__invert_out \main_op__zero_a \main_op__invert_a { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$40 \input_op__data_len$39 \input_op__is_signed$38 \input_op__is_32bit$37 \input_op__output_carry$36 \input_op__input_carry$35 \input_op__write_cr0$34 \input_op__invert_out$33 \input_op__zero_a$32 \input_op__invert_a$31 { \input_op__oe__oe_ok$30 \input_op__oe__oe$29 } { \input_op__rc__rc_ok$28 \input_op__rc__rc$27 } { \input_op__imm_data__imm_ok$26 \input_op__imm_data__imm$25 } \input_op__fn_unit$24 \input_op__insn_type$23 }
+    assign \main_alu_op__insn_type 7'0000000
+    assign \main_alu_op__fn_unit 11'00000000000
+    assign \main_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_alu_op__imm_data__imm_ok 1'0
+    assign \main_alu_op__rc__rc 1'0
+    assign \main_alu_op__rc__rc_ok 1'0
+    assign \main_alu_op__oe__oe 1'0
+    assign \main_alu_op__oe__oe_ok 1'0
+    assign \main_alu_op__invert_a 1'0
+    assign \main_alu_op__zero_a 1'0
+    assign \main_alu_op__invert_out 1'0
+    assign \main_alu_op__write_cr0 1'0
+    assign \main_alu_op__input_carry 2'00
+    assign \main_alu_op__output_carry 1'0
+    assign \main_alu_op__is_32bit 1'0
+    assign \main_alu_op__is_signed 1'0
+    assign \main_alu_op__data_len 4'0000
+    assign \main_alu_op__insn 32'00000000000000000000000000000000
+    assign { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_a { \main_alu_op__oe__oe_ok \main_alu_op__oe__oe } { \main_alu_op__rc__rc_ok \main_alu_op__rc__rc } { \main_alu_op__imm_data__imm_ok \main_alu_op__imm_data__imm } \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_a$31 { \input_alu_op__oe__oe_ok$30 \input_alu_op__oe__oe$29 } { \input_alu_op__rc__rc_ok$28 \input_alu_op__rc__rc$27 } { \input_alu_op__imm_data__imm_ok$26 \input_alu_op__imm_data__imm$25 } \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 }
     sync init
   end
   process $group_42
@@ -47496,25 +47496,25 @@ module \pipe
     sync init
   end
   process $group_47
-    assign \output_op__insn_type 7'0000000
-    assign \output_op__fn_unit 11'00000000000
-    assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_op__imm_data__imm_ok 1'0
-    assign \output_op__rc__rc 1'0
-    assign \output_op__rc__rc_ok 1'0
-    assign \output_op__oe__oe 1'0
-    assign \output_op__oe__oe_ok 1'0
-    assign \output_op__invert_a 1'0
-    assign \output_op__zero_a 1'0
-    assign \output_op__invert_out 1'0
-    assign \output_op__write_cr0 1'0
-    assign \output_op__input_carry 2'00
-    assign \output_op__output_carry 1'0
-    assign \output_op__is_32bit 1'0
-    assign \output_op__is_signed 1'0
-    assign \output_op__data_len 4'0000
-    assign \output_op__insn 32'00000000000000000000000000000000
-    assign { \output_op__insn \output_op__data_len \output_op__is_signed \output_op__is_32bit \output_op__output_carry \output_op__input_carry \output_op__write_cr0 \output_op__invert_out \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$63 \main_op__data_len$62 \main_op__is_signed$61 \main_op__is_32bit$60 \main_op__output_carry$59 \main_op__input_carry$58 \main_op__write_cr0$57 \main_op__invert_out$56 \main_op__zero_a$55 \main_op__invert_a$54 { \main_op__oe__oe_ok$53 \main_op__oe__oe$52 } { \main_op__rc__rc_ok$51 \main_op__rc__rc$50 } { \main_op__imm_data__imm_ok$49 \main_op__imm_data__imm$48 } \main_op__fn_unit$47 \main_op__insn_type$46 }
+    assign \output_alu_op__insn_type 7'0000000
+    assign \output_alu_op__fn_unit 11'00000000000
+    assign \output_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_alu_op__imm_data__imm_ok 1'0
+    assign \output_alu_op__rc__rc 1'0
+    assign \output_alu_op__rc__rc_ok 1'0
+    assign \output_alu_op__oe__oe 1'0
+    assign \output_alu_op__oe__oe_ok 1'0
+    assign \output_alu_op__invert_a 1'0
+    assign \output_alu_op__zero_a 1'0
+    assign \output_alu_op__invert_out 1'0
+    assign \output_alu_op__write_cr0 1'0
+    assign \output_alu_op__input_carry 2'00
+    assign \output_alu_op__output_carry 1'0
+    assign \output_alu_op__is_32bit 1'0
+    assign \output_alu_op__is_signed 1'0
+    assign \output_alu_op__data_len 4'0000
+    assign \output_alu_op__insn 32'00000000000000000000000000000000
+    assign { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_a { \output_alu_op__oe__oe_ok \output_alu_op__oe__oe } { \output_alu_op__rc__rc_ok \output_alu_op__rc__rc } { \output_alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm } \output_alu_op__fn_unit \output_alu_op__insn_type } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_a$54 { \main_alu_op__oe__oe_ok$53 \main_alu_op__oe__oe$52 } { \main_alu_op__rc__rc_ok$51 \main_alu_op__rc__rc$50 } { \main_alu_op__imm_data__imm_ok$49 \main_alu_op__imm_data__imm$48 } \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 }
     sync init
   end
   process $group_65
@@ -47523,7 +47523,7 @@ module \pipe
     assign { \output_o_ok \output_o } { \main_o_ok \main_o }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$91
   process $group_67
     assign \output_cr_a 4'0000
@@ -47531,7 +47531,7 @@ module \pipe
     assign { \cr_a_ok$91 \output_cr_a } { \main_cr_a_ok \main_cr_a }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$92
   process $group_69
     assign \output_xer_ca 2'00
@@ -47539,7 +47539,7 @@ module \pipe
     assign { \xer_ca_ok$92 \output_xer_ca } { \main_xer_ca_ok \main_xer_ca$64 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$93
   process $group_71
     assign \output_xer_ov 2'00
@@ -47547,9 +47547,9 @@ module \pipe
     assign { \xer_ov_ok$93 \output_xer_ov } { \main_xer_ov_ok \main_xer_ov }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$95
   process $group_73
     assign \output_xer_so 1'0
@@ -47591,7 +47591,7 @@ module \pipe
     assign \p_valid_i_p_ready_o $97
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$99
   process $group_78
     assign \muxid$99 2'00
@@ -47671,8 +47671,8 @@ module \pipe
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$100
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_op__insn_type$100
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -47685,69 +47685,69 @@ module \pipe
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$111
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_op__fn_unit$101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_op__imm_data__imm$102
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__imm_data__imm_ok$103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__rc__rc$104
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__rc__rc_ok$105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__oe__oe$106
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__oe__oe_ok$107
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__invert_a$108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__zero_a$109
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__invert_out$110
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__write_cr0$111
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \op__data_len$116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$117
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \alu_op__input_carry$112
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__output_carry$113
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__is_32bit$114
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__is_signed$115
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \alu_op__data_len$116
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_op__insn$117
   process $group_79
-    assign \op__insn_type$100 7'0000000
-    assign \op__fn_unit$101 11'00000000000
-    assign \op__imm_data__imm$102 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$103 1'0
-    assign \op__rc__rc$104 1'0
-    assign \op__rc__rc_ok$105 1'0
-    assign \op__oe__oe$106 1'0
-    assign \op__oe__oe_ok$107 1'0
-    assign \op__invert_a$108 1'0
-    assign \op__zero_a$109 1'0
-    assign \op__invert_out$110 1'0
-    assign \op__write_cr0$111 1'0
-    assign \op__input_carry$112 2'00
-    assign \op__output_carry$113 1'0
-    assign \op__is_32bit$114 1'0
-    assign \op__is_signed$115 1'0
-    assign \op__data_len$116 4'0000
-    assign \op__insn$117 32'00000000000000000000000000000000
-    assign { \op__insn$117 \op__data_len$116 \op__is_signed$115 \op__is_32bit$114 \op__output_carry$113 \op__input_carry$112 \op__write_cr0$111 \op__invert_out$110 \op__zero_a$109 \op__invert_a$108 { \op__oe__oe_ok$107 \op__oe__oe$106 } { \op__rc__rc_ok$105 \op__rc__rc$104 } { \op__imm_data__imm_ok$103 \op__imm_data__imm$102 } \op__fn_unit$101 \op__insn_type$100 } { \output_op__insn$84 \output_op__data_len$83 \output_op__is_signed$82 \output_op__is_32bit$81 \output_op__output_carry$80 \output_op__input_carry$79 \output_op__write_cr0$78 \output_op__invert_out$77 \output_op__zero_a$76 \output_op__invert_a$75 { \output_op__oe__oe_ok$74 \output_op__oe__oe$73 } { \output_op__rc__rc_ok$72 \output_op__rc__rc$71 } { \output_op__imm_data__imm_ok$70 \output_op__imm_data__imm$69 } \output_op__fn_unit$68 \output_op__insn_type$67 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+    assign \alu_op__insn_type$100 7'0000000
+    assign \alu_op__fn_unit$101 11'00000000000
+    assign \alu_op__imm_data__imm$102 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_op__imm_data__imm_ok$103 1'0
+    assign \alu_op__rc__rc$104 1'0
+    assign \alu_op__rc__rc_ok$105 1'0
+    assign \alu_op__oe__oe$106 1'0
+    assign \alu_op__oe__oe_ok$107 1'0
+    assign \alu_op__invert_a$108 1'0
+    assign \alu_op__zero_a$109 1'0
+    assign \alu_op__invert_out$110 1'0
+    assign \alu_op__write_cr0$111 1'0
+    assign \alu_op__input_carry$112 2'00
+    assign \alu_op__output_carry$113 1'0
+    assign \alu_op__is_32bit$114 1'0
+    assign \alu_op__is_signed$115 1'0
+    assign \alu_op__data_len$116 4'0000
+    assign \alu_op__insn$117 32'00000000000000000000000000000000
+    assign { \alu_op__insn$117 \alu_op__data_len$116 \alu_op__is_signed$115 \alu_op__is_32bit$114 \alu_op__output_carry$113 \alu_op__input_carry$112 \alu_op__write_cr0$111 \alu_op__invert_out$110 \alu_op__zero_a$109 \alu_op__invert_a$108 { \alu_op__oe__oe_ok$107 \alu_op__oe__oe$106 } { \alu_op__rc__rc_ok$105 \alu_op__rc__rc$104 } { \alu_op__imm_data__imm_ok$103 \alu_op__imm_data__imm$102 } \alu_op__fn_unit$101 \alu_op__insn_type$100 } { \output_alu_op__insn$84 \output_alu_op__data_len$83 \output_alu_op__is_signed$82 \output_alu_op__is_32bit$81 \output_alu_op__output_carry$80 \output_alu_op__input_carry$79 \output_alu_op__write_cr0$78 \output_alu_op__invert_out$77 \output_alu_op__zero_a$76 \output_alu_op__invert_a$75 { \output_alu_op__oe__oe_ok$74 \output_alu_op__oe__oe$73 } { \output_alu_op__rc__rc_ok$72 \output_alu_op__rc__rc$71 } { \output_alu_op__imm_data__imm_ok$70 \output_alu_op__imm_data__imm$69 } \output_alu_op__fn_unit$68 \output_alu_op__insn_type$67 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$119
   process $group_97
     assign \o$118 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -47755,9 +47755,9 @@ module \pipe
     assign { \o_ok$119 \o$118 } { \output_o_ok$86 \output_o$85 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$121
   process $group_99
     assign \cr_a$120 4'0000
@@ -47765,9 +47765,9 @@ module \pipe
     assign { \cr_a_ok$121 \cr_a$120 } { \output_cr_a_ok \output_cr_a$87 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$123
   process $group_101
     assign \xer_ca$122 2'00
@@ -47775,9 +47775,9 @@ module \pipe
     assign { \xer_ca_ok$123 \xer_ca$122 } { \output_xer_ca_ok \output_xer_ca$88 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ov$124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$125
   process $group_103
     assign \xer_ov$124 2'00
@@ -47785,9 +47785,9 @@ module \pipe
     assign { \xer_ov_ok$125 \xer_ov$124 } { \output_xer_ov_ok \output_xer_ov$89 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so$126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$127
   process $group_105
     assign \xer_so$126 1'0
@@ -47837,81 +47837,81 @@ module \pipe
       update \muxid$1 \muxid$1$next
   end
   process $group_109
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__imm_data__imm$4$next \op__imm_data__imm$4
-    assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
-    assign \op__rc__rc$6$next \op__rc__rc$6
-    assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
-    assign \op__oe__oe$8$next \op__oe__oe$8
-    assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
-    assign \op__invert_a$10$next \op__invert_a$10
-    assign \op__zero_a$11$next \op__zero_a$11
-    assign \op__invert_out$12$next \op__invert_out$12
-    assign \op__write_cr0$13$next \op__write_cr0$13
-    assign \op__input_carry$14$next \op__input_carry$14
-    assign \op__output_carry$15$next \op__output_carry$15
-    assign \op__is_32bit$16$next \op__is_32bit$16
-    assign \op__is_signed$17$next \op__is_signed$17
-    assign \op__data_len$18$next \op__data_len$18
-    assign \op__insn$19$next \op__insn$19
+    assign \alu_op__insn_type$2$next \alu_op__insn_type$2
+    assign \alu_op__fn_unit$3$next \alu_op__fn_unit$3
+    assign \alu_op__imm_data__imm$4$next \alu_op__imm_data__imm$4
+    assign \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm_ok$5
+    assign \alu_op__rc__rc$6$next \alu_op__rc__rc$6
+    assign \alu_op__rc__rc_ok$7$next \alu_op__rc__rc_ok$7
+    assign \alu_op__oe__oe$8$next \alu_op__oe__oe$8
+    assign \alu_op__oe__oe_ok$9$next \alu_op__oe__oe_ok$9
+    assign \alu_op__invert_a$10$next \alu_op__invert_a$10
+    assign \alu_op__zero_a$11$next \alu_op__zero_a$11
+    assign \alu_op__invert_out$12$next \alu_op__invert_out$12
+    assign \alu_op__write_cr0$13$next \alu_op__write_cr0$13
+    assign \alu_op__input_carry$14$next \alu_op__input_carry$14
+    assign \alu_op__output_carry$15$next \alu_op__output_carry$15
+    assign \alu_op__is_32bit$16$next \alu_op__is_32bit$16
+    assign \alu_op__is_signed$17$next \alu_op__is_signed$17
+    assign \alu_op__data_len$18$next \alu_op__data_len$18
+    assign \alu_op__insn$19$next \alu_op__insn$19
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__input_carry$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$117 \op__data_len$116 \op__is_signed$115 \op__is_32bit$114 \op__output_carry$113 \op__input_carry$112 \op__write_cr0$111 \op__invert_out$110 \op__zero_a$109 \op__invert_a$108 { \op__oe__oe_ok$107 \op__oe__oe$106 } { \op__rc__rc_ok$105 \op__rc__rc$104 } { \op__imm_data__imm_ok$103 \op__imm_data__imm$102 } \op__fn_unit$101 \op__insn_type$100 }
+        assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_a$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$117 \alu_op__data_len$116 \alu_op__is_signed$115 \alu_op__is_32bit$114 \alu_op__output_carry$113 \alu_op__input_carry$112 \alu_op__write_cr0$111 \alu_op__invert_out$110 \alu_op__zero_a$109 \alu_op__invert_a$108 { \alu_op__oe__oe_ok$107 \alu_op__oe__oe$106 } { \alu_op__rc__rc_ok$105 \alu_op__rc__rc$104 } { \alu_op__imm_data__imm_ok$103 \alu_op__imm_data__imm$102 } \alu_op__fn_unit$101 \alu_op__insn_type$100 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__input_carry$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$117 \op__data_len$116 \op__is_signed$115 \op__is_32bit$114 \op__output_carry$113 \op__input_carry$112 \op__write_cr0$111 \op__invert_out$110 \op__zero_a$109 \op__invert_a$108 { \op__oe__oe_ok$107 \op__oe__oe$106 } { \op__rc__rc_ok$105 \op__rc__rc$104 } { \op__imm_data__imm_ok$103 \op__imm_data__imm$102 } \op__fn_unit$101 \op__insn_type$100 }
+        assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_a$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$117 \alu_op__data_len$116 \alu_op__is_signed$115 \alu_op__is_32bit$114 \alu_op__output_carry$113 \alu_op__input_carry$112 \alu_op__write_cr0$111 \alu_op__invert_out$110 \alu_op__zero_a$109 \alu_op__invert_a$108 { \alu_op__oe__oe_ok$107 \alu_op__oe__oe$106 } { \alu_op__rc__rc_ok$105 \alu_op__rc__rc$104 } { \alu_op__imm_data__imm_ok$103 \alu_op__imm_data__imm$102 } \alu_op__fn_unit$101 \alu_op__insn_type$100 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \op__imm_data__imm_ok$5$next 1'0
-        assign \op__rc__rc$6$next 1'0
-        assign \op__rc__rc_ok$7$next 1'0
-        assign \op__oe__oe$8$next 1'0
-        assign \op__oe__oe_ok$9$next 1'0
-    end
-    sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__imm_data__imm_ok$5 1'0
-      update \op__rc__rc$6 1'0
-      update \op__rc__rc_ok$7 1'0
-      update \op__oe__oe$8 1'0
-      update \op__oe__oe_ok$9 1'0
-      update \op__invert_a$10 1'0
-      update \op__zero_a$11 1'0
-      update \op__invert_out$12 1'0
-      update \op__write_cr0$13 1'0
-      update \op__input_carry$14 2'00
-      update \op__output_carry$15 1'0
-      update \op__is_32bit$16 1'0
-      update \op__is_signed$17 1'0
-      update \op__data_len$18 4'0000
-      update \op__insn$19 32'00000000000000000000000000000000
+        assign \alu_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \alu_op__imm_data__imm_ok$5$next 1'0
+        assign \alu_op__rc__rc$6$next 1'0
+        assign \alu_op__rc__rc_ok$7$next 1'0
+        assign \alu_op__oe__oe$8$next 1'0
+        assign \alu_op__oe__oe_ok$9$next 1'0
+    end
+    sync init
+      update \alu_op__insn_type$2 7'0000000
+      update \alu_op__fn_unit$3 11'00000000000
+      update \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \alu_op__imm_data__imm_ok$5 1'0
+      update \alu_op__rc__rc$6 1'0
+      update \alu_op__rc__rc_ok$7 1'0
+      update \alu_op__oe__oe$8 1'0
+      update \alu_op__oe__oe_ok$9 1'0
+      update \alu_op__invert_a$10 1'0
+      update \alu_op__zero_a$11 1'0
+      update \alu_op__invert_out$12 1'0
+      update \alu_op__write_cr0$13 1'0
+      update \alu_op__input_carry$14 2'00
+      update \alu_op__output_carry$15 1'0
+      update \alu_op__is_32bit$16 1'0
+      update \alu_op__is_signed$17 1'0
+      update \alu_op__data_len$18 4'0000
+      update \alu_op__insn$19 32'00000000000000000000000000000000
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__imm_data__imm$4 \op__imm_data__imm$4$next
-      update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
-      update \op__rc__rc$6 \op__rc__rc$6$next
-      update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
-      update \op__oe__oe$8 \op__oe__oe$8$next
-      update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
-      update \op__invert_a$10 \op__invert_a$10$next
-      update \op__zero_a$11 \op__zero_a$11$next
-      update \op__invert_out$12 \op__invert_out$12$next
-      update \op__write_cr0$13 \op__write_cr0$13$next
-      update \op__input_carry$14 \op__input_carry$14$next
-      update \op__output_carry$15 \op__output_carry$15$next
-      update \op__is_32bit$16 \op__is_32bit$16$next
-      update \op__is_signed$17 \op__is_signed$17$next
-      update \op__data_len$18 \op__data_len$18$next
-      update \op__insn$19 \op__insn$19$next
+      update \alu_op__insn_type$2 \alu_op__insn_type$2$next
+      update \alu_op__fn_unit$3 \alu_op__fn_unit$3$next
+      update \alu_op__imm_data__imm$4 \alu_op__imm_data__imm$4$next
+      update \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm_ok$5$next
+      update \alu_op__rc__rc$6 \alu_op__rc__rc$6$next
+      update \alu_op__rc__rc_ok$7 \alu_op__rc__rc_ok$7$next
+      update \alu_op__oe__oe$8 \alu_op__oe__oe$8$next
+      update \alu_op__oe__oe_ok$9 \alu_op__oe__oe_ok$9$next
+      update \alu_op__invert_a$10 \alu_op__invert_a$10$next
+      update \alu_op__zero_a$11 \alu_op__zero_a$11$next
+      update \alu_op__invert_out$12 \alu_op__invert_out$12$next
+      update \alu_op__write_cr0$13 \alu_op__write_cr0$13$next
+      update \alu_op__input_carry$14 \alu_op__input_carry$14$next
+      update \alu_op__output_carry$15 \alu_op__output_carry$15$next
+      update \alu_op__is_32bit$16 \alu_op__is_32bit$16$next
+      update \alu_op__is_signed$17 \alu_op__is_signed$17$next
+      update \alu_op__data_len$18 \alu_op__data_len$18$next
+      update \alu_op__insn$19 \alu_op__insn$19$next
   end
   process $group_127
     assign \o$next \o
@@ -48052,29 +48052,29 @@ module \alu_alu0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 6 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 7 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 8 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 9 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 10 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 11 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 12 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 13 \xer_so
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -48149,8 +48149,8 @@ module \alu_alu0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 14 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 14 \alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -48163,51 +48163,51 @@ module \alu_alu0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 15 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 16 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 20 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 21 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 22 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 23 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 24 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 25 \op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 15 \alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 16 \alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 21 \alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 22 \alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 23 \alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 24 \alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 25 \alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 26 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 27 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 28 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 29 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 30 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 31 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 26 \alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 27 \alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 28 \alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 29 \alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 30 \alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 31 \alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 32 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 33 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 34 \xer_so$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 35 \xer_ca$2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 36 \p_valid_i
@@ -48225,7 +48225,7 @@ module \alu_alu0
   wire width 1 \pipe_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -48300,8 +48300,8 @@ module \alu_alu0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -48314,57 +48314,57 @@ module \alu_alu0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \pipe_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \pipe_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \pipe_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \pipe_xer_ca
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \pipe_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \pipe_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid$3
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -48439,8 +48439,8 @@ module \alu_alu0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_alu_op__insn_type$4
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -48453,63 +48453,63 @@ module \alu_alu0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe_ok$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_a$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__zero_a$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_out$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__write_cr0$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_alu_op__fn_unit$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_alu_op__imm_data__imm$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__imm_data__imm_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__rc__rc$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__rc__rc_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__oe__oe$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__oe__oe_ok$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__invert_a$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__zero_a$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__invert_out$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__write_cr0$15
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \pipe_op__input_carry$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_carry$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_signed$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \pipe_op__data_len$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_alu_op__input_carry$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__output_carry$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__is_32bit$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_alu_op__is_signed$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_alu_op__data_len$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_alu_op__insn$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \pipe_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \pipe_xer_ca$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \pipe_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_so$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_so_ok
   cell \pipe \pipe
     connect \rst \rst
@@ -48517,24 +48517,24 @@ module \alu_alu0
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
-    connect \op__insn_type \pipe_op__insn_type
-    connect \op__fn_unit \pipe_op__fn_unit
-    connect \op__imm_data__imm \pipe_op__imm_data__imm
-    connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
-    connect \op__rc__rc \pipe_op__rc__rc
-    connect \op__rc__rc_ok \pipe_op__rc__rc_ok
-    connect \op__oe__oe \pipe_op__oe__oe
-    connect \op__oe__oe_ok \pipe_op__oe__oe_ok
-    connect \op__invert_a \pipe_op__invert_a
-    connect \op__zero_a \pipe_op__zero_a
-    connect \op__invert_out \pipe_op__invert_out
-    connect \op__write_cr0 \pipe_op__write_cr0
-    connect \op__input_carry \pipe_op__input_carry
-    connect \op__output_carry \pipe_op__output_carry
-    connect \op__is_32bit \pipe_op__is_32bit
-    connect \op__is_signed \pipe_op__is_signed
-    connect \op__data_len \pipe_op__data_len
-    connect \op__insn \pipe_op__insn
+    connect \alu_op__insn_type \pipe_alu_op__insn_type
+    connect \alu_op__fn_unit \pipe_alu_op__fn_unit
+    connect \alu_op__imm_data__imm \pipe_alu_op__imm_data__imm
+    connect \alu_op__imm_data__imm_ok \pipe_alu_op__imm_data__imm_ok
+    connect \alu_op__rc__rc \pipe_alu_op__rc__rc
+    connect \alu_op__rc__rc_ok \pipe_alu_op__rc__rc_ok
+    connect \alu_op__oe__oe \pipe_alu_op__oe__oe
+    connect \alu_op__oe__oe_ok \pipe_alu_op__oe__oe_ok
+    connect \alu_op__invert_a \pipe_alu_op__invert_a
+    connect \alu_op__zero_a \pipe_alu_op__zero_a
+    connect \alu_op__invert_out \pipe_alu_op__invert_out
+    connect \alu_op__write_cr0 \pipe_alu_op__write_cr0
+    connect \alu_op__input_carry \pipe_alu_op__input_carry
+    connect \alu_op__output_carry \pipe_alu_op__output_carry
+    connect \alu_op__is_32bit \pipe_alu_op__is_32bit
+    connect \alu_op__is_signed \pipe_alu_op__is_signed
+    connect \alu_op__data_len \pipe_alu_op__data_len
+    connect \alu_op__insn \pipe_alu_op__insn
     connect \ra \pipe_ra
     connect \rb \pipe_rb
     connect \xer_so \pipe_xer_so
@@ -48542,24 +48542,24 @@ module \alu_alu0
     connect \n_valid_o \pipe_n_valid_o
     connect \n_ready_i \pipe_n_ready_i
     connect \muxid$1 \pipe_muxid$3
-    connect \op__insn_type$2 \pipe_op__insn_type$4
-    connect \op__fn_unit$3 \pipe_op__fn_unit$5
-    connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$6
-    connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$7
-    connect \op__rc__rc$6 \pipe_op__rc__rc$8
-    connect \op__rc__rc_ok$7 \pipe_op__rc__rc_ok$9
-    connect \op__oe__oe$8 \pipe_op__oe__oe$10
-    connect \op__oe__oe_ok$9 \pipe_op__oe__oe_ok$11
-    connect \op__invert_a$10 \pipe_op__invert_a$12
-    connect \op__zero_a$11 \pipe_op__zero_a$13
-    connect \op__invert_out$12 \pipe_op__invert_out$14
-    connect \op__write_cr0$13 \pipe_op__write_cr0$15
-    connect \op__input_carry$14 \pipe_op__input_carry$16
-    connect \op__output_carry$15 \pipe_op__output_carry$17
-    connect \op__is_32bit$16 \pipe_op__is_32bit$18
-    connect \op__is_signed$17 \pipe_op__is_signed$19
-    connect \op__data_len$18 \pipe_op__data_len$20
-    connect \op__insn$19 \pipe_op__insn$21
+    connect \alu_op__insn_type$2 \pipe_alu_op__insn_type$4
+    connect \alu_op__fn_unit$3 \pipe_alu_op__fn_unit$5
+    connect \alu_op__imm_data__imm$4 \pipe_alu_op__imm_data__imm$6
+    connect \alu_op__imm_data__imm_ok$5 \pipe_alu_op__imm_data__imm_ok$7
+    connect \alu_op__rc__rc$6 \pipe_alu_op__rc__rc$8
+    connect \alu_op__rc__rc_ok$7 \pipe_alu_op__rc__rc_ok$9
+    connect \alu_op__oe__oe$8 \pipe_alu_op__oe__oe$10
+    connect \alu_op__oe__oe_ok$9 \pipe_alu_op__oe__oe_ok$11
+    connect \alu_op__invert_a$10 \pipe_alu_op__invert_a$12
+    connect \alu_op__zero_a$11 \pipe_alu_op__zero_a$13
+    connect \alu_op__invert_out$12 \pipe_alu_op__invert_out$14
+    connect \alu_op__write_cr0$13 \pipe_alu_op__write_cr0$15
+    connect \alu_op__input_carry$14 \pipe_alu_op__input_carry$16
+    connect \alu_op__output_carry$15 \pipe_alu_op__output_carry$17
+    connect \alu_op__is_32bit$16 \pipe_alu_op__is_32bit$18
+    connect \alu_op__is_signed$17 \pipe_alu_op__is_signed$19
+    connect \alu_op__data_len$18 \pipe_alu_op__data_len$20
+    connect \alu_op__insn$19 \pipe_alu_op__insn$21
     connect \o \pipe_o
     connect \o_ok \pipe_o_ok
     connect \cr_a \pipe_cr_a
@@ -48581,7 +48581,7 @@ module \alu_alu0
     assign \p_ready_o \pipe_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_2
     assign \pipe_muxid 2'00
@@ -48589,25 +48589,25 @@ module \alu_alu0
     sync init
   end
   process $group_3
-    assign \pipe_op__insn_type 7'0000000
-    assign \pipe_op__fn_unit 11'00000000000
-    assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_op__imm_data__imm_ok 1'0
-    assign \pipe_op__rc__rc 1'0
-    assign \pipe_op__rc__rc_ok 1'0
-    assign \pipe_op__oe__oe 1'0
-    assign \pipe_op__oe__oe_ok 1'0
-    assign \pipe_op__invert_a 1'0
-    assign \pipe_op__zero_a 1'0
-    assign \pipe_op__invert_out 1'0
-    assign \pipe_op__write_cr0 1'0
-    assign \pipe_op__input_carry 2'00
-    assign \pipe_op__output_carry 1'0
-    assign \pipe_op__is_32bit 1'0
-    assign \pipe_op__is_signed 1'0
-    assign \pipe_op__data_len 4'0000
-    assign \pipe_op__insn 32'00000000000000000000000000000000
-    assign { \pipe_op__insn \pipe_op__data_len \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_carry \pipe_op__input_carry \pipe_op__write_cr0 \pipe_op__invert_out \pipe_op__zero_a \pipe_op__invert_a { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \pipe_alu_op__insn_type 7'0000000
+    assign \pipe_alu_op__fn_unit 11'00000000000
+    assign \pipe_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_alu_op__imm_data__imm_ok 1'0
+    assign \pipe_alu_op__rc__rc 1'0
+    assign \pipe_alu_op__rc__rc_ok 1'0
+    assign \pipe_alu_op__oe__oe 1'0
+    assign \pipe_alu_op__oe__oe_ok 1'0
+    assign \pipe_alu_op__invert_a 1'0
+    assign \pipe_alu_op__zero_a 1'0
+    assign \pipe_alu_op__invert_out 1'0
+    assign \pipe_alu_op__write_cr0 1'0
+    assign \pipe_alu_op__input_carry 2'00
+    assign \pipe_alu_op__output_carry 1'0
+    assign \pipe_alu_op__is_32bit 1'0
+    assign \pipe_alu_op__is_signed 1'0
+    assign \pipe_alu_op__data_len 4'0000
+    assign \pipe_alu_op__insn 32'00000000000000000000000000000000
+    assign { \pipe_alu_op__insn \pipe_alu_op__data_len \pipe_alu_op__is_signed \pipe_alu_op__is_32bit \pipe_alu_op__output_carry \pipe_alu_op__input_carry \pipe_alu_op__write_cr0 \pipe_alu_op__invert_out \pipe_alu_op__zero_a \pipe_alu_op__invert_a { \pipe_alu_op__oe__oe_ok \pipe_alu_op__oe__oe } { \pipe_alu_op__rc__rc_ok \pipe_alu_op__rc__rc } { \pipe_alu_op__imm_data__imm_ok \pipe_alu_op__imm_data__imm } \pipe_alu_op__fn_unit \pipe_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type }
     sync init
   end
   process $group_21
@@ -48640,7 +48640,7 @@ module \alu_alu0
     assign \pipe_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$24
   process $group_27
     assign \muxid$24 2'00
@@ -48720,8 +48720,8 @@ module \alu_alu0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_op__insn_type$25
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -48734,64 +48734,64 @@ module \alu_alu0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_op__fn_unit$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_op__imm_data__imm$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__imm_data__imm_ok$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__rc__rc$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__rc__rc_ok$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__oe__oe$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__oe__oe_ok$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__invert_a$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__zero_a$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__invert_out$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__write_cr0$36
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \op__data_len$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \alu_op__input_carry$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__output_carry$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__is_32bit$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_op__is_signed$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \alu_op__data_len$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_op__insn$42
   process $group_28
-    assign \op__insn_type$25 7'0000000
-    assign \op__fn_unit$26 11'00000000000
-    assign \op__imm_data__imm$27 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$28 1'0
-    assign \op__rc__rc$29 1'0
-    assign \op__rc__rc_ok$30 1'0
-    assign \op__oe__oe$31 1'0
-    assign \op__oe__oe_ok$32 1'0
-    assign \op__invert_a$33 1'0
-    assign \op__zero_a$34 1'0
-    assign \op__invert_out$35 1'0
-    assign \op__write_cr0$36 1'0
-    assign \op__input_carry$37 2'00
-    assign \op__output_carry$38 1'0
-    assign \op__is_32bit$39 1'0
-    assign \op__is_signed$40 1'0
-    assign \op__data_len$41 4'0000
-    assign \op__insn$42 32'00000000000000000000000000000000
-    assign { \op__insn$42 \op__data_len$41 \op__is_signed$40 \op__is_32bit$39 \op__output_carry$38 \op__input_carry$37 \op__write_cr0$36 \op__invert_out$35 \op__zero_a$34 \op__invert_a$33 { \op__oe__oe_ok$32 \op__oe__oe$31 } { \op__rc__rc_ok$30 \op__rc__rc$29 } { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 } { \pipe_op__insn$21 \pipe_op__data_len$20 \pipe_op__is_signed$19 \pipe_op__is_32bit$18 \pipe_op__output_carry$17 \pipe_op__input_carry$16 \pipe_op__write_cr0$15 \pipe_op__invert_out$14 \pipe_op__zero_a$13 \pipe_op__invert_a$12 { \pipe_op__oe__oe_ok$11 \pipe_op__oe__oe$10 } { \pipe_op__rc__rc_ok$9 \pipe_op__rc__rc$8 } { \pipe_op__imm_data__imm_ok$7 \pipe_op__imm_data__imm$6 } \pipe_op__fn_unit$5 \pipe_op__insn_type$4 }
+    assign \alu_op__insn_type$25 7'0000000
+    assign \alu_op__fn_unit$26 11'00000000000
+    assign \alu_op__imm_data__imm$27 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_op__imm_data__imm_ok$28 1'0
+    assign \alu_op__rc__rc$29 1'0
+    assign \alu_op__rc__rc_ok$30 1'0
+    assign \alu_op__oe__oe$31 1'0
+    assign \alu_op__oe__oe_ok$32 1'0
+    assign \alu_op__invert_a$33 1'0
+    assign \alu_op__zero_a$34 1'0
+    assign \alu_op__invert_out$35 1'0
+    assign \alu_op__write_cr0$36 1'0
+    assign \alu_op__input_carry$37 2'00
+    assign \alu_op__output_carry$38 1'0
+    assign \alu_op__is_32bit$39 1'0
+    assign \alu_op__is_signed$40 1'0
+    assign \alu_op__data_len$41 4'0000
+    assign \alu_op__insn$42 32'00000000000000000000000000000000
+    assign { \alu_op__insn$42 \alu_op__data_len$41 \alu_op__is_signed$40 \alu_op__is_32bit$39 \alu_op__output_carry$38 \alu_op__input_carry$37 \alu_op__write_cr0$36 \alu_op__invert_out$35 \alu_op__zero_a$34 \alu_op__invert_a$33 { \alu_op__oe__oe_ok$32 \alu_op__oe__oe$31 } { \alu_op__rc__rc_ok$30 \alu_op__rc__rc$29 } { \alu_op__imm_data__imm_ok$28 \alu_op__imm_data__imm$27 } \alu_op__fn_unit$26 \alu_op__insn_type$25 } { \pipe_alu_op__insn$21 \pipe_alu_op__data_len$20 \pipe_alu_op__is_signed$19 \pipe_alu_op__is_32bit$18 \pipe_alu_op__output_carry$17 \pipe_alu_op__input_carry$16 \pipe_alu_op__write_cr0$15 \pipe_alu_op__invert_out$14 \pipe_alu_op__zero_a$13 \pipe_alu_op__invert_a$12 { \pipe_alu_op__oe__oe_ok$11 \pipe_alu_op__oe__oe$10 } { \pipe_alu_op__rc__rc_ok$9 \pipe_alu_op__rc__rc$8 } { \pipe_alu_op__imm_data__imm_ok$7 \pipe_alu_op__imm_data__imm$6 } \pipe_alu_op__fn_unit$5 \pipe_alu_op__insn_type$4 }
     sync init
   end
   process $group_46
@@ -49921,8 +49921,8 @@ module \alu0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \oper_i_alu_alu0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -49935,103 +49935,103 @@ module \alu0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 4 \oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \oper_i__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \oper_i__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \oper_i__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \oper_i__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \oper_i__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \oper_i__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \oper_i__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \oper_i__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \oper_i_alu_alu0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 4 \oper_i_alu_alu0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \oper_i_alu_alu0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \oper_i_alu_alu0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_alu_alu0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_alu_alu0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_alu_alu0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \oper_i_alu_alu0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_alu_alu0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_alu_alu0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_alu_alu0__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 14 \oper_i__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \oper_i__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \oper_i__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 18 \oper_i__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 19 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 20 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 14 \oper_i_alu_alu0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_alu_alu0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \oper_i_alu_alu0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \oper_i_alu_alu0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 18 \oper_i_alu_alu0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 19 \oper_i_alu_alu0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 21 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 input 22 \rdmaskn
+  wire width 1 input 20 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 21 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 22 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 23 \rd__rel
+  wire width 4 output 23 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 24 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 4 input 24 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 25 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 26 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 1 input 27 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 input 28 \src4_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 30 \wr__rel
+  wire width 5 output 30 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 input 31 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 5 input 31 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 32 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 output 34 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 35 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 36 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 37 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 38 \dest4_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 39 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 40 \dest5_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 41 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 42 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 41 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 42 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_alu0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_alu0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_alu0_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \alu_alu0_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \alu_alu0_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \alu_alu0_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \alu_alu0_xer_so
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -50106,8 +50106,8 @@ module \alu0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_alu0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_alu0_alu_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -50120,51 +50120,51 @@ module \alu0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_alu0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_alu0_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_alu0_alu_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_alu0_alu_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \alu_alu0_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_alu0_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \alu_alu0_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_alu0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \alu_alu0_alu_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_alu0_alu_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \alu_alu0_alu_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_alu0_alu_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_alu0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_alu0_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \alu_alu0_xer_so$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \alu_alu0_xer_ca$2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_alu0_p_valid_i
@@ -50185,24 +50185,24 @@ module \alu0
     connect \xer_ca \alu_alu0_xer_ca
     connect \xer_ov \alu_alu0_xer_ov
     connect \xer_so \alu_alu0_xer_so
-    connect \op__insn_type \alu_alu0_op__insn_type
-    connect \op__fn_unit \alu_alu0_op__fn_unit
-    connect \op__imm_data__imm \alu_alu0_op__imm_data__imm
-    connect \op__imm_data__imm_ok \alu_alu0_op__imm_data__imm_ok
-    connect \op__rc__rc \alu_alu0_op__rc__rc
-    connect \op__rc__rc_ok \alu_alu0_op__rc__rc_ok
-    connect \op__oe__oe \alu_alu0_op__oe__oe
-    connect \op__oe__oe_ok \alu_alu0_op__oe__oe_ok
-    connect \op__invert_a \alu_alu0_op__invert_a
-    connect \op__zero_a \alu_alu0_op__zero_a
-    connect \op__invert_out \alu_alu0_op__invert_out
-    connect \op__write_cr0 \alu_alu0_op__write_cr0
-    connect \op__input_carry \alu_alu0_op__input_carry
-    connect \op__output_carry \alu_alu0_op__output_carry
-    connect \op__is_32bit \alu_alu0_op__is_32bit
-    connect \op__is_signed \alu_alu0_op__is_signed
-    connect \op__data_len \alu_alu0_op__data_len
-    connect \op__insn \alu_alu0_op__insn
+    connect \alu_op__insn_type \alu_alu0_alu_op__insn_type
+    connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit
+    connect \alu_op__imm_data__imm \alu_alu0_alu_op__imm_data__imm
+    connect \alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm_ok
+    connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc
+    connect \alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc_ok
+    connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe
+    connect \alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe_ok
+    connect \alu_op__invert_a \alu_alu0_alu_op__invert_a
+    connect \alu_op__zero_a \alu_alu0_alu_op__zero_a
+    connect \alu_op__invert_out \alu_alu0_alu_op__invert_out
+    connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0
+    connect \alu_op__input_carry \alu_alu0_alu_op__input_carry
+    connect \alu_op__output_carry \alu_alu0_alu_op__output_carry
+    connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit
+    connect \alu_op__is_signed \alu_alu0_alu_op__is_signed
+    connect \alu_op__data_len \alu_alu0_alu_op__data_len
+    connect \alu_op__insn \alu_alu0_alu_op__insn
     connect \ra \alu_alu0_ra
     connect \rb \alu_alu0_rb
     connect \xer_so$1 \alu_alu0_xer_so$1
@@ -50312,36 +50312,36 @@ module \alu0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 4 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $6
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 4 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -50349,10 +50349,10 @@ module \alu0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A $6
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -50360,9 +50360,9 @@ module \alu0
     connect \A $8
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50378,9 +50378,9 @@ module \alu0
     assign \all_rd $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -50390,11 +50390,11 @@ module \alu0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50402,9 +50402,9 @@ module \alu0
     connect \A \all_rd_dly
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50420,16 +50420,16 @@ module \alu0
     assign \all_rd_pulse $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_alu0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -50439,11 +50439,11 @@ module \alu0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50451,9 +50451,9 @@ module \alu0
     connect \A \alu_done_dly
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50469,28 +50469,28 @@ module \alu0
     assign \alu_pulse $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 5 \alu_pulsem
   process $group_6
     assign \alu_pulsem 5'00000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 5 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 5 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 5 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $21
   end
   process $group_7
@@ -50506,38 +50506,38 @@ module \alu0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 5 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 5 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 5 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 5 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $25
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -50545,7 +50545,7 @@ module \alu0
     connect \A $27
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50553,39 +50553,39 @@ module \alu0
     connect \A $24
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $23
     connect \Y $31
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $31
+    assign \cu_done_o 1'0
+    assign \cu_done_o $31
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -50593,9 +50593,9 @@ module \alu0
     connect \A \prev_wr_go
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50611,11 +50611,11 @@ module \alu0
     assign \wr_any $37
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50623,9 +50623,9 @@ module \alu0
     connect \A \alu_alu0_n_ready_i
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50636,9 +50636,9 @@ module \alu0
     connect \B $39
     connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 5 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -50646,12 +50646,12 @@ module \alu0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -50662,9 +50662,9 @@ module \alu0
     connect \B 1'0
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50675,22 +50675,22 @@ module \alu0
     connect \B $45
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50701,9 +50701,9 @@ module \alu0
     connect \B \alu_alu0_n_ready_i
     connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50714,9 +50714,9 @@ module \alu0
     connect \B \alu_alu0_n_valid_o
     connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50724,25 +50724,25 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $53
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $55
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $47
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $55 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50750,7 +50750,7 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $57
   end
   process $group_11
@@ -50758,19 +50758,19 @@ module \alu0
     assign \reset $57
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $59
   end
   process $group_12
@@ -50778,19 +50778,19 @@ module \alu0
     assign \rst_r $59
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 5 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 5 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $61
   end
   process $group_13
@@ -50798,19 +50798,19 @@ module \alu0
     assign \reset_w $61
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 4 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 4 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $63
   end
   process $group_14
@@ -50820,12 +50820,12 @@ module \alu0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -50833,7 +50833,7 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_alu0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $65
   end
   process $group_16
@@ -50861,7 +50861,7 @@ module \alu0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -50887,7 +50887,7 @@ module \alu0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -50911,9 +50911,9 @@ module \alu0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 5 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -50921,7 +50921,7 @@ module \alu0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $67
   end
   process $group_23
@@ -50929,9 +50929,9 @@ module \alu0
     assign \req_l_s_req $67
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 5 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -51020,7 +51020,7 @@ module \alu0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -51034,43 +51034,43 @@ module \alu0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 2 \oper_r__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 4 \oper_r__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -51150,8 +51150,8 @@ module \alu0
   cell $mux $72
     parameter \WIDTH 132
     connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__input_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__input_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_a { \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type }
+    connect \S \cu_issue_i
     connect \Y $71
   end
   process $group_25
@@ -51196,10 +51196,10 @@ module \alu0
     assign \oper_l__data_len$next \oper_l__data_len
     assign \oper_l__insn$next \oper_l__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__input_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__input_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+        assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__input_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_a { \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -51250,9 +51250,9 @@ module \alu0
       update \oper_l__data_len \oper_l__data_len$next
       update \oper_l__insn \oper_l__insn$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__o_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__o
@@ -51319,9 +51319,9 @@ module \alu0
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 4 \data_r1__cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 4 \data_r1_l__cr_a
@@ -51388,9 +51388,9 @@ module \alu0
       update \data_r1_l__cr_a \data_r1_l__cr_a$next
       update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 2 \data_r2__xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \data_r2_l__xer_ca
@@ -51457,9 +51457,9 @@ module \alu0
       update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
       update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 2 \data_r3__xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r3__xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \data_r3_l__xer_ov
@@ -51526,9 +51526,9 @@ module \alu0
       update \data_r3_l__xer_ov \data_r3_l__xer_ov$next
       update \data_r3_l__xer_ov_ok \data_r3_l__xer_ov_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r4__xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r4__xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \data_r4_l__xer_so
@@ -51595,9 +51595,9 @@ module \alu0
       update \data_r4_l__xer_so \data_r4_l__xer_so$next
       update \data_r4_l__xer_so_ok \data_r4_l__xer_so_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51605,12 +51605,12 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__o_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $103
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51618,12 +51618,12 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__cr_a_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $105
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51631,12 +51631,12 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__xer_ca_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $107
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51644,12 +51644,12 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r3__xer_ov_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $109
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51657,41 +51657,41 @@ module \alu0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r4__xer_so_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $111
   end
   process $group_81
-    assign \wrmask 5'00000
-    assign \wrmask { $111 $109 $107 $105 $103 }
+    assign \cu_wrmask_o 5'00000
+    assign \cu_wrmask_o { $111 $109 $107 $105 $103 }
     sync init
   end
   process $group_82
-    assign \alu_alu0_op__insn_type 7'0000000
-    assign \alu_alu0_op__fn_unit 11'00000000000
-    assign \alu_alu0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_alu0_op__imm_data__imm_ok 1'0
-    assign \alu_alu0_op__rc__rc 1'0
-    assign \alu_alu0_op__rc__rc_ok 1'0
-    assign \alu_alu0_op__oe__oe 1'0
-    assign \alu_alu0_op__oe__oe_ok 1'0
-    assign \alu_alu0_op__invert_a 1'0
-    assign \alu_alu0_op__zero_a 1'0
-    assign \alu_alu0_op__invert_out 1'0
-    assign \alu_alu0_op__write_cr0 1'0
-    assign \alu_alu0_op__input_carry 2'00
-    assign \alu_alu0_op__output_carry 1'0
-    assign \alu_alu0_op__is_32bit 1'0
-    assign \alu_alu0_op__is_signed 1'0
-    assign \alu_alu0_op__data_len 4'0000
-    assign \alu_alu0_op__insn 32'00000000000000000000000000000000
-    assign { \alu_alu0_op__insn \alu_alu0_op__data_len \alu_alu0_op__is_signed \alu_alu0_op__is_32bit \alu_alu0_op__output_carry \alu_alu0_op__input_carry \alu_alu0_op__write_cr0 \alu_alu0_op__invert_out \alu_alu0_op__zero_a \alu_alu0_op__invert_a { \alu_alu0_op__oe__oe_ok \alu_alu0_op__oe__oe } { \alu_alu0_op__rc__rc_ok \alu_alu0_op__rc__rc } { \alu_alu0_op__imm_data__imm_ok \alu_alu0_op__imm_data__imm } \alu_alu0_op__fn_unit \alu_alu0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__input_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+    assign \alu_alu0_alu_op__insn_type 7'0000000
+    assign \alu_alu0_alu_op__fn_unit 11'00000000000
+    assign \alu_alu0_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_alu0_alu_op__imm_data__imm_ok 1'0
+    assign \alu_alu0_alu_op__rc__rc 1'0
+    assign \alu_alu0_alu_op__rc__rc_ok 1'0
+    assign \alu_alu0_alu_op__oe__oe 1'0
+    assign \alu_alu0_alu_op__oe__oe_ok 1'0
+    assign \alu_alu0_alu_op__invert_a 1'0
+    assign \alu_alu0_alu_op__zero_a 1'0
+    assign \alu_alu0_alu_op__invert_out 1'0
+    assign \alu_alu0_alu_op__write_cr0 1'0
+    assign \alu_alu0_alu_op__input_carry 2'00
+    assign \alu_alu0_alu_op__output_carry 1'0
+    assign \alu_alu0_alu_op__is_32bit 1'0
+    assign \alu_alu0_alu_op__is_signed 1'0
+    assign \alu_alu0_alu_op__data_len 4'0000
+    assign \alu_alu0_alu_op__insn 32'00000000000000000000000000000000
+    assign { \alu_alu0_alu_op__insn \alu_alu0_alu_op__data_len \alu_alu0_alu_op__is_signed \alu_alu0_alu_op__is_32bit \alu_alu0_alu_op__output_carry \alu_alu0_alu_op__input_carry \alu_alu0_alu_op__write_cr0 \alu_alu0_alu_op__invert_out \alu_alu0_alu_op__zero_a \alu_alu0_alu_op__invert_a { \alu_alu0_alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe } { \alu_alu0_alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc } { \alu_alu0_alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm } \alu_alu0_alu_op__fn_unit \alu_alu0_alu_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__input_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $114
     parameter \WIDTH 1
     connect \A \src_l_q_src [0]
@@ -51704,11 +51704,11 @@ module \alu0
     assign \src_sel $113
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $116
     parameter \WIDTH 64
     connect \A \src1_i
@@ -51721,11 +51721,11 @@ module \alu0
     assign \src_or_imm $115
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel$117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $119
     parameter \WIDTH 1
     connect \A \src_l_q_src [1]
@@ -51738,11 +51738,11 @@ module \alu0
     assign \src_sel$117 $118
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm$120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $122
     parameter \WIDTH 64
     connect \A \src2_i
@@ -51888,9 +51888,9 @@ module \alu0
     assign \alu_alu0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51924,9 +51924,9 @@ module \alu0
     assign \alu_alu0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51956,13 +51956,13 @@ module \alu0
     sync init
   end
   process $group_118
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -51970,12 +51970,12 @@ module \alu0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $135
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51983,9 +51983,9 @@ module \alu0
     connect \A \oper_r__zero_a
     connect \Y $137
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -51993,9 +51993,9 @@ module \alu0
     connect \A \oper_r__imm_data__imm_ok
     connect \Y $139
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -52006,19 +52006,19 @@ module \alu0
     connect \B { 1'1 1'1 $139 $137 }
     connect \Y $141
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $143
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $143
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $145
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $146
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -52030,78 +52030,78 @@ module \alu0
     connect \Y $145
   end
   process $group_119
-    assign \rd__rel 4'0000
-    assign \rd__rel $145
+    assign \cu_rd__rel_o 4'0000
+    assign \cu_rd__rel_o $145
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $147
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $148
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $147
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $149
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $150
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $149
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $151
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $151
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $153
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $153
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $155
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $155
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 5 $157
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $158
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -52112,9 +52112,9 @@ module \alu0
     connect \B { $147 $149 $151 $153 $155 }
     connect \Y $157
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 5 $159
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -52122,124 +52122,124 @@ module \alu0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A $157
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $159
   end
   process $group_120
-    assign \wr__rel 5'00000
-    assign \wr__rel $159
+    assign \cu_wr__rel_o 5'00000
+    assign \cu_wr__rel_o $159
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $161
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $161
   end
   process $group_121
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $161 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $163
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $163
   end
   process $group_122
     assign \dest2_o 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $163 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $165
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $166
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $165
   end
   process $group_123
     assign \dest3_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $165 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $167
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $168
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [3]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [3]
+    connect \B \cu_busy_o
     connect \Y $167
   end
   process $group_124
     assign \dest4_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $167 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $169
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $170
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [4]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [4]
+    connect \B \cu_busy_o
     connect \Y $169
   end
   process $group_125
     assign \dest5_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $169 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0]
     end
@@ -52283,9 +52283,9 @@ module \n$5
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -52339,9 +52339,9 @@ module \n$8
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -52361,7 +52361,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main"
 module \main$9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -52436,8 +52436,8 @@ module \main$9
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \cr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -52450,27 +52450,27 @@ module \main$9
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 3 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \cr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 3 \cr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \cr_op__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \cr_op__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 6 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 7 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 32 input 8 \full_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 9 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 10 \cr_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 11 \cr_c
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 12 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -52545,8 +52545,8 @@ module \main$9
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 13 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 13 \cr_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -52559,36 +52559,36 @@ module \main$9
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 14 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 15 \op__insn$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 16 \op__read_cr_whole$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 17 \op__write_cr_whole$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 14 \cr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 15 \cr_op__insn$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 16 \cr_op__read_cr_whole$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 17 \cr_op__write_cr_whole$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 18 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 19 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 output 20 \full_cr$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 21 \full_cr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 22 \cr_a$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 23 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:47"
   wire width 32 \mask
   process $group_0
     assign \mask 32'00000000000000000000000000000000
-    assign \mask { { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] } }
+    assign \mask { { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] } }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 5 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   cell $pos $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -52604,7 +52604,7 @@ module \main$9
     assign \cr_a$8 4'0000
     assign \cr_a_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -52649,14 +52649,14 @@ module \main$9
   process $group_3
     assign \lut 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66"
       attribute \nmigen.decoding "OP_CROP/69"
       case 7'1000101
-        assign \lut \op__insn [9:6]
+        assign \lut \cr_op__insn [9:6]
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112"
       attribute \nmigen.decoding "OP_MTCRF/48"
       case 7'0110000
@@ -52684,14 +52684,14 @@ module \main$9
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 3
     connect \A 2'11
-    connect \B { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [1:0]
+    connect \B { \cr_op__insn [25] \cr_op__insn [24] \cr_op__insn [23] \cr_op__insn [22] \cr_op__insn [21] } [1:0]
     connect \Y $12
   end
   connect $11 $12
   process $group_4
     assign \bt 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -52728,14 +52728,14 @@ module \main$9
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 3
     connect \A 2'11
-    connect \B { \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] } [1:0]
+    connect \B { \cr_op__insn [20] \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] } [1:0]
     connect \Y $15
   end
   connect $14 $15
   process $group_5
     assign \ba 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -52772,14 +52772,14 @@ module \main$9
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 3
     connect \A 2'11
-    connect \B { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] } [1:0]
+    connect \B { \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] \cr_op__insn [11] } [1:0]
     connect \Y $18
   end
   connect $17 $18
   process $group_6
     assign \bb 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -52807,7 +52807,7 @@ module \main$9
   process $group_7
     assign \bit_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -52845,7 +52845,7 @@ module \main$9
   process $group_8
     assign \bit_b 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -52911,7 +52911,7 @@ module \main$9
   process $group_9
     assign \bit_o 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -52986,7 +52986,7 @@ module \main$9
   process $group_10
     assign \full_cr$7 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -53012,7 +53012,7 @@ module \main$9
   process $group_11
     assign \full_cr_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -53040,7 +53040,7 @@ module \main$9
   process $group_12
     assign \move_one 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -53053,7 +53053,7 @@ module \main$9
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120"
       attribute \nmigen.decoding "OP_MFCR/45"
       case 7'0101101
-        assign \move_one \op__insn [20]
+        assign \move_one \cr_op__insn [20]
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138"
       attribute \nmigen.decoding "OP_ISEL/35"
       case 7'0100011
@@ -53086,9 +53086,9 @@ module \main$9
     connect \A $35
     connect \Y $34
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   cell $pos $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
@@ -53122,7 +53122,7 @@ module \main$9
     assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \o_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -53178,7 +53178,7 @@ module \main$9
   process $group_15
     assign \cr_bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55"
-    switch \op__insn_type
+    switch \cr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57"
       attribute \nmigen.decoding "OP_MCRF/42"
       case 7'0101010
@@ -53195,7 +53195,7 @@ module \main$9
       attribute \nmigen.decoding "OP_ISEL/35"
       case 7'0100011
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:147"
-        switch { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] } [1:0]
+        switch { \cr_op__insn [10] \cr_op__insn [9] \cr_op__insn [8] \cr_op__insn [7] \cr_op__insn [6] } [1:0]
           case 2'00
             assign \cr_bit \cr_a [3]
           case 2'01
@@ -53217,12 +53217,12 @@ module \main$9
     sync init
   end
   process $group_17
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__insn$4 32'00000000000000000000000000000000
-    assign \op__read_cr_whole$5 1'0
-    assign \op__write_cr_whole$6 1'0
-    assign { \op__write_cr_whole$6 \op__read_cr_whole$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__write_cr_whole \op__read_cr_whole \op__insn \op__fn_unit \op__insn_type }
+    assign \cr_op__insn_type$2 7'0000000
+    assign \cr_op__fn_unit$3 11'00000000000
+    assign \cr_op__insn$4 32'00000000000000000000000000000000
+    assign \cr_op__read_cr_whole$5 1'0
+    assign \cr_op__write_cr_whole$6 1'0
+    assign { \cr_op__write_cr_whole$6 \cr_op__read_cr_whole$5 \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type }
     sync init
   end
 end
@@ -53237,7 +53237,7 @@ module \pipe$6
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -53312,8 +53312,8 @@ module \pipe$6
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \cr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -53326,33 +53326,33 @@ module \pipe$6
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 7 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \cr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 7 \cr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \cr_op__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \cr_op__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 10 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 11 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 32 input 12 \full_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 13 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 14 \cr_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 15 \cr_c
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 16 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 17 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 18 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -53427,10 +53427,10 @@ module \pipe$6
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 19 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 19 \cr_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \cr_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -53443,45 +53443,45 @@ module \pipe$6
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 20 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 21 \op__insn$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 22 \op__read_cr_whole$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__read_cr_whole$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 23 \op__write_cr_whole$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr_whole$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 20 \cr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \cr_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 21 \cr_op__insn$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \cr_op__insn$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 22 \cr_op__read_cr_whole$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \cr_op__read_cr_whole$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 23 \cr_op__write_cr_whole$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \cr_op__write_cr_whole$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 24 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 25 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 output 26 \full_cr$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 \full_cr$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \full_cr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \full_cr_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 28 \cr_a$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$next
   cell \p$7 \p
     connect \p_valid_i \p_valid_i
@@ -53491,7 +53491,7 @@ module \pipe$6
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -53566,8 +53566,8 @@ module \pipe$6
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_cr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -53580,27 +53580,27 @@ module \pipe$6
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_cr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_cr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_cr_op__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_cr_op__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 32 \main_full_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \main_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \main_cr_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \main_cr_c
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid$9
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -53675,8 +53675,8 @@ module \pipe$6
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_cr_op__insn_type$10
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -53689,33 +53689,33 @@ module \pipe$6
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__read_cr_whole$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__write_cr_whole$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_cr_op__fn_unit$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_cr_op__insn$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_cr_op__read_cr_whole$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_cr_op__write_cr_whole$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 \main_full_cr$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_full_cr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \main_cr_a$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_cr_a_ok
   cell \main$9 \main
     connect \muxid \main_muxid
-    connect \op__insn_type \main_op__insn_type
-    connect \op__fn_unit \main_op__fn_unit
-    connect \op__insn \main_op__insn
-    connect \op__read_cr_whole \main_op__read_cr_whole
-    connect \op__write_cr_whole \main_op__write_cr_whole
+    connect \cr_op__insn_type \main_cr_op__insn_type
+    connect \cr_op__fn_unit \main_cr_op__fn_unit
+    connect \cr_op__insn \main_cr_op__insn
+    connect \cr_op__read_cr_whole \main_cr_op__read_cr_whole
+    connect \cr_op__write_cr_whole \main_cr_op__write_cr_whole
     connect \ra \main_ra
     connect \rb \main_rb
     connect \full_cr \main_full_cr
@@ -53723,11 +53723,11 @@ module \pipe$6
     connect \cr_b \main_cr_b
     connect \cr_c \main_cr_c
     connect \muxid$1 \main_muxid$9
-    connect \op__insn_type$2 \main_op__insn_type$10
-    connect \op__fn_unit$3 \main_op__fn_unit$11
-    connect \op__insn$4 \main_op__insn$12
-    connect \op__read_cr_whole$5 \main_op__read_cr_whole$13
-    connect \op__write_cr_whole$6 \main_op__write_cr_whole$14
+    connect \cr_op__insn_type$2 \main_cr_op__insn_type$10
+    connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$11
+    connect \cr_op__insn$4 \main_cr_op__insn$12
+    connect \cr_op__read_cr_whole$5 \main_cr_op__read_cr_whole$13
+    connect \cr_op__write_cr_whole$6 \main_cr_op__write_cr_whole$14
     connect \o \main_o
     connect \o_ok \main_o_ok
     connect \full_cr$7 \main_full_cr$15
@@ -53741,12 +53741,12 @@ module \pipe$6
     sync init
   end
   process $group_1
-    assign \main_op__insn_type 7'0000000
-    assign \main_op__fn_unit 11'00000000000
-    assign \main_op__insn 32'00000000000000000000000000000000
-    assign \main_op__read_cr_whole 1'0
-    assign \main_op__write_cr_whole 1'0
-    assign { \main_op__write_cr_whole \main_op__read_cr_whole \main_op__insn \main_op__fn_unit \main_op__insn_type } { \op__write_cr_whole \op__read_cr_whole \op__insn \op__fn_unit \op__insn_type }
+    assign \main_cr_op__insn_type 7'0000000
+    assign \main_cr_op__fn_unit 11'00000000000
+    assign \main_cr_op__insn 32'00000000000000000000000000000000
+    assign \main_cr_op__read_cr_whole 1'0
+    assign \main_cr_op__write_cr_whole 1'0
+    assign { \main_cr_op__write_cr_whole \main_cr_op__read_cr_whole \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type }
     sync init
   end
   process $group_6
@@ -53813,7 +53813,7 @@ module \pipe$6
     assign \p_valid_i_p_ready_o $18
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$20
   process $group_15
     assign \muxid$20 2'00
@@ -53893,8 +53893,8 @@ module \pipe$6
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \cr_op__insn_type$21
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -53907,26 +53907,26 @@ module \pipe$6
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__read_cr_whole$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr_whole$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \cr_op__fn_unit$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \cr_op__insn$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \cr_op__read_cr_whole$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \cr_op__write_cr_whole$25
   process $group_16
-    assign \op__insn_type$21 7'0000000
-    assign \op__fn_unit$22 11'00000000000
-    assign \op__insn$23 32'00000000000000000000000000000000
-    assign \op__read_cr_whole$24 1'0
-    assign \op__write_cr_whole$25 1'0
-    assign { \op__write_cr_whole$25 \op__read_cr_whole$24 \op__insn$23 \op__fn_unit$22 \op__insn_type$21 } { \main_op__write_cr_whole$14 \main_op__read_cr_whole$13 \main_op__insn$12 \main_op__fn_unit$11 \main_op__insn_type$10 }
+    assign \cr_op__insn_type$21 7'0000000
+    assign \cr_op__fn_unit$22 11'00000000000
+    assign \cr_op__insn$23 32'00000000000000000000000000000000
+    assign \cr_op__read_cr_whole$24 1'0
+    assign \cr_op__write_cr_whole$25 1'0
+    assign { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } { \main_cr_op__write_cr_whole$14 \main_cr_op__read_cr_whole$13 \main_cr_op__insn$12 \main_cr_op__fn_unit$11 \main_cr_op__insn_type$10 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$27
   process $group_21
     assign \o$26 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -53934,9 +53934,9 @@ module \pipe$6
     assign { \o_ok$27 \o$26 } { \main_o_ok \main_o }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 \full_cr$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \full_cr_ok$29
   process $group_23
     assign \full_cr$28 32'00000000000000000000000000000000
@@ -53944,9 +53944,9 @@ module \pipe$6
     assign { \full_cr_ok$29 \full_cr$28 } { \main_full_cr_ok \main_full_cr$15 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$31
   process $group_25
     assign \cr_a$30 4'0000
@@ -53996,32 +53996,32 @@ module \pipe$6
       update \muxid$1 \muxid$1$next
   end
   process $group_29
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__insn$4$next \op__insn$4
-    assign \op__read_cr_whole$5$next \op__read_cr_whole$5
-    assign \op__write_cr_whole$6$next \op__write_cr_whole$6
+    assign \cr_op__insn_type$2$next \cr_op__insn_type$2
+    assign \cr_op__fn_unit$3$next \cr_op__fn_unit$3
+    assign \cr_op__insn$4$next \cr_op__insn$4
+    assign \cr_op__read_cr_whole$5$next \cr_op__read_cr_whole$5
+    assign \cr_op__write_cr_whole$6$next \cr_op__write_cr_whole$6
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__write_cr_whole$6$next \op__read_cr_whole$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__write_cr_whole$25 \op__read_cr_whole$24 \op__insn$23 \op__fn_unit$22 \op__insn_type$21 }
+        assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__write_cr_whole$6$next \op__read_cr_whole$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__write_cr_whole$25 \op__read_cr_whole$24 \op__insn$23 \op__fn_unit$22 \op__insn_type$21 }
+        assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 }
     end
     sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__insn$4 32'00000000000000000000000000000000
-      update \op__read_cr_whole$5 1'0
-      update \op__write_cr_whole$6 1'0
+      update \cr_op__insn_type$2 7'0000000
+      update \cr_op__fn_unit$3 11'00000000000
+      update \cr_op__insn$4 32'00000000000000000000000000000000
+      update \cr_op__read_cr_whole$5 1'0
+      update \cr_op__write_cr_whole$6 1'0
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__insn$4 \op__insn$4$next
-      update \op__read_cr_whole$5 \op__read_cr_whole$5$next
-      update \op__write_cr_whole$6 \op__write_cr_whole$6$next
+      update \cr_op__insn_type$2 \cr_op__insn_type$2$next
+      update \cr_op__fn_unit$3 \cr_op__fn_unit$3$next
+      update \cr_op__insn$4 \cr_op__insn$4$next
+      update \cr_op__read_cr_whole$5 \cr_op__read_cr_whole$5$next
+      update \cr_op__write_cr_whole$6 \cr_op__write_cr_whole$6$next
   end
   process $group_34
     assign \o$next \o
@@ -54113,21 +54113,21 @@ module \alu_cr0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \full_cr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 6 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 7 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 output 8 \full_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 9 \cr_a
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -54202,8 +54202,8 @@ module \alu_cr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 10 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 10 \cr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -54216,25 +54216,25 @@ module \alu_cr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 11 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 12 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 11 \cr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 12 \cr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \cr_op__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \cr_op__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 15 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 16 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 32 input 17 \full_cr$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 18 \cr_a$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 19 \cr_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 20 \cr_c
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 21 \p_valid_i
@@ -54252,7 +54252,7 @@ module \alu_cr0
   wire width 1 \pipe_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -54327,8 +54327,8 @@ module \alu_cr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_cr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -54341,31 +54341,31 @@ module \alu_cr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_cr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_cr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_cr_op__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_cr_op__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 32 \pipe_full_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \pipe_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \pipe_cr_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \pipe_cr_c
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \pipe_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \pipe_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid$3
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -54440,8 +54440,8 @@ module \alu_cr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_cr_op__insn_type$4
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -54454,25 +54454,25 @@ module \alu_cr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__read_cr_whole$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__write_cr_whole$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_cr_op__fn_unit$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_cr_op__insn$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_cr_op__read_cr_whole$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_cr_op__write_cr_whole$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 \pipe_full_cr$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_full_cr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \pipe_cr_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_cr_a_ok
   cell \pipe$6 \pipe
     connect \rst \rst
@@ -54480,11 +54480,11 @@ module \alu_cr0
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
-    connect \op__insn_type \pipe_op__insn_type
-    connect \op__fn_unit \pipe_op__fn_unit
-    connect \op__insn \pipe_op__insn
-    connect \op__read_cr_whole \pipe_op__read_cr_whole
-    connect \op__write_cr_whole \pipe_op__write_cr_whole
+    connect \cr_op__insn_type \pipe_cr_op__insn_type
+    connect \cr_op__fn_unit \pipe_cr_op__fn_unit
+    connect \cr_op__insn \pipe_cr_op__insn
+    connect \cr_op__read_cr_whole \pipe_cr_op__read_cr_whole
+    connect \cr_op__write_cr_whole \pipe_cr_op__write_cr_whole
     connect \ra \pipe_ra
     connect \rb \pipe_rb
     connect \full_cr \pipe_full_cr
@@ -54494,11 +54494,11 @@ module \alu_cr0
     connect \n_valid_o \pipe_n_valid_o
     connect \n_ready_i \pipe_n_ready_i
     connect \muxid$1 \pipe_muxid$3
-    connect \op__insn_type$2 \pipe_op__insn_type$4
-    connect \op__fn_unit$3 \pipe_op__fn_unit$5
-    connect \op__insn$4 \pipe_op__insn$6
-    connect \op__read_cr_whole$5 \pipe_op__read_cr_whole$7
-    connect \op__write_cr_whole$6 \pipe_op__write_cr_whole$8
+    connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4
+    connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5
+    connect \cr_op__insn$4 \pipe_cr_op__insn$6
+    connect \cr_op__read_cr_whole$5 \pipe_cr_op__read_cr_whole$7
+    connect \cr_op__write_cr_whole$6 \pipe_cr_op__write_cr_whole$8
     connect \o \pipe_o
     connect \o_ok \pipe_o_ok
     connect \full_cr$7 \pipe_full_cr$9
@@ -54516,7 +54516,7 @@ module \alu_cr0
     assign \p_ready_o \pipe_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_2
     assign \pipe_muxid 2'00
@@ -54524,12 +54524,12 @@ module \alu_cr0
     sync init
   end
   process $group_3
-    assign \pipe_op__insn_type 7'0000000
-    assign \pipe_op__fn_unit 11'00000000000
-    assign \pipe_op__insn 32'00000000000000000000000000000000
-    assign \pipe_op__read_cr_whole 1'0
-    assign \pipe_op__write_cr_whole 1'0
-    assign { \pipe_op__write_cr_whole \pipe_op__read_cr_whole \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__write_cr_whole \op__read_cr_whole \op__insn \op__fn_unit \op__insn_type }
+    assign \pipe_cr_op__insn_type 7'0000000
+    assign \pipe_cr_op__fn_unit 11'00000000000
+    assign \pipe_cr_op__insn 32'00000000000000000000000000000000
+    assign \pipe_cr_op__read_cr_whole 1'0
+    assign \pipe_cr_op__write_cr_whole 1'0
+    assign { \pipe_cr_op__write_cr_whole \pipe_cr_op__read_cr_whole \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type }
     sync init
   end
   process $group_8
@@ -54572,7 +54572,7 @@ module \alu_cr0
     assign \pipe_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$11
   process $group_16
     assign \muxid$11 2'00
@@ -54652,8 +54652,8 @@ module \alu_cr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \cr_op__insn_type$12
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -54666,21 +54666,21 @@ module \alu_cr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__read_cr_whole$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr_whole$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \cr_op__fn_unit$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \cr_op__insn$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \cr_op__read_cr_whole$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \cr_op__write_cr_whole$16
   process $group_17
-    assign \op__insn_type$12 7'0000000
-    assign \op__fn_unit$13 11'00000000000
-    assign \op__insn$14 32'00000000000000000000000000000000
-    assign \op__read_cr_whole$15 1'0
-    assign \op__write_cr_whole$16 1'0
-    assign { \op__write_cr_whole$16 \op__read_cr_whole$15 \op__insn$14 \op__fn_unit$13 \op__insn_type$12 } { \pipe_op__write_cr_whole$8 \pipe_op__read_cr_whole$7 \pipe_op__insn$6 \pipe_op__fn_unit$5 \pipe_op__insn_type$4 }
+    assign \cr_op__insn_type$12 7'0000000
+    assign \cr_op__fn_unit$13 11'00000000000
+    assign \cr_op__insn$14 32'00000000000000000000000000000000
+    assign \cr_op__read_cr_whole$15 1'0
+    assign \cr_op__write_cr_whole$16 1'0
+    assign { \cr_op__write_cr_whole$16 \cr_op__read_cr_whole$15 \cr_op__insn$14 \cr_op__fn_unit$13 \cr_op__insn_type$12 } { \pipe_cr_op__write_cr_whole$8 \pipe_cr_op__read_cr_whole$7 \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 }
     sync init
   end
   process $group_22
@@ -55798,8 +55798,8 @@ module \cr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \oper_i_alu_cr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -55812,65 +55812,65 @@ module \cr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 4 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \oper_i__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \oper_i__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 7 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \oper_i_alu_cr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 4 \oper_i_alu_cr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \oper_i_alu_cr0__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \oper_i_alu_cr0__write_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 8 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 6 input 9 \rdmaskn
+  wire width 1 input 7 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 8 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 input 9 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 10 \rd__rel
+  wire width 6 output 10 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 11 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 6 input 11 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 12 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 13 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 32 input 14 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 4 input 15 \src4_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 4 input 16 \src5_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 4 input 17 \src6_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 18 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 19 \wr__rel
+  wire width 3 output 19 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 20 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 3 input 20 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 21 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 22 \full_cr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 32 output 23 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 24 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 output 25 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 26 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 27 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 26 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 27 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_cr0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_cr0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_cr0_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 32 \alu_cr0_full_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \alu_cr0_cr_a
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -55945,8 +55945,8 @@ module \cr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_cr0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_cr0_cr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -55959,25 +55959,25 @@ module \cr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_cr0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_cr0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_cr0_op__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_cr0_op__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_cr0_cr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_cr0_cr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_cr0_cr_op__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_cr0_cr_op__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_cr0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_cr0_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 32 \alu_cr0_full_cr$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \alu_cr0_cr_a$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \alu_cr0_cr_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \alu_cr0_cr_c
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_cr0_p_valid_i
@@ -55994,11 +55994,11 @@ module \cr0
     connect \o \alu_cr0_o
     connect \full_cr \alu_cr0_full_cr
     connect \cr_a \alu_cr0_cr_a
-    connect \op__insn_type \alu_cr0_op__insn_type
-    connect \op__fn_unit \alu_cr0_op__fn_unit
-    connect \op__insn \alu_cr0_op__insn
-    connect \op__read_cr_whole \alu_cr0_op__read_cr_whole
-    connect \op__write_cr_whole \alu_cr0_op__write_cr_whole
+    connect \cr_op__insn_type \alu_cr0_cr_op__insn_type
+    connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit
+    connect \cr_op__insn \alu_cr0_cr_op__insn
+    connect \cr_op__read_cr_whole \alu_cr0_cr_op__read_cr_whole
+    connect \cr_op__write_cr_whole \alu_cr0_cr_op__write_cr_whole
     connect \ra \alu_cr0_ra
     connect \rb \alu_cr0_rb
     connect \full_cr$1 \alu_cr0_full_cr$1
@@ -56110,36 +56110,36 @@ module \cr0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 6 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $6
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 6 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -56147,10 +56147,10 @@ module \cr0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A $6
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -56158,9 +56158,9 @@ module \cr0
     connect \A $8
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56176,9 +56176,9 @@ module \cr0
     assign \all_rd $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -56188,11 +56188,11 @@ module \cr0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56200,9 +56200,9 @@ module \cr0
     connect \A \all_rd_dly
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56218,16 +56218,16 @@ module \cr0
     assign \all_rd_pulse $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_cr0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -56237,11 +56237,11 @@ module \cr0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56249,9 +56249,9 @@ module \cr0
     connect \A \alu_done_dly
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56267,28 +56267,28 @@ module \cr0
     assign \alu_pulse $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 3 \alu_pulsem
   process $group_6
     assign \alu_pulsem 3'000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 3 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $21
   end
   process $group_7
@@ -56304,38 +56304,38 @@ module \cr0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 3 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 3 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $25
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -56343,7 +56343,7 @@ module \cr0
     connect \A $27
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56351,39 +56351,39 @@ module \cr0
     connect \A $24
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $23
     connect \Y $31
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $31
+    assign \cu_done_o 1'0
+    assign \cu_done_o $31
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -56391,9 +56391,9 @@ module \cr0
     connect \A \prev_wr_go
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56409,11 +56409,11 @@ module \cr0
     assign \wr_any $37
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56421,9 +56421,9 @@ module \cr0
     connect \A \alu_cr0_n_ready_i
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56434,9 +56434,9 @@ module \cr0
     connect \B $39
     connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 3 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -56444,12 +56444,12 @@ module \cr0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -56460,9 +56460,9 @@ module \cr0
     connect \B 1'0
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56473,22 +56473,22 @@ module \cr0
     connect \B $45
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56499,9 +56499,9 @@ module \cr0
     connect \B \alu_cr0_n_ready_i
     connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56512,9 +56512,9 @@ module \cr0
     connect \B \alu_cr0_n_valid_o
     connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56522,25 +56522,25 @@ module \cr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $53
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $55
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $47
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $55 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56548,7 +56548,7 @@ module \cr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $57
   end
   process $group_11
@@ -56556,19 +56556,19 @@ module \cr0
     assign \reset $57
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $59
   end
   process $group_12
@@ -56576,19 +56576,19 @@ module \cr0
     assign \rst_r $59
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 3 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 3 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $61
   end
   process $group_13
@@ -56596,19 +56596,19 @@ module \cr0
     assign \reset_w $61
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 6 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 6 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $63
   end
   process $group_14
@@ -56618,12 +56618,12 @@ module \cr0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -56631,7 +56631,7 @@ module \cr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_cr0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $65
   end
   process $group_16
@@ -56659,7 +56659,7 @@ module \cr0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -56685,7 +56685,7 @@ module \cr0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -56709,9 +56709,9 @@ module \cr0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 3 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -56719,7 +56719,7 @@ module \cr0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $67
   end
   process $group_23
@@ -56727,9 +56727,9 @@ module \cr0
     assign \req_l_s_req $67
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 3 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -56818,7 +56818,7 @@ module \cr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -56832,13 +56832,13 @@ module \cr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__write_cr_whole
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -56866,8 +56866,8 @@ module \cr0
   cell $mux $72
     parameter \WIDTH 52
     connect \A { \oper_l__write_cr_whole \oper_l__read_cr_whole \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type }
+    connect \S \cu_issue_i
     connect \Y $71
   end
   process $group_25
@@ -56886,10 +56886,10 @@ module \cr0
     assign \oper_l__read_cr_whole$next \oper_l__read_cr_whole
     assign \oper_l__write_cr_whole$next \oper_l__write_cr_whole
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__write_cr_whole$next \oper_l__read_cr_whole$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
+        assign { \oper_l__write_cr_whole$next \oper_l__read_cr_whole$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type }
     end
     sync init
       update \oper_l__insn_type 7'0000000
@@ -56904,9 +56904,9 @@ module \cr0
       update \oper_l__read_cr_whole \oper_l__read_cr_whole$next
       update \oper_l__write_cr_whole \oper_l__write_cr_whole$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__o_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__o
@@ -56973,9 +56973,9 @@ module \cr0
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 32 \data_r1__full_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__full_cr_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 32 \data_r1_l__full_cr
@@ -57042,9 +57042,9 @@ module \cr0
       update \data_r1_l__full_cr \data_r1_l__full_cr$next
       update \data_r1_l__full_cr_ok \data_r1_l__full_cr_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 4 \data_r2__cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 4 \data_r2_l__cr_a
@@ -57111,9 +57111,9 @@ module \cr0
       update \data_r2_l__cr_a \data_r2_l__cr_a$next
       update \data_r2_l__cr_a_ok \data_r2_l__cr_a_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $92
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -57121,12 +57121,12 @@ module \cr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__o_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $94
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -57134,12 +57134,12 @@ module \cr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__full_cr_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $93
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $96
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -57147,21 +57147,21 @@ module \cr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__cr_a_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $95
   end
   process $group_47
-    assign \wrmask 3'000
-    assign \wrmask { $95 $93 $91 }
+    assign \cu_wrmask_o 3'000
+    assign \cu_wrmask_o { $95 $93 $91 }
     sync init
   end
   process $group_48
-    assign \alu_cr0_op__insn_type 7'0000000
-    assign \alu_cr0_op__fn_unit 11'00000000000
-    assign \alu_cr0_op__insn 32'00000000000000000000000000000000
-    assign \alu_cr0_op__read_cr_whole 1'0
-    assign \alu_cr0_op__write_cr_whole 1'0
-    assign { \alu_cr0_op__write_cr_whole \alu_cr0_op__read_cr_whole \alu_cr0_op__insn \alu_cr0_op__fn_unit \alu_cr0_op__insn_type } { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
+    assign \alu_cr0_cr_op__insn_type 7'0000000
+    assign \alu_cr0_cr_op__fn_unit 11'00000000000
+    assign \alu_cr0_cr_op__insn 32'00000000000000000000000000000000
+    assign \alu_cr0_cr_op__read_cr_whole 1'0
+    assign \alu_cr0_cr_op__write_cr_whole 1'0
+    assign { \alu_cr0_cr_op__write_cr_whole \alu_cr0_cr_op__read_cr_whole \alu_cr0_cr_op__insn \alu_cr0_cr_op__fn_unit \alu_cr0_cr_op__insn_type } { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -57361,9 +57361,9 @@ module \cr0
     assign \alu_cr0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -57397,9 +57397,9 @@ module \cr0
     assign \alu_cr0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -57429,13 +57429,13 @@ module \cr0
     sync init
   end
   process $group_71
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -57443,12 +57443,12 @@ module \cr0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $113
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -57459,19 +57459,19 @@ module \cr0
     connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 }
     connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $117
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -57483,52 +57483,52 @@ module \cr0
     connect \Y $119
   end
   process $group_72
-    assign \rd__rel 6'000000
-    assign \rd__rel $119
+    assign \cu_rd__rel_o 6'000000
+    assign \cu_rd__rel_o $119
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $121
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $123
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $125
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -57539,9 +57539,9 @@ module \cr0
     connect \B { $121 $123 $125 }
     connect \Y $127
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -57549,78 +57549,78 @@ module \cr0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A $127
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $129
   end
   process $group_73
-    assign \wr__rel 3'000
-    assign \wr__rel $129
+    assign \cu_wr__rel_o 3'000
+    assign \cu_wr__rel_o $129
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $131
   end
   process $group_74
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $131 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $133
   end
   process $group_75
     assign \dest2_o 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $133 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__full_cr_ok \data_r1__full_cr } [31:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $135
   end
   process $group_76
     assign \dest3_o 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $135 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__cr_a_ok \data_r2__cr_a } [3:0]
     end
@@ -57664,9 +57664,9 @@ module \n$18
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -57720,9 +57720,9 @@ module \n$21
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -57742,10 +57742,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main"
 module \main$22
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 1 \op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 1 \br_op__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -57819,8 +57819,8 @@ module \main$22
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \br_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -57833,28 +57833,28 @@ module \main$22
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 4 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 5 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \br_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 4 \br_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 5 \br_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \br_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \br_op__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \br_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 9 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 10 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 11 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 12 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 13 \op__cia$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 13 \br_op__cia$2
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -57928,8 +57928,8 @@ module \main$22
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 14 \op__insn_type$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 14 \br_op__insn_type$3
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -57942,29 +57942,29 @@ module \main$22
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 15 \op__fn_unit$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 16 \op__insn$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 17 \op__imm_data__imm$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 18 \op__imm_data__imm_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 19 \op__lk$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 20 \op__is_32bit$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 15 \br_op__fn_unit$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 16 \br_op__insn$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 17 \br_op__imm_data__imm$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 18 \br_op__imm_data__imm_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 19 \br_op__lk$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 20 \br_op__is_32bit$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 21 \fast1$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 22 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 23 \fast2$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 24 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 25 \nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 26 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:84"
   wire width 64 \br_addr
@@ -57977,7 +57977,7 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \br_op__insn_type
     connect \B 7'0001000
     connect \Y $12
   end
@@ -57990,7 +57990,7 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [1] }
+    connect \A { \br_op__insn [1] }
     connect \B $12
     connect \Y $14
   end
@@ -58008,7 +58008,7 @@ module \main$22
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 65
     connect \A \br_imm_addr
-    connect \B \op__cia
+    connect \B \br_op__cia
     connect \Y $17
   end
   connect $16 $17
@@ -58029,7 +58029,7 @@ module \main$22
   wire width 2 \bi
   process $group_1
     assign \bi 2'00
-    assign \bi { \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] } [1:0]
+    assign \bi { \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] } [1:0]
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
@@ -58055,7 +58055,7 @@ module \main$22
     assign \ctr_write 1'0
     assign \ctr_write 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
-    switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
+    switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
       case 1'1
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
@@ -58076,7 +58076,7 @@ module \main$22
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \cr_bit
-    connect \B { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [3]
+    connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [3]
     connect \Y $19
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
@@ -58089,7 +58089,7 @@ module \main$22
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $19
-    connect \B { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4]
+    connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4]
     connect \Y $21
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
@@ -58101,7 +58101,7 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4:3]
+    connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3]
     connect \B 1'0
     connect \Y $23
   end
@@ -58114,7 +58114,7 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4:3]
+    connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3]
     connect \B 1'1
     connect \Y $25
   end
@@ -58127,7 +58127,7 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4]
+    connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4]
     connect \B 1'1
     connect \Y $27
   end
@@ -58172,7 +58172,7 @@ module \main$22
   process $group_4
     assign \bc_taken 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
-    switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
+    switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
       case 1'1
         assign \bc_taken $21
@@ -58214,7 +58214,7 @@ module \main$22
   process $group_5
     assign \ctr_n 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
-    switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
+    switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
       case 1'1
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
@@ -58226,7 +58226,7 @@ module \main$22
   process $group_6
     assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
-    switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
+    switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
       case 1'1
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
@@ -58250,13 +58250,13 @@ module \main$22
   process $group_7
     assign \ctr_m 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
-    switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
+    switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
       case 1'1
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
       case
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
-        switch { \op__is_32bit }
+        switch { \br_op__is_32bit }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
           case 1'1
             assign \ctr_m $38
@@ -58286,14 +58286,14 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [1]
+    connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [1]
     connect \B $40
     connect \Y $42
   end
   process $group_8
     assign \ctr_zero_bo1 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
-    switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
+    switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
       case 1'1
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
@@ -58309,7 +58309,7 @@ module \main$22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] } [5]
+    connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [5]
     connect \Y $44
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
@@ -58321,22 +58321,22 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] } [9]
+    connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [9]
     connect \B $44
     connect \Y $46
   end
   process $group_9
     assign \br_imm_addr 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
-    switch \op__insn_type
+    switch \br_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
       attribute \nmigen.decoding "OP_B/6"
       case 7'0000110
-        assign \br_imm_addr { { { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] } { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } } 2'00 }
+        assign \br_imm_addr { { { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] } { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:144"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-        assign \br_imm_addr { { { { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] } { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } } 2'00 }
+        assign \br_imm_addr { { { { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] } { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:150"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
@@ -58357,7 +58357,7 @@ module \main$22
   process $group_10
     assign \br_taken 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
-    switch \op__insn_type
+    switch \br_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
       attribute \nmigen.decoding "OP_B/6"
       case 7'0000110
@@ -58376,7 +58376,7 @@ module \main$22
   process $group_11
     assign \fast1_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
-    switch \op__insn_type
+    switch \br_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
       attribute \nmigen.decoding "OP_B/6"
       case 7'0000110
@@ -58412,7 +58412,7 @@ module \main$22
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 65
-    connect \A \op__cia
+    connect \A \br_op__cia
     connect \B 3'100
     connect \Y $49
   end
@@ -58420,7 +58420,7 @@ module \main$22
   process $group_14
     assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
-    switch { \op__lk }
+    switch { \br_op__lk }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
       case 1'1
         assign \fast2$11 $48 [63:0]
@@ -58430,7 +58430,7 @@ module \main$22
   process $group_15
     assign \fast2_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
-    switch { \op__lk }
+    switch { \br_op__lk }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
       case 1'1
         assign \fast2_ok 1'1
@@ -58443,15 +58443,15 @@ module \main$22
     sync init
   end
   process $group_17
-    assign \op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__insn_type$3 7'0000000
-    assign \op__fn_unit$4 11'00000000000
-    assign \op__insn$5 32'00000000000000000000000000000000
-    assign \op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$7 1'0
-    assign \op__lk$8 1'0
-    assign \op__is_32bit$9 1'0
-    assign { \op__is_32bit$9 \op__lk$8 { \op__imm_data__imm_ok$7 \op__imm_data__imm$6 } \op__insn$5 \op__fn_unit$4 \op__insn_type$3 \op__cia$2 } { \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__insn \op__fn_unit \op__insn_type \op__cia }
+    assign \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \br_op__insn_type$3 7'0000000
+    assign \br_op__fn_unit$4 11'00000000000
+    assign \br_op__insn$5 32'00000000000000000000000000000000
+    assign \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \br_op__imm_data__imm_ok$7 1'0
+    assign \br_op__lk$8 1'0
+    assign \br_op__is_32bit$9 1'0
+    assign { \br_op__is_32bit$9 \br_op__lk$8 { \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm$6 } \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia }
     sync init
   end
 end
@@ -58466,10 +58466,10 @@ module \pipe$19
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 5 \op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 5 \br_op__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -58543,8 +58543,8 @@ module \pipe$19
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 6 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 6 \br_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -58557,36 +58557,36 @@ module \pipe$19
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 7 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 8 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 9 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 7 \br_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 8 \br_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 9 \br_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \br_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \br_op__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \br_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 13 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 14 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 15 \cr_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 16 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 17 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 18 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 19 \op__cia$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__cia$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 19 \br_op__cia$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \br_op__cia$2$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -58660,10 +58660,10 @@ module \pipe$19
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 20 \op__insn_type$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 20 \br_op__insn_type$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \br_op__insn_type$3$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -58676,53 +58676,53 @@ module \pipe$19
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 21 \op__fn_unit$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 22 \op__insn$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 23 \op__imm_data__imm$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 24 \op__imm_data__imm_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__lk$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__lk$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__is_32bit$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 21 \br_op__fn_unit$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \br_op__fn_unit$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 22 \br_op__insn$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \br_op__insn$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 23 \br_op__imm_data__imm$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \br_op__imm_data__imm$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 24 \br_op__imm_data__imm_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__imm_data__imm_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \br_op__lk$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__lk$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \br_op__is_32bit$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__is_32bit$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 27 \fast1$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast1$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 28 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast1_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 29 \fast2$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast2$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 30 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast2_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 31 \nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \nia$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 32 \nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \nia_ok$next
   cell \p$20 \p
     connect \p_valid_i \p_valid_i
@@ -58732,10 +58732,10 @@ module \pipe$19
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_br_op__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -58809,8 +58809,8 @@ module \pipe$19
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_br_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -58823,28 +58823,28 @@ module \pipe$19
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_br_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_br_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_br_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_br_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_br_op__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_br_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \main_cr_a
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__cia$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_br_op__cia$13
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -58918,8 +58918,8 @@ module \pipe$19
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_br_op__insn_type$14
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -58932,52 +58932,52 @@ module \pipe$19
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__lk$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_br_op__fn_unit$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_br_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_br_op__imm_data__imm$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_br_op__imm_data__imm_ok$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_br_op__lk$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_br_op__is_32bit$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_fast1$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_fast2$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_nia_ok
   cell \main$22 \main
     connect \muxid \main_muxid
-    connect \op__cia \main_op__cia
-    connect \op__insn_type \main_op__insn_type
-    connect \op__fn_unit \main_op__fn_unit
-    connect \op__insn \main_op__insn
-    connect \op__imm_data__imm \main_op__imm_data__imm
-    connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
-    connect \op__lk \main_op__lk
-    connect \op__is_32bit \main_op__is_32bit
+    connect \br_op__cia \main_br_op__cia
+    connect \br_op__insn_type \main_br_op__insn_type
+    connect \br_op__fn_unit \main_br_op__fn_unit
+    connect \br_op__insn \main_br_op__insn
+    connect \br_op__imm_data__imm \main_br_op__imm_data__imm
+    connect \br_op__imm_data__imm_ok \main_br_op__imm_data__imm_ok
+    connect \br_op__lk \main_br_op__lk
+    connect \br_op__is_32bit \main_br_op__is_32bit
     connect \fast1 \main_fast1
     connect \fast2 \main_fast2
     connect \cr_a \main_cr_a
     connect \muxid$1 \main_muxid$12
-    connect \op__cia$2 \main_op__cia$13
-    connect \op__insn_type$3 \main_op__insn_type$14
-    connect \op__fn_unit$4 \main_op__fn_unit$15
-    connect \op__insn$5 \main_op__insn$16
-    connect \op__imm_data__imm$6 \main_op__imm_data__imm$17
-    connect \op__imm_data__imm_ok$7 \main_op__imm_data__imm_ok$18
-    connect \op__lk$8 \main_op__lk$19
-    connect \op__is_32bit$9 \main_op__is_32bit$20
+    connect \br_op__cia$2 \main_br_op__cia$13
+    connect \br_op__insn_type$3 \main_br_op__insn_type$14
+    connect \br_op__fn_unit$4 \main_br_op__fn_unit$15
+    connect \br_op__insn$5 \main_br_op__insn$16
+    connect \br_op__imm_data__imm$6 \main_br_op__imm_data__imm$17
+    connect \br_op__imm_data__imm_ok$7 \main_br_op__imm_data__imm_ok$18
+    connect \br_op__lk$8 \main_br_op__lk$19
+    connect \br_op__is_32bit$9 \main_br_op__is_32bit$20
     connect \fast1$10 \main_fast1$21
     connect \fast1_ok \main_fast1_ok
     connect \fast2$11 \main_fast2$22
@@ -58991,15 +58991,15 @@ module \pipe$19
     sync init
   end
   process $group_1
-    assign \main_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_op__insn_type 7'0000000
-    assign \main_op__fn_unit 11'00000000000
-    assign \main_op__insn 32'00000000000000000000000000000000
-    assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_op__imm_data__imm_ok 1'0
-    assign \main_op__lk 1'0
-    assign \main_op__is_32bit 1'0
-    assign { \main_op__is_32bit \main_op__lk { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__insn \main_op__fn_unit \main_op__insn_type \main_op__cia } { \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__insn \op__fn_unit \op__insn_type \op__cia }
+    assign \main_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_br_op__insn_type 7'0000000
+    assign \main_br_op__fn_unit 11'00000000000
+    assign \main_br_op__insn 32'00000000000000000000000000000000
+    assign \main_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_br_op__imm_data__imm_ok 1'0
+    assign \main_br_op__lk 1'0
+    assign \main_br_op__is_32bit 1'0
+    assign { \main_br_op__is_32bit \main_br_op__lk { \main_br_op__imm_data__imm_ok \main_br_op__imm_data__imm } \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia }
     sync init
   end
   process $group_9
@@ -59051,15 +59051,15 @@ module \pipe$19
     assign \p_valid_i_p_ready_o $24
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$26
   process $group_15
     assign \muxid$26 2'00
     assign \muxid$26 \main_muxid$12
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__cia$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \br_op__cia$27
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -59133,8 +59133,8 @@ module \pipe$19
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \br_op__insn_type$28
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -59147,33 +59147,33 @@ module \pipe$19
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__lk$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \br_op__fn_unit$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \br_op__insn$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \br_op__imm_data__imm$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__imm_data__imm_ok$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__lk$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__is_32bit$34
   process $group_16
-    assign \op__cia$27 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__insn_type$28 7'0000000
-    assign \op__fn_unit$29 11'00000000000
-    assign \op__insn$30 32'00000000000000000000000000000000
-    assign \op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$32 1'0
-    assign \op__lk$33 1'0
-    assign \op__is_32bit$34 1'0
-    assign { \op__is_32bit$34 \op__lk$33 { \op__imm_data__imm_ok$32 \op__imm_data__imm$31 } \op__insn$30 \op__fn_unit$29 \op__insn_type$28 \op__cia$27 } { \main_op__is_32bit$20 \main_op__lk$19 { \main_op__imm_data__imm_ok$18 \main_op__imm_data__imm$17 } \main_op__insn$16 \main_op__fn_unit$15 \main_op__insn_type$14 \main_op__cia$13 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+    assign \br_op__cia$27 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \br_op__insn_type$28 7'0000000
+    assign \br_op__fn_unit$29 11'00000000000
+    assign \br_op__insn$30 32'00000000000000000000000000000000
+    assign \br_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \br_op__imm_data__imm_ok$32 1'0
+    assign \br_op__lk$33 1'0
+    assign \br_op__is_32bit$34 1'0
+    assign { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 { \main_br_op__imm_data__imm_ok$18 \main_br_op__imm_data__imm$17 } \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast1$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast1_ok$36
   process $group_24
     assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -59181,9 +59181,9 @@ module \pipe$19
     assign { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast2$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast2_ok$38
   process $group_26
     assign \fast2$37 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -59191,9 +59191,9 @@ module \pipe$19
     assign { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \nia$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \nia_ok$40
   process $group_28
     assign \nia$39 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -59243,47 +59243,47 @@ module \pipe$19
       update \muxid$1 \muxid$1$next
   end
   process $group_32
-    assign \op__cia$2$next \op__cia$2
-    assign \op__insn_type$3$next \op__insn_type$3
-    assign \op__fn_unit$4$next \op__fn_unit$4
-    assign \op__insn$5$next \op__insn$5
-    assign \op__imm_data__imm$6$next \op__imm_data__imm$6
-    assign \op__imm_data__imm_ok$7$next \op__imm_data__imm_ok$7
-    assign \op__lk$8$next \op__lk$8
-    assign \op__is_32bit$9$next \op__is_32bit$9
+    assign \br_op__cia$2$next \br_op__cia$2
+    assign \br_op__insn_type$3$next \br_op__insn_type$3
+    assign \br_op__fn_unit$4$next \br_op__fn_unit$4
+    assign \br_op__insn$5$next \br_op__insn$5
+    assign \br_op__imm_data__imm$6$next \br_op__imm_data__imm$6
+    assign \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm_ok$7
+    assign \br_op__lk$8$next \br_op__lk$8
+    assign \br_op__is_32bit$9$next \br_op__is_32bit$9
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__is_32bit$9$next \op__lk$8$next { \op__imm_data__imm_ok$7$next \op__imm_data__imm$6$next } \op__insn$5$next \op__fn_unit$4$next \op__insn_type$3$next \op__cia$2$next } { \op__is_32bit$34 \op__lk$33 { \op__imm_data__imm_ok$32 \op__imm_data__imm$31 } \op__insn$30 \op__fn_unit$29 \op__insn_type$28 \op__cia$27 }
+        assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__is_32bit$9$next \op__lk$8$next { \op__imm_data__imm_ok$7$next \op__imm_data__imm$6$next } \op__insn$5$next \op__fn_unit$4$next \op__insn_type$3$next \op__cia$2$next } { \op__is_32bit$34 \op__lk$33 { \op__imm_data__imm_ok$32 \op__imm_data__imm$31 } \op__insn$30 \op__fn_unit$29 \op__insn_type$28 \op__cia$27 }
+        assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \op__imm_data__imm$6$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \op__imm_data__imm_ok$7$next 1'0
+        assign \br_op__imm_data__imm$6$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \br_op__imm_data__imm_ok$7$next 1'0
     end
     sync init
-      update \op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__insn_type$3 7'0000000
-      update \op__fn_unit$4 11'00000000000
-      update \op__insn$5 32'00000000000000000000000000000000
-      update \op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__imm_data__imm_ok$7 1'0
-      update \op__lk$8 1'0
-      update \op__is_32bit$9 1'0
+      update \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \br_op__insn_type$3 7'0000000
+      update \br_op__fn_unit$4 11'00000000000
+      update \br_op__insn$5 32'00000000000000000000000000000000
+      update \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \br_op__imm_data__imm_ok$7 1'0
+      update \br_op__lk$8 1'0
+      update \br_op__is_32bit$9 1'0
     sync posedge \clk
-      update \op__cia$2 \op__cia$2$next
-      update \op__insn_type$3 \op__insn_type$3$next
-      update \op__fn_unit$4 \op__fn_unit$4$next
-      update \op__insn$5 \op__insn$5$next
-      update \op__imm_data__imm$6 \op__imm_data__imm$6$next
-      update \op__imm_data__imm_ok$7 \op__imm_data__imm_ok$7$next
-      update \op__lk$8 \op__lk$8$next
-      update \op__is_32bit$9 \op__is_32bit$9$next
+      update \br_op__cia$2 \br_op__cia$2$next
+      update \br_op__insn_type$3 \br_op__insn_type$3$next
+      update \br_op__fn_unit$4 \br_op__fn_unit$4$next
+      update \br_op__insn$5 \br_op__insn$5$next
+      update \br_op__imm_data__imm$6 \br_op__imm_data__imm$6$next
+      update \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm_ok$7$next
+      update \br_op__lk$8 \br_op__lk$8$next
+      update \br_op__is_32bit$9 \br_op__is_32bit$9$next
   end
   process $group_40
     assign \fast1$10$next \fast1$10
@@ -59375,24 +59375,24 @@ module \alu_branch0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 6 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 7 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 8 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 9 \nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 10 \op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 10 \br_op__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -59466,8 +59466,8 @@ module \alu_branch0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 11 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 11 \br_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -59480,23 +59480,23 @@ module \alu_branch0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 12 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 13 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 14 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 12 \br_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 13 \br_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 14 \br_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \br_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \br_op__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \br_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 18 \fast1$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 19 \fast2$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 input 20 \cr_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 21 \p_valid_i
@@ -59514,10 +59514,10 @@ module \alu_branch0
   wire width 1 \pipe_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_br_op__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -59591,8 +59591,8 @@ module \alu_branch0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_br_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -59605,32 +59605,32 @@ module \alu_branch0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_br_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_br_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_br_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_br_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_br_op__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_br_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \pipe_cr_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \pipe_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \pipe_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__cia$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_br_op__cia$4
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -59704,8 +59704,8 @@ module \alu_branch0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_br_op__insn_type$5
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -59718,29 +59718,29 @@ module \alu_branch0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__lk$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_br_op__fn_unit$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_br_op__insn$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_br_op__imm_data__imm$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_br_op__imm_data__imm_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_br_op__lk$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_br_op__is_32bit$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_fast1$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_fast2$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_nia_ok
   cell \pipe$19 \pipe
     connect \rst \rst
@@ -59748,28 +59748,28 @@ module \alu_branch0
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
-    connect \op__cia \pipe_op__cia
-    connect \op__insn_type \pipe_op__insn_type
-    connect \op__fn_unit \pipe_op__fn_unit
-    connect \op__insn \pipe_op__insn
-    connect \op__imm_data__imm \pipe_op__imm_data__imm
-    connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
-    connect \op__lk \pipe_op__lk
-    connect \op__is_32bit \pipe_op__is_32bit
+    connect \br_op__cia \pipe_br_op__cia
+    connect \br_op__insn_type \pipe_br_op__insn_type
+    connect \br_op__fn_unit \pipe_br_op__fn_unit
+    connect \br_op__insn \pipe_br_op__insn
+    connect \br_op__imm_data__imm \pipe_br_op__imm_data__imm
+    connect \br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm_ok
+    connect \br_op__lk \pipe_br_op__lk
+    connect \br_op__is_32bit \pipe_br_op__is_32bit
     connect \fast1 \pipe_fast1
     connect \fast2 \pipe_fast2
     connect \cr_a \pipe_cr_a
     connect \n_valid_o \pipe_n_valid_o
     connect \n_ready_i \pipe_n_ready_i
     connect \muxid$1 \pipe_muxid$3
-    connect \op__cia$2 \pipe_op__cia$4
-    connect \op__insn_type$3 \pipe_op__insn_type$5
-    connect \op__fn_unit$4 \pipe_op__fn_unit$6
-    connect \op__insn$5 \pipe_op__insn$7
-    connect \op__imm_data__imm$6 \pipe_op__imm_data__imm$8
-    connect \op__imm_data__imm_ok$7 \pipe_op__imm_data__imm_ok$9
-    connect \op__lk$8 \pipe_op__lk$10
-    connect \op__is_32bit$9 \pipe_op__is_32bit$11
+    connect \br_op__cia$2 \pipe_br_op__cia$4
+    connect \br_op__insn_type$3 \pipe_br_op__insn_type$5
+    connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6
+    connect \br_op__insn$5 \pipe_br_op__insn$7
+    connect \br_op__imm_data__imm$6 \pipe_br_op__imm_data__imm$8
+    connect \br_op__imm_data__imm_ok$7 \pipe_br_op__imm_data__imm_ok$9
+    connect \br_op__lk$8 \pipe_br_op__lk$10
+    connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11
     connect \fast1$10 \pipe_fast1$12
     connect \fast1_ok \pipe_fast1_ok
     connect \fast2$11 \pipe_fast2$13
@@ -59787,7 +59787,7 @@ module \alu_branch0
     assign \p_ready_o \pipe_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_2
     assign \pipe_muxid 2'00
@@ -59795,15 +59795,15 @@ module \alu_branch0
     sync init
   end
   process $group_3
-    assign \pipe_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_op__insn_type 7'0000000
-    assign \pipe_op__fn_unit 11'00000000000
-    assign \pipe_op__insn 32'00000000000000000000000000000000
-    assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_op__imm_data__imm_ok 1'0
-    assign \pipe_op__lk 1'0
-    assign \pipe_op__is_32bit 1'0
-    assign { \pipe_op__is_32bit \pipe_op__lk { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type \pipe_op__cia } { \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__insn \op__fn_unit \op__insn_type \op__cia }
+    assign \pipe_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_br_op__insn_type 7'0000000
+    assign \pipe_br_op__fn_unit 11'00000000000
+    assign \pipe_br_op__insn 32'00000000000000000000000000000000
+    assign \pipe_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_br_op__imm_data__imm_ok 1'0
+    assign \pipe_br_op__lk 1'0
+    assign \pipe_br_op__is_32bit 1'0
+    assign { \pipe_br_op__is_32bit \pipe_br_op__lk { \pipe_br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm } \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia }
     sync init
   end
   process $group_11
@@ -59831,15 +59831,15 @@ module \alu_branch0
     assign \pipe_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$14
   process $group_16
     assign \muxid$14 2'00
     assign \muxid$14 \pipe_muxid$3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__cia$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \br_op__cia$15
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -59913,8 +59913,8 @@ module \alu_branch0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \br_op__insn_type$16
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -59927,28 +59927,28 @@ module \alu_branch0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__lk$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \br_op__fn_unit$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \br_op__insn$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \br_op__imm_data__imm$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__imm_data__imm_ok$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__lk$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \br_op__is_32bit$22
   process $group_17
-    assign \op__cia$15 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__insn_type$16 7'0000000
-    assign \op__fn_unit$17 11'00000000000
-    assign \op__insn$18 32'00000000000000000000000000000000
-    assign \op__imm_data__imm$19 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$20 1'0
-    assign \op__lk$21 1'0
-    assign \op__is_32bit$22 1'0
-    assign { \op__is_32bit$22 \op__lk$21 { \op__imm_data__imm_ok$20 \op__imm_data__imm$19 } \op__insn$18 \op__fn_unit$17 \op__insn_type$16 \op__cia$15 } { \pipe_op__is_32bit$11 \pipe_op__lk$10 { \pipe_op__imm_data__imm_ok$9 \pipe_op__imm_data__imm$8 } \pipe_op__insn$7 \pipe_op__fn_unit$6 \pipe_op__insn_type$5 \pipe_op__cia$4 }
+    assign \br_op__cia$15 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \br_op__insn_type$16 7'0000000
+    assign \br_op__fn_unit$17 11'00000000000
+    assign \br_op__insn$18 32'00000000000000000000000000000000
+    assign \br_op__imm_data__imm$19 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \br_op__imm_data__imm_ok$20 1'0
+    assign \br_op__lk$21 1'0
+    assign \br_op__is_32bit$22 1'0
+    assign { \br_op__is_32bit$22 \br_op__lk$21 { \br_op__imm_data__imm_ok$20 \br_op__imm_data__imm$19 } \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 { \pipe_br_op__imm_data__imm_ok$9 \pipe_br_op__imm_data__imm$8 } \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 }
     sync init
   end
   process $group_25
@@ -60993,8 +60993,8 @@ module \branch0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 2 \oper_i__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 2 \oper_i_alu_branch0__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -61068,8 +61068,8 @@ module \branch0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 3 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 3 \oper_i_alu_branch0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -61082,66 +61082,66 @@ module \branch0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 4 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 5 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 6 \oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \oper_i__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 10 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 4 \oper_i_alu_branch0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 5 \oper_i_alu_branch0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 6 \oper_i_alu_branch0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_alu_branch0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_alu_branch0__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_alu_branch0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 11 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 input 12 \rdmaskn
+  wire width 1 input 10 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 11 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 12 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 13 \rd__rel
+  wire width 3 output 13 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 14 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 3 input 14 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 4 input 15 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 16 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 17 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 18 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 19 \wr__rel
+  wire width 3 output 19 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 20 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 3 input 20 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 21 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 22 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 23 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 24 \nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 25 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 26 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 27 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 26 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 27 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_branch0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_branch0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_branch0_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_branch0_fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_branch0_nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_branch0_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_branch0_br_op__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -61215,8 +61215,8 @@ module \branch0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_branch0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_branch0_br_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -61229,23 +61229,23 @@ module \branch0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_branch0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_branch0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_branch0_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_branch0_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_branch0_op__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_branch0_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_branch0_br_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_branch0_br_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_branch0_br_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_branch0_br_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_branch0_br_op__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_branch0_br_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_branch0_fast1$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_branch0_fast2$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 4 \alu_branch0_cr_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_branch0_p_valid_i
@@ -61262,14 +61262,14 @@ module \branch0
     connect \fast1 \alu_branch0_fast1
     connect \fast2 \alu_branch0_fast2
     connect \nia \alu_branch0_nia
-    connect \op__cia \alu_branch0_op__cia
-    connect \op__insn_type \alu_branch0_op__insn_type
-    connect \op__fn_unit \alu_branch0_op__fn_unit
-    connect \op__insn \alu_branch0_op__insn
-    connect \op__imm_data__imm \alu_branch0_op__imm_data__imm
-    connect \op__imm_data__imm_ok \alu_branch0_op__imm_data__imm_ok
-    connect \op__lk \alu_branch0_op__lk
-    connect \op__is_32bit \alu_branch0_op__is_32bit
+    connect \br_op__cia \alu_branch0_br_op__cia
+    connect \br_op__insn_type \alu_branch0_br_op__insn_type
+    connect \br_op__fn_unit \alu_branch0_br_op__fn_unit
+    connect \br_op__insn \alu_branch0_br_op__insn
+    connect \br_op__imm_data__imm \alu_branch0_br_op__imm_data__imm
+    connect \br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm_ok
+    connect \br_op__lk \alu_branch0_br_op__lk
+    connect \br_op__is_32bit \alu_branch0_br_op__is_32bit
     connect \fast1$1 \alu_branch0_fast1$1
     connect \fast2$2 \alu_branch0_fast2$2
     connect \cr_a \alu_branch0_cr_a
@@ -61378,36 +61378,36 @@ module \branch0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 3 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $6
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 3 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -61415,10 +61415,10 @@ module \branch0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A $6
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -61426,9 +61426,9 @@ module \branch0
     connect \A $8
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61444,9 +61444,9 @@ module \branch0
     assign \all_rd $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -61456,11 +61456,11 @@ module \branch0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61468,9 +61468,9 @@ module \branch0
     connect \A \all_rd_dly
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61486,16 +61486,16 @@ module \branch0
     assign \all_rd_pulse $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_branch0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -61505,11 +61505,11 @@ module \branch0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61517,9 +61517,9 @@ module \branch0
     connect \A \alu_done_dly
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61535,28 +61535,28 @@ module \branch0
     assign \alu_pulse $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 3 \alu_pulsem
   process $group_6
     assign \alu_pulsem 3'000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 3 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $21
   end
   process $group_7
@@ -61572,38 +61572,38 @@ module \branch0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 3 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 3 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $25
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -61611,7 +61611,7 @@ module \branch0
     connect \A $27
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61619,39 +61619,39 @@ module \branch0
     connect \A $24
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $23
     connect \Y $31
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $31
+    assign \cu_done_o 1'0
+    assign \cu_done_o $31
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -61659,9 +61659,9 @@ module \branch0
     connect \A \prev_wr_go
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61677,11 +61677,11 @@ module \branch0
     assign \wr_any $37
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61689,9 +61689,9 @@ module \branch0
     connect \A \alu_branch0_n_ready_i
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61702,9 +61702,9 @@ module \branch0
     connect \B $39
     connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 3 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -61712,12 +61712,12 @@ module \branch0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -61728,9 +61728,9 @@ module \branch0
     connect \B 1'0
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61741,22 +61741,22 @@ module \branch0
     connect \B $45
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61767,9 +61767,9 @@ module \branch0
     connect \B \alu_branch0_n_ready_i
     connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61780,9 +61780,9 @@ module \branch0
     connect \B \alu_branch0_n_valid_o
     connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61790,25 +61790,25 @@ module \branch0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $53
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $55
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $47
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $55 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61816,7 +61816,7 @@ module \branch0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $57
   end
   process $group_11
@@ -61824,19 +61824,19 @@ module \branch0
     assign \reset $57
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $59
   end
   process $group_12
@@ -61844,19 +61844,19 @@ module \branch0
     assign \rst_r $59
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 3 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 3 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $61
   end
   process $group_13
@@ -61864,19 +61864,19 @@ module \branch0
     assign \reset_w $61
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 3 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 3 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $63
   end
   process $group_14
@@ -61886,12 +61886,12 @@ module \branch0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -61899,7 +61899,7 @@ module \branch0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_branch0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $65
   end
   process $group_16
@@ -61927,7 +61927,7 @@ module \branch0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -61953,7 +61953,7 @@ module \branch0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -61977,9 +61977,9 @@ module \branch0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 3 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -61987,7 +61987,7 @@ module \branch0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $67
   end
   process $group_23
@@ -61995,9 +61995,9 @@ module \branch0
     assign \req_l_s_req $67
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 3 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -62013,7 +62013,7 @@ module \branch0
     assign \req_l_r_req $69
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -62088,7 +62088,7 @@ module \branch0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -62102,17 +62102,17 @@ module \branch0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \oper_l__cia
@@ -62152,8 +62152,8 @@ module \branch0
   cell $mux $72
     parameter \WIDTH 181
     connect \A { \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn \oper_l__fn_unit \oper_l__insn_type \oper_l__cia }
-    connect \B { \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn \oper_i__fn_unit \oper_i__insn_type \oper_i__cia }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia }
+    connect \S \cu_issue_i
     connect \Y $71
   end
   process $group_25
@@ -62178,10 +62178,10 @@ module \branch0
     assign \oper_l__lk$next \oper_l__lk
     assign \oper_l__is_32bit$next \oper_l__is_32bit
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next \oper_l__cia$next } { \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn \oper_i__fn_unit \oper_i__insn_type \oper_i__cia }
+        assign { \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next \oper_l__cia$next } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -62208,9 +62208,9 @@ module \branch0
       update \oper_l__lk \oper_l__lk$next
       update \oper_l__is_32bit \oper_l__is_32bit$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__fast1_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__fast1
@@ -62277,9 +62277,9 @@ module \branch0
       update \data_r0_l__fast1 \data_r0_l__fast1$next
       update \data_r0_l__fast1_ok \data_r0_l__fast1_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r1__fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__fast2_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r1_l__fast2
@@ -62346,9 +62346,9 @@ module \branch0
       update \data_r1_l__fast2 \data_r1_l__fast2$next
       update \data_r1_l__fast2_ok \data_r1_l__fast2_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r2__nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__nia_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r2_l__nia
@@ -62415,9 +62415,9 @@ module \branch0
       update \data_r2_l__nia \data_r2_l__nia$next
       update \data_r2_l__nia_ok \data_r2_l__nia_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $92
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62425,12 +62425,12 @@ module \branch0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__fast1_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $94
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62438,12 +62438,12 @@ module \branch0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__fast2_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $93
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $96
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62451,31 +62451,31 @@ module \branch0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__nia_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $95
   end
   process $group_53
-    assign \wrmask 3'000
-    assign \wrmask { $95 $93 $91 }
+    assign \cu_wrmask_o 3'000
+    assign \cu_wrmask_o { $95 $93 $91 }
     sync init
   end
   process $group_54
-    assign \alu_branch0_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_branch0_op__insn_type 7'0000000
-    assign \alu_branch0_op__fn_unit 11'00000000000
-    assign \alu_branch0_op__insn 32'00000000000000000000000000000000
-    assign \alu_branch0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_branch0_op__imm_data__imm_ok 1'0
-    assign \alu_branch0_op__lk 1'0
-    assign \alu_branch0_op__is_32bit 1'0
-    assign { \alu_branch0_op__is_32bit \alu_branch0_op__lk { \alu_branch0_op__imm_data__imm_ok \alu_branch0_op__imm_data__imm } \alu_branch0_op__insn \alu_branch0_op__fn_unit \alu_branch0_op__insn_type \alu_branch0_op__cia } { \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn \oper_r__fn_unit \oper_r__insn_type \oper_r__cia }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+    assign \alu_branch0_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_branch0_br_op__insn_type 7'0000000
+    assign \alu_branch0_br_op__fn_unit 11'00000000000
+    assign \alu_branch0_br_op__insn 32'00000000000000000000000000000000
+    assign \alu_branch0_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_branch0_br_op__imm_data__imm_ok 1'0
+    assign \alu_branch0_br_op__lk 1'0
+    assign \alu_branch0_br_op__is_32bit 1'0
+    assign { \alu_branch0_br_op__is_32bit \alu_branch0_br_op__lk { \alu_branch0_br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm } \alu_branch0_br_op__insn \alu_branch0_br_op__fn_unit \alu_branch0_br_op__insn_type \alu_branch0_br_op__cia } { \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn \oper_r__fn_unit \oper_r__insn_type \oper_r__cia }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $98
     parameter \WIDTH 1
     connect \A \src_l_q_src [1]
@@ -62488,11 +62488,11 @@ module \branch0
     assign \src_sel $97
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $100
     parameter \WIDTH 64
     connect \A \src2_i
@@ -62606,9 +62606,9 @@ module \branch0
     assign \alu_branch0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62642,9 +62642,9 @@ module \branch0
     assign \alu_branch0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62674,13 +62674,13 @@ module \branch0
     sync init
   end
   process $group_76
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -62688,12 +62688,12 @@ module \branch0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $111
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62701,9 +62701,9 @@ module \branch0
     connect \A \oper_r__imm_data__imm_ok
     connect \Y $113
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -62714,19 +62714,19 @@ module \branch0
     connect \B { 1'1 $113 1'1 }
     connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $117
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -62738,52 +62738,52 @@ module \branch0
     connect \Y $119
   end
   process $group_77
-    assign \rd__rel 3'000
-    assign \rd__rel $119
+    assign \cu_rd__rel_o 3'000
+    assign \cu_rd__rel_o $119
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $121
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $123
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $125
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -62794,9 +62794,9 @@ module \branch0
     connect \B { $121 $123 $125 }
     connect \Y $127
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -62804,78 +62804,78 @@ module \branch0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A $127
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $129
   end
   process $group_78
-    assign \wr__rel 3'000
-    assign \wr__rel $129
+    assign \cu_wr__rel_o 3'000
+    assign \cu_wr__rel_o $129
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $131
   end
   process $group_79
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $131 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__fast1_ok \data_r0__fast1 } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $133
   end
   process $group_80
     assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $133 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__fast2_ok \data_r1__fast2 } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $135
   end
   process $group_81
     assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $135 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__nia_ok \data_r2__nia } [63:0]
     end
@@ -62919,9 +62919,9 @@ module \n$31
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62975,9 +62975,9 @@ module \n$34
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -62997,7 +62997,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main"
 module \main$35
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -63072,8 +63072,8 @@ module \main$35
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \trap_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -63086,29 +63086,29 @@ module \main$35
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 3 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 4 \op__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 5 \op__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 input 7 \op__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 input 8 \op__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \trap_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 3 \trap_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 4 \trap_op__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 5 \trap_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \trap_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 input 7 \trap_op__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 input 8 \trap_op__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 9 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 10 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 11 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 12 \fast2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 13 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -63183,8 +63183,8 @@ module \main$35
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 14 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 14 \trap_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -63197,78 +63197,78 @@ module \main$35
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 15 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 16 \op__insn$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 17 \op__msr$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 18 \op__cia$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 19 \op__is_32bit$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 output 20 \op__traptype$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 output 21 \op__trapaddr$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 15 \trap_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 16 \trap_op__insn$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 17 \trap_op__msr$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 18 \trap_op__cia$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 19 \trap_op__is_32bit$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 output 20 \trap_op__traptype$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 output 21 \trap_op__trapaddr$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 22 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 23 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 24 \fast1$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 25 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 26 \fast2$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 28 \nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 30 \msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 31 \msr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133"
   wire width 5 \to
   process $group_0
     assign \to 5'00000
-    assign \to { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] }
+    assign \to { \trap_op__insn [25] \trap_op__insn [24] \trap_op__insn [23] \trap_op__insn [22] \trap_op__insn [21] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
   wire width 64 \a_s
   process $group_1
     assign \a_s 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
-    switch { \op__is_32bit }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
+    switch { \trap_op__is_32bit }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
       case 1'1
         assign \a_s { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
       case
         assign \a_s \ra
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138"
   wire width 64 \b_s
   process $group_2
     assign \b_s 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
-    switch { \op__is_32bit }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
+    switch { \trap_op__is_32bit }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
       case 1'1
         assign \b_s { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
       case
         assign \b_s \rb
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:140"
   wire width 64 \a
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
   wire width 64 $12
@@ -63282,18 +63282,18 @@ module \main$35
   end
   process $group_3
     assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
-    switch { \op__is_32bit }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
+    switch { \trap_op__is_32bit }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
       case 1'1
         assign \a $12
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
       case
         assign \a \ra
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141"
   wire width 64 \b
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
   wire width 64 $14
@@ -63307,22 +63307,22 @@ module \main$35
   end
   process $group_4
     assign \b 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
-    switch { \op__is_32bit }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
+    switch { \trap_op__is_32bit }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
       case 1'1
         assign \b $14
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
       case
         assign \b \rb
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156"
   wire width 1 \lt_s
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162"
   wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162"
   cell $lt $17
     parameter \A_SIGNED 1
     parameter \A_WIDTH 64
@@ -63338,11 +63338,11 @@ module \main$35
     assign \lt_s $16
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
   wire width 1 \gt_s
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
   wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
   cell $gt $19
     parameter \A_SIGNED 1
     parameter \A_WIDTH 64
@@ -63358,11 +63358,11 @@ module \main$35
     assign \gt_s $18
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:146"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158"
   wire width 1 \lt_u
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:152"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
   wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:152"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
   cell $lt $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -63378,11 +63378,11 @@ module \main$35
     assign \lt_u $20
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159"
   wire width 1 \gt_u
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165"
   wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165"
   cell $gt $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -63398,11 +63398,11 @@ module \main$35
     assign \gt_u $22
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:148"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160"
   wire width 1 \equal
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166"
   cell $eq $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -63418,20 +63418,20 @@ module \main$35
     assign \equal $24
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:170"
   wire width 5 \trap_bits
   process $group_10
     assign \trap_bits 5'00000
     assign \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175"
   wire width 1 \should_trap
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   wire width 5 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -63442,7 +63442,7 @@ module \main$35
     connect \B \to
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   cell $reduce_or $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -63450,19 +63450,19 @@ module \main$35
     connect \A $27
     connect \Y $26
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   cell $reduce_or $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \op__traptype
+    connect \A \trap_op__traptype
     connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176"
   cell $or $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -63478,22 +63478,22 @@ module \main$35
     assign \should_trap $32
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188"
   wire width 64 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188"
   wire width 20 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188"
   cell $sshl $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 13
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 20
-    connect \A \op__trapaddr
+    connect \A \trap_op__trapaddr
     connect \B 3'100
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188"
   cell $pos $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
@@ -63503,28 +63503,28 @@ module \main$35
   end
   process $group_12
     assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
         switch { \should_trap }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
           case 1'1
             assign \nia $34
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \nia { { {  } \fast1 [63:2] } 2'00 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
         assign \nia 64'0000000000000000000000000000000000000000000000000000110000000000
@@ -63533,73 +63533,73 @@ module \main$35
   end
   process $group_13
     assign \nia_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
         switch { \should_trap }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
           case 1'1
             assign \nia_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \nia_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
         assign \nia_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:254"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:301"
   wire width 65 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:254"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:301"
   wire width 65 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:254"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:301"
   cell $add $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 65
-    connect \A \op__cia
+    connect \A \trap_op__cia
     connect \B 3'100
     connect \Y $39
   end
   connect $38 $39
   process $group_14
     assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
         switch { \should_trap }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
           case 1'1
-            assign \fast1$10 \op__cia
+            assign \fast1$10 \trap_op__cia
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
         assign \fast1$10 $38 [63:0]
@@ -63608,58 +63608,58 @@ module \main$35
   end
   process $group_15
     assign \fast1_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
         switch { \should_trap }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
           case 1'1
             assign \fast1_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
         assign \fast1_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
   cell $eq $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \op__traptype
+    connect \A \trap_op__traptype
     connect \B 1'0
     connect \Y $41
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
   wire width 1 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192"
   wire width 5 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192"
   cell $and $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 5
-    connect \A \op__traptype
+    connect \A \trap_op__traptype
     connect \B 2'10
     connect \Y $44
   end
@@ -63673,16 +63673,16 @@ module \main$35
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194"
   wire width 5 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194"
   cell $and $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 5
-    connect \A \op__traptype
+    connect \A \trap_op__traptype
     connect \B 1'1
     connect \Y $48
   end
@@ -63696,16 +63696,16 @@ module \main$35
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196"
   wire width 5 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196"
   cell $and $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 5
-    connect \A \op__traptype
+    connect \A \trap_op__traptype
     connect \B 4'1000
     connect \Y $52
   end
@@ -63719,16 +63719,16 @@ module \main$35
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198"
   wire width 5 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198"
   cell $and $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \op__traptype
+    connect \A \trap_op__traptype
     connect \B 5'10000
     connect \Y $56
   end
@@ -63742,107 +63742,107 @@ module \main$35
   end
   process $group_16
     assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
         switch { \should_trap }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
           case 1'1
             assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
-            assign \fast2$11 [15:0] \op__msr [15:0]
-            assign \fast2$11 [26:22] \op__msr [26:22]
-            assign \fast2$11 [63:31] \op__msr [63:31]
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
+            assign \fast2$11 [15:0] \trap_op__msr [15:0]
+            assign \fast2$11 [26:22] \trap_op__msr [26:22]
+            assign \fast2$11 [63:31] \trap_op__msr [63:31]
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
             switch { $41 }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189"
               case 1'1
                 assign \fast2$11 [17] 1'1
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192"
             switch { $43 }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192"
               case 1'1
                 assign \fast2$11 [18] 1'1
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194"
             switch { $47 }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194"
               case 1'1
                 assign \fast2$11 [20] 1'1
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196"
             switch { $51 }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196"
               case 1'1
                 assign \fast2$11 [16] 1'1
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198"
             switch { $55 }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198"
               case 1'1
                 assign \fast2$11 [19] 1'1
             end
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
         assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \fast2$11 [15:0] \op__msr [15:0]
-        assign \fast2$11 [26:22] \op__msr [26:22]
-        assign \fast2$11 [63:31] \op__msr [63:31]
+        assign \fast2$11 [15:0] \trap_op__msr [15:0]
+        assign \fast2$11 [26:22] \trap_op__msr [26:22]
+        assign \fast2$11 [63:31] \trap_op__msr [63:31]
     end
     sync init
   end
   process $group_17
     assign \fast2_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
         switch { \should_trap }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
           case 1'1
             assign \fast2_ok 1'1
             assign \fast2_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
         assign \fast2_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 65 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   cell $pos $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 65
-    connect \A \op__msr
+    connect \A \trap_op__msr
     connect \Y $59
   end
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
@@ -63852,49 +63852,88 @@ module \main$35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A { \op__insn [22] \op__insn [21] }
+    connect \A { \trap_op__insn [22] \trap_op__insn [21] }
     connect \Y $61
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219"
   wire width 1 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219"
   cell $eq $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \trap_op__insn_type
     connect \B 7'1001000
     connect \Y $63
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225"
   wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
-  cell $not $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225"
+  cell $eq $66
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \op__msr [60]
+    connect \A \trap_op__msr [34:32]
+    connect \B 3'010
     connect \Y $65
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:242"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226"
   wire width 1 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:242"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226"
   cell $eq $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \op__msr [34:32]
-    connect \B 3'010
+    connect \A \ra [34:32]
+    connect \B 3'000
     connect \Y $67
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226"
   wire width 1 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
-  cell $eq $70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226"
+  cell $and $70
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $65
+    connect \B $67
+    connect \Y $69
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
+  wire width 1 $71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
+  cell $not $72
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \trap_op__msr [60]
+    connect \Y $71
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281"
+  cell $eq $74
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \trap_op__msr [34:32]
+    connect \B 3'010
+    connect \Y $73
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
+  wire width 1 $75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
+  cell $eq $76
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -63902,34 +63941,34 @@ module \main$35
     parameter \Y_WIDTH 1
     connect \A \fast2 [34:32]
     connect \B 3'000
-    connect \Y $69
+    connect \Y $75
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
-  wire width 1 $71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
-  cell $and $72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
+  wire width 1 $77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
+  cell $and $78
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $67
-    connect \B $69
-    connect \Y $71
+    connect \A $73
+    connect \B $75
+    connect \Y $77
   end
   process $group_18
     assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \msr_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
         switch { \should_trap }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186"
           case 1'1
-            assign \msr \op__msr
+            assign \msr \trap_op__msr
             assign \msr [63] 1'1
             assign \msr [15] 1'0
             assign \msr [14] 1'0
@@ -63937,28 +63976,44 @@ module \main$35
             assign \msr [4] 1'0
             assign \msr [1] 1'0
             assign \msr [0] 1'1
+            assign \msr [11] 1'0
+            assign \msr [8] 1'0
+            assign \msr [23] 1'0
+            assign \msr [32] 1'0
+            assign \msr [25] 1'0
+            assign \msr [13] 1'0
+            assign \msr [3] 1'0
+            assign \msr [10] 1'0
+            assign \msr [9] 1'0
+            assign \msr [58] 1'0
             assign \msr_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
         assign { \msr_ok \msr } $59
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212"
         switch { $61 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212"
           case 1'1
             assign \msr [1] \ra [1]
             assign \msr [15] \ra [15]
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:216"
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219"
             switch { $63 }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219"
               case 1'1
                 assign \msr [11:1] \ra [11:1]
                 assign \msr [59:13] \ra [59:13]
                 assign \msr [63:61] \ra [63:61]
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205"
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226"
+                switch { $69 }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226"
+                  case 1'1
+                    assign \msr [34:32] \trap_op__msr [34:32]
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:229"
               case
                 assign \msr [11:1] \ra [11:1]
                 assign \msr [31:13] \ra [31:13]
@@ -63972,19 +64027,35 @@ module \main$35
                 assign \msr [4] 1'1
             end
         end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
+        switch { $71 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241"
+          case 1'1
+            assign \msr [60] \trap_op__msr [60]
+            assign \msr [12] \trap_op__msr [12]
+        end
         switch { }
           case
             assign \msr_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \msr [15:0] \fast2 [15:0]
         assign \msr [26:22] \fast2 [26:22]
         assign \msr [63:31] \fast2 [63:31]
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:269"
+        switch { \trap_op__msr [60] }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:269"
+          case 1'1
+            assign { \msr_ok \msr } [12] \fast2 [12]
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:271"
+          case
+            assign { \msr_ok \msr } [12] \trap_op__msr [12]
+        end
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48"
         switch { \msr [14] }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48"
@@ -63993,27 +64064,20 @@ module \main$35
             assign \msr [5] 1'1
             assign \msr [4] 1'1
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
-        switch { $65 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
+        switch { $77 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282"
           case 1'1
-            assign \msr [60] \op__msr [60]
-            assign \msr [12] \op__msr [12]
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
-        switch { $71 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
-          case 1'1
-            assign \msr [34:32] \op__msr [34:32]
+            assign \msr [34:32] \trap_op__msr [34:32]
         end
         switch { }
           case
             assign \msr_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
-        assign \msr \op__msr
+        assign \msr \trap_op__msr
         assign \msr [63] 1'1
         assign \msr [15] 1'0
         assign \msr [14] 1'0
@@ -64021,28 +64085,38 @@ module \main$35
         assign \msr [4] 1'0
         assign \msr [1] 1'0
         assign \msr [0] 1'1
+        assign \msr [11] 1'0
+        assign \msr [8] 1'0
+        assign \msr [23] 1'0
+        assign \msr [32] 1'0
+        assign \msr [25] 1'0
+        assign \msr [13] 1'0
+        assign \msr [3] 1'0
+        assign \msr [10] 1'0
+        assign \msr [9] 1'0
+        assign \msr [58] 1'0
         assign \msr_ok 1'1
     end
     sync init
   end
   process $group_20
     assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
-        assign \o \op__msr
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+        assign \o \trap_op__msr
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
     end
@@ -64050,22 +64124,22 @@ module \main$35
   end
   process $group_21
     assign \o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+    switch \trap_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184"
       attribute \nmigen.decoding "OP_TRAP/63"
       case 7'0111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208"
       attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
       case 7'1001000, 7'1001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250"
       attribute \nmigen.decoding "OP_MFMSR/71"
       case 7'1000111
         assign \o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290"
       attribute \nmigen.decoding "OP_SC/73"
       case 7'1001001
     end
@@ -64077,15 +64151,15 @@ module \main$35
     sync init
   end
   process $group_23
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__insn$4 32'00000000000000000000000000000000
-    assign \op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__is_32bit$7 1'0
-    assign \op__traptype$8 5'00000
-    assign \op__trapaddr$9 13'0000000000000
-    assign { \op__trapaddr$9 \op__traptype$8 \op__is_32bit$7 \op__cia$6 \op__msr$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__trapaddr \op__traptype \op__is_32bit \op__cia \op__msr \op__insn \op__fn_unit \op__insn_type }
+    assign \trap_op__insn_type$2 7'0000000
+    assign \trap_op__fn_unit$3 11'00000000000
+    assign \trap_op__insn$4 32'00000000000000000000000000000000
+    assign \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \trap_op__is_32bit$7 1'0
+    assign \trap_op__traptype$8 5'00000
+    assign \trap_op__trapaddr$9 13'0000000000000
+    assign { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
     sync init
   end
 end
@@ -64100,7 +64174,7 @@ module \pipe$32
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -64175,8 +64249,8 @@ module \pipe$32
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \trap_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -64189,35 +64263,35 @@ module \pipe$32
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 7 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 8 \op__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 9 \op__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 input 11 \op__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 input 12 \op__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \trap_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 7 \trap_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 8 \trap_op__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 9 \trap_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \trap_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 input 11 \trap_op__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 input 12 \trap_op__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 13 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 14 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 15 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 16 \fast2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 17 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 18 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 19 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -64292,10 +64366,10 @@ module \pipe$32
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 20 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 20 \trap_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \trap_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -64308,73 +64382,73 @@ module \pipe$32
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 21 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 22 \op__insn$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 23 \op__msr$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__msr$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 24 \op__cia$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__cia$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__is_32bit$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 output 26 \op__traptype$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \op__traptype$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 output 27 \op__trapaddr$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \op__trapaddr$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 21 \trap_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \trap_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 22 \trap_op__insn$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \trap_op__insn$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 23 \trap_op__msr$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \trap_op__msr$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \trap_op__cia$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \trap_op__cia$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \trap_op__is_32bit$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \trap_op__is_32bit$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 output 26 \trap_op__traptype$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \trap_op__traptype$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 output 27 \trap_op__trapaddr$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \trap_op__trapaddr$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 28 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 30 \fast1$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast1$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 31 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast1_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 32 \fast2$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast2$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast2_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 34 \nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \nia$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 35 \nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \nia_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 36 \msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \msr$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 37 \msr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \msr_ok$next
   cell \p$33 \p
     connect \p_valid_i \p_valid_i
@@ -64384,7 +64458,7 @@ module \pipe$32
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -64459,8 +64533,8 @@ module \pipe$32
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_trap_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -64473,29 +64547,29 @@ module \pipe$32
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \main_op__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \main_op__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_trap_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_trap_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_trap_op__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_trap_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_trap_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \main_trap_op__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \main_trap_op__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_fast2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid$12
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -64570,8 +64644,8 @@ module \pipe$32
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_trap_op__insn_type$13
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -64584,63 +64658,63 @@ module \pipe$32
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__msr$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__cia$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \main_op__traptype$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \main_op__trapaddr$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_trap_op__fn_unit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_trap_op__insn$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_trap_op__msr$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_trap_op__cia$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_trap_op__is_32bit$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \main_trap_op__traptype$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \main_trap_op__trapaddr$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_fast1$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_fast2$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_msr_ok
   cell \main$35 \main
     connect \muxid \main_muxid
-    connect \op__insn_type \main_op__insn_type
-    connect \op__fn_unit \main_op__fn_unit
-    connect \op__insn \main_op__insn
-    connect \op__msr \main_op__msr
-    connect \op__cia \main_op__cia
-    connect \op__is_32bit \main_op__is_32bit
-    connect \op__traptype \main_op__traptype
-    connect \op__trapaddr \main_op__trapaddr
+    connect \trap_op__insn_type \main_trap_op__insn_type
+    connect \trap_op__fn_unit \main_trap_op__fn_unit
+    connect \trap_op__insn \main_trap_op__insn
+    connect \trap_op__msr \main_trap_op__msr
+    connect \trap_op__cia \main_trap_op__cia
+    connect \trap_op__is_32bit \main_trap_op__is_32bit
+    connect \trap_op__traptype \main_trap_op__traptype
+    connect \trap_op__trapaddr \main_trap_op__trapaddr
     connect \ra \main_ra
     connect \rb \main_rb
     connect \fast1 \main_fast1
     connect \fast2 \main_fast2
     connect \muxid$1 \main_muxid$12
-    connect \op__insn_type$2 \main_op__insn_type$13
-    connect \op__fn_unit$3 \main_op__fn_unit$14
-    connect \op__insn$4 \main_op__insn$15
-    connect \op__msr$5 \main_op__msr$16
-    connect \op__cia$6 \main_op__cia$17
-    connect \op__is_32bit$7 \main_op__is_32bit$18
-    connect \op__traptype$8 \main_op__traptype$19
-    connect \op__trapaddr$9 \main_op__trapaddr$20
+    connect \trap_op__insn_type$2 \main_trap_op__insn_type$13
+    connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14
+    connect \trap_op__insn$4 \main_trap_op__insn$15
+    connect \trap_op__msr$5 \main_trap_op__msr$16
+    connect \trap_op__cia$6 \main_trap_op__cia$17
+    connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18
+    connect \trap_op__traptype$8 \main_trap_op__traptype$19
+    connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20
     connect \o \main_o
     connect \o_ok \main_o_ok
     connect \fast1$10 \main_fast1$21
@@ -64658,15 +64732,15 @@ module \pipe$32
     sync init
   end
   process $group_1
-    assign \main_op__insn_type 7'0000000
-    assign \main_op__fn_unit 11'00000000000
-    assign \main_op__insn 32'00000000000000000000000000000000
-    assign \main_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_op__is_32bit 1'0
-    assign \main_op__traptype 5'00000
-    assign \main_op__trapaddr 13'0000000000000
-    assign { \main_op__trapaddr \main_op__traptype \main_op__is_32bit \main_op__cia \main_op__msr \main_op__insn \main_op__fn_unit \main_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__cia \op__msr \op__insn \op__fn_unit \op__insn_type }
+    assign \main_trap_op__insn_type 7'0000000
+    assign \main_trap_op__fn_unit 11'00000000000
+    assign \main_trap_op__insn 32'00000000000000000000000000000000
+    assign \main_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_trap_op__is_32bit 1'0
+    assign \main_trap_op__traptype 5'00000
+    assign \main_trap_op__trapaddr 13'0000000000000
+    assign { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
     sync init
   end
   process $group_9
@@ -64723,7 +64797,7 @@ module \pipe$32
     assign \p_valid_i_p_ready_o $24
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$26
   process $group_16
     assign \muxid$26 2'00
@@ -64803,8 +64877,8 @@ module \pipe$32
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \trap_op__insn_type$27
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -64817,35 +64891,35 @@ module \pipe$32
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__msr$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__cia$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \op__traptype$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \op__trapaddr$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \trap_op__fn_unit$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \trap_op__insn$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \trap_op__msr$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \trap_op__cia$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \trap_op__is_32bit$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \trap_op__traptype$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \trap_op__trapaddr$34
   process $group_17
-    assign \op__insn_type$27 7'0000000
-    assign \op__fn_unit$28 11'00000000000
-    assign \op__insn$29 32'00000000000000000000000000000000
-    assign \op__msr$30 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__cia$31 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__is_32bit$32 1'0
-    assign \op__traptype$33 5'00000
-    assign \op__trapaddr$34 13'0000000000000
-    assign { \op__trapaddr$34 \op__traptype$33 \op__is_32bit$32 \op__cia$31 \op__msr$30 \op__insn$29 \op__fn_unit$28 \op__insn_type$27 } { \main_op__trapaddr$20 \main_op__traptype$19 \main_op__is_32bit$18 \main_op__cia$17 \main_op__msr$16 \main_op__insn$15 \main_op__fn_unit$14 \main_op__insn_type$13 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+    assign \trap_op__insn_type$27 7'0000000
+    assign \trap_op__fn_unit$28 11'00000000000
+    assign \trap_op__insn$29 32'00000000000000000000000000000000
+    assign \trap_op__msr$30 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \trap_op__cia$31 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \trap_op__is_32bit$32 1'0
+    assign \trap_op__traptype$33 5'00000
+    assign \trap_op__trapaddr$34 13'0000000000000
+    assign { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$36
   process $group_25
     assign \o$35 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -64853,9 +64927,9 @@ module \pipe$32
     assign { \o_ok$36 \o$35 } { \main_o_ok \main_o }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast1$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast1_ok$38
   process $group_27
     assign \fast1$37 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -64863,9 +64937,9 @@ module \pipe$32
     assign { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast2$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast2_ok$40
   process $group_29
     assign \fast2$39 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -64873,9 +64947,9 @@ module \pipe$32
     assign { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \nia$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \nia_ok$42
   process $group_31
     assign \nia$41 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -64883,9 +64957,9 @@ module \pipe$32
     assign { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \msr$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \msr_ok$44
   process $group_33
     assign \msr$43 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -64935,41 +65009,41 @@ module \pipe$32
       update \muxid$1 \muxid$1$next
   end
   process $group_37
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__insn$4$next \op__insn$4
-    assign \op__msr$5$next \op__msr$5
-    assign \op__cia$6$next \op__cia$6
-    assign \op__is_32bit$7$next \op__is_32bit$7
-    assign \op__traptype$8$next \op__traptype$8
-    assign \op__trapaddr$9$next \op__trapaddr$9
+    assign \trap_op__insn_type$2$next \trap_op__insn_type$2
+    assign \trap_op__fn_unit$3$next \trap_op__fn_unit$3
+    assign \trap_op__insn$4$next \trap_op__insn$4
+    assign \trap_op__msr$5$next \trap_op__msr$5
+    assign \trap_op__cia$6$next \trap_op__cia$6
+    assign \trap_op__is_32bit$7$next \trap_op__is_32bit$7
+    assign \trap_op__traptype$8$next \trap_op__traptype$8
+    assign \trap_op__trapaddr$9$next \trap_op__trapaddr$9
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__trapaddr$9$next \op__traptype$8$next \op__is_32bit$7$next \op__cia$6$next \op__msr$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$34 \op__traptype$33 \op__is_32bit$32 \op__cia$31 \op__msr$30 \op__insn$29 \op__fn_unit$28 \op__insn_type$27 }
+        assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__trapaddr$9$next \op__traptype$8$next \op__is_32bit$7$next \op__cia$6$next \op__msr$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$34 \op__traptype$33 \op__is_32bit$32 \op__cia$31 \op__msr$30 \op__insn$29 \op__fn_unit$28 \op__insn_type$27 }
+        assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 }
     end
     sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__insn$4 32'00000000000000000000000000000000
-      update \op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__is_32bit$7 1'0
-      update \op__traptype$8 5'00000
-      update \op__trapaddr$9 13'0000000000000
+      update \trap_op__insn_type$2 7'0000000
+      update \trap_op__fn_unit$3 11'00000000000
+      update \trap_op__insn$4 32'00000000000000000000000000000000
+      update \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \trap_op__is_32bit$7 1'0
+      update \trap_op__traptype$8 5'00000
+      update \trap_op__trapaddr$9 13'0000000000000
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__insn$4 \op__insn$4$next
-      update \op__msr$5 \op__msr$5$next
-      update \op__cia$6 \op__cia$6$next
-      update \op__is_32bit$7 \op__is_32bit$7$next
-      update \op__traptype$8 \op__traptype$8$next
-      update \op__trapaddr$9 \op__trapaddr$9$next
+      update \trap_op__insn_type$2 \trap_op__insn_type$2$next
+      update \trap_op__fn_unit$3 \trap_op__fn_unit$3$next
+      update \trap_op__insn$4 \trap_op__insn$4$next
+      update \trap_op__msr$5 \trap_op__msr$5$next
+      update \trap_op__cia$6 \trap_op__cia$6$next
+      update \trap_op__is_32bit$7 \trap_op__is_32bit$7$next
+      update \trap_op__traptype$8 \trap_op__traptype$8$next
+      update \trap_op__trapaddr$9 \trap_op__trapaddr$9$next
   end
   process $group_45
     assign \o$next \o
@@ -65109,29 +65183,29 @@ module \alu_trap0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 6 \msr_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 7 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 8 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 9 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 10 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 11 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 12 \nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 13 \msr
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -65206,8 +65280,8 @@ module \alu_trap0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 14 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 14 \trap_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -65220,27 +65294,27 @@ module \alu_trap0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 15 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 16 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 17 \op__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 18 \op__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 input 20 \op__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 input 21 \op__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 15 \trap_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \trap_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 17 \trap_op__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 18 \trap_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \trap_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 input 20 \trap_op__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 input 21 \trap_op__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 22 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 23 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 24 \fast1$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 25 \fast2$2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 26 \p_valid_i
@@ -65258,7 +65332,7 @@ module \alu_trap0
   wire width 1 \pipe_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -65333,8 +65407,8 @@ module \alu_trap0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_trap_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -65347,33 +65421,33 @@ module \alu_trap0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \pipe_op__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \pipe_op__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_trap_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_trap_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_trap_op__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_trap_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_trap_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \pipe_trap_op__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \pipe_trap_op__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_fast2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \pipe_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \pipe_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid$3
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -65448,8 +65522,8 @@ module \alu_trap0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_trap_op__insn_type$4
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -65462,39 +65536,39 @@ module \alu_trap0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__msr$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__cia$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \pipe_op__traptype$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \pipe_op__trapaddr$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_trap_op__fn_unit$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_trap_op__insn$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_trap_op__msr$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_trap_op__cia$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_trap_op__is_32bit$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \pipe_trap_op__traptype$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \pipe_trap_op__trapaddr$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_fast1$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_fast2$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_msr_ok
   cell \pipe$32 \pipe
     connect \rst \rst
@@ -65502,14 +65576,14 @@ module \alu_trap0
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
-    connect \op__insn_type \pipe_op__insn_type
-    connect \op__fn_unit \pipe_op__fn_unit
-    connect \op__insn \pipe_op__insn
-    connect \op__msr \pipe_op__msr
-    connect \op__cia \pipe_op__cia
-    connect \op__is_32bit \pipe_op__is_32bit
-    connect \op__traptype \pipe_op__traptype
-    connect \op__trapaddr \pipe_op__trapaddr
+    connect \trap_op__insn_type \pipe_trap_op__insn_type
+    connect \trap_op__fn_unit \pipe_trap_op__fn_unit
+    connect \trap_op__insn \pipe_trap_op__insn
+    connect \trap_op__msr \pipe_trap_op__msr
+    connect \trap_op__cia \pipe_trap_op__cia
+    connect \trap_op__is_32bit \pipe_trap_op__is_32bit
+    connect \trap_op__traptype \pipe_trap_op__traptype
+    connect \trap_op__trapaddr \pipe_trap_op__trapaddr
     connect \ra \pipe_ra
     connect \rb \pipe_rb
     connect \fast1 \pipe_fast1
@@ -65517,14 +65591,14 @@ module \alu_trap0
     connect \n_valid_o \pipe_n_valid_o
     connect \n_ready_i \pipe_n_ready_i
     connect \muxid$1 \pipe_muxid$3
-    connect \op__insn_type$2 \pipe_op__insn_type$4
-    connect \op__fn_unit$3 \pipe_op__fn_unit$5
-    connect \op__insn$4 \pipe_op__insn$6
-    connect \op__msr$5 \pipe_op__msr$7
-    connect \op__cia$6 \pipe_op__cia$8
-    connect \op__is_32bit$7 \pipe_op__is_32bit$9
-    connect \op__traptype$8 \pipe_op__traptype$10
-    connect \op__trapaddr$9 \pipe_op__trapaddr$11
+    connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4
+    connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5
+    connect \trap_op__insn$4 \pipe_trap_op__insn$6
+    connect \trap_op__msr$5 \pipe_trap_op__msr$7
+    connect \trap_op__cia$6 \pipe_trap_op__cia$8
+    connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9
+    connect \trap_op__traptype$8 \pipe_trap_op__traptype$10
+    connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11
     connect \o \pipe_o
     connect \o_ok \pipe_o_ok
     connect \fast1$10 \pipe_fast1$12
@@ -65546,7 +65620,7 @@ module \alu_trap0
     assign \p_ready_o \pipe_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_2
     assign \pipe_muxid 2'00
@@ -65554,15 +65628,15 @@ module \alu_trap0
     sync init
   end
   process $group_3
-    assign \pipe_op__insn_type 7'0000000
-    assign \pipe_op__fn_unit 11'00000000000
-    assign \pipe_op__insn 32'00000000000000000000000000000000
-    assign \pipe_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_op__is_32bit 1'0
-    assign \pipe_op__traptype 5'00000
-    assign \pipe_op__trapaddr 13'0000000000000
-    assign { \pipe_op__trapaddr \pipe_op__traptype \pipe_op__is_32bit \pipe_op__cia \pipe_op__msr \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__cia \op__msr \op__insn \op__fn_unit \op__insn_type }
+    assign \pipe_trap_op__insn_type 7'0000000
+    assign \pipe_trap_op__fn_unit 11'00000000000
+    assign \pipe_trap_op__insn 32'00000000000000000000000000000000
+    assign \pipe_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_trap_op__is_32bit 1'0
+    assign \pipe_trap_op__traptype 5'00000
+    assign \pipe_trap_op__trapaddr 13'0000000000000
+    assign { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type }
     sync init
   end
   process $group_11
@@ -65595,7 +65669,7 @@ module \alu_trap0
     assign \pipe_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$14
   process $group_17
     assign \muxid$14 2'00
@@ -65675,8 +65749,8 @@ module \alu_trap0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \trap_op__insn_type$15
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -65689,30 +65763,30 @@ module \alu_trap0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__msr$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__cia$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \op__traptype$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \op__trapaddr$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \trap_op__fn_unit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \trap_op__insn$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \trap_op__msr$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \trap_op__cia$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \trap_op__is_32bit$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \trap_op__traptype$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \trap_op__trapaddr$22
   process $group_18
-    assign \op__insn_type$15 7'0000000
-    assign \op__fn_unit$16 11'00000000000
-    assign \op__insn$17 32'00000000000000000000000000000000
-    assign \op__msr$18 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__is_32bit$20 1'0
-    assign \op__traptype$21 5'00000
-    assign \op__trapaddr$22 13'0000000000000
-    assign { \op__trapaddr$22 \op__traptype$21 \op__is_32bit$20 \op__cia$19 \op__msr$18 \op__insn$17 \op__fn_unit$16 \op__insn_type$15 } { \pipe_op__trapaddr$11 \pipe_op__traptype$10 \pipe_op__is_32bit$9 \pipe_op__cia$8 \pipe_op__msr$7 \pipe_op__insn$6 \pipe_op__fn_unit$5 \pipe_op__insn_type$4 }
+    assign \trap_op__insn_type$15 7'0000000
+    assign \trap_op__fn_unit$16 11'00000000000
+    assign \trap_op__insn$17 32'00000000000000000000000000000000
+    assign \trap_op__msr$18 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \trap_op__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \trap_op__is_32bit$20 1'0
+    assign \trap_op__traptype$21 5'00000
+    assign \trap_op__trapaddr$22 13'0000000000000
+    assign { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 }
     sync init
   end
   process $group_26
@@ -66842,8 +66916,8 @@ module \trap0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \oper_i_alu_trap0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -66856,79 +66930,79 @@ module \trap0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 4 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 5 \oper_i__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 6 \oper_i__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 input 8 \oper_i__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 input 9 \oper_i__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 10 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \oper_i_alu_trap0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 4 \oper_i_alu_trap0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 5 \oper_i_alu_trap0__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 6 \oper_i_alu_trap0__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_alu_trap0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 input 8 \oper_i_alu_trap0__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 input 9 \oper_i_alu_trap0__trapaddr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 11 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 input 12 \rdmaskn
+  wire width 1 input 10 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 11 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 12 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 13 \rd__rel
+  wire width 4 output 13 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 14 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 4 input 14 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 15 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 16 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 17 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 18 \src4_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 19 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 20 \wr__rel
+  wire width 5 output 20 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 input 21 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 5 input 21 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 22 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 23 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 24 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 25 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 26 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 28 \dest4_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \msr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 30 \dest5_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 31 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 32 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 31 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 32 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_trap0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_trap0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_trap0_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_trap0_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_trap0_fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_trap0_nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_trap0_msr
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -67003,8 +67077,8 @@ module \trap0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_trap0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_trap0_trap_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -67017,27 +67091,27 @@ module \trap0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_trap0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_trap0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_trap0_op__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_trap0_op__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_trap0_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 \alu_trap0_op__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 \alu_trap0_op__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_trap0_trap_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_trap0_trap_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_trap0_trap_op__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_trap0_trap_op__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_trap0_trap_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 \alu_trap0_trap_op__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 \alu_trap0_trap_op__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_trap0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_trap0_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_trap0_fast1$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_trap0_fast2$2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_trap0_p_valid_i
@@ -67058,14 +67132,14 @@ module \trap0
     connect \fast2 \alu_trap0_fast2
     connect \nia \alu_trap0_nia
     connect \msr \alu_trap0_msr
-    connect \op__insn_type \alu_trap0_op__insn_type
-    connect \op__fn_unit \alu_trap0_op__fn_unit
-    connect \op__insn \alu_trap0_op__insn
-    connect \op__msr \alu_trap0_op__msr
-    connect \op__cia \alu_trap0_op__cia
-    connect \op__is_32bit \alu_trap0_op__is_32bit
-    connect \op__traptype \alu_trap0_op__traptype
-    connect \op__trapaddr \alu_trap0_op__trapaddr
+    connect \trap_op__insn_type \alu_trap0_trap_op__insn_type
+    connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit
+    connect \trap_op__insn \alu_trap0_trap_op__insn
+    connect \trap_op__msr \alu_trap0_trap_op__msr
+    connect \trap_op__cia \alu_trap0_trap_op__cia
+    connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit
+    connect \trap_op__traptype \alu_trap0_trap_op__traptype
+    connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr
     connect \ra \alu_trap0_ra
     connect \rb \alu_trap0_rb
     connect \fast1$1 \alu_trap0_fast1$1
@@ -67175,36 +67249,36 @@ module \trap0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 4 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $6
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 4 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -67212,10 +67286,10 @@ module \trap0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A $6
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -67223,9 +67297,9 @@ module \trap0
     connect \A $8
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67241,9 +67315,9 @@ module \trap0
     assign \all_rd $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -67253,11 +67327,11 @@ module \trap0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67265,9 +67339,9 @@ module \trap0
     connect \A \all_rd_dly
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67283,16 +67357,16 @@ module \trap0
     assign \all_rd_pulse $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_trap0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -67302,11 +67376,11 @@ module \trap0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67314,9 +67388,9 @@ module \trap0
     connect \A \alu_done_dly
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67332,28 +67406,28 @@ module \trap0
     assign \alu_pulse $19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 5 \alu_pulsem
   process $group_6
     assign \alu_pulsem 5'00000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 5 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 5 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 5 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $21
   end
   process $group_7
@@ -67369,38 +67443,38 @@ module \trap0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 5 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 5 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 5 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 5 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $25
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -67408,7 +67482,7 @@ module \trap0
     connect \A $27
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67416,39 +67490,39 @@ module \trap0
     connect \A $24
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $23
     connect \Y $31
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $31
+    assign \cu_done_o 1'0
+    assign \cu_done_o $31
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -67456,9 +67530,9 @@ module \trap0
     connect \A \prev_wr_go
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67474,11 +67548,11 @@ module \trap0
     assign \wr_any $37
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67486,9 +67560,9 @@ module \trap0
     connect \A \alu_trap0_n_ready_i
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67499,9 +67573,9 @@ module \trap0
     connect \B $39
     connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 5 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -67509,12 +67583,12 @@ module \trap0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -67525,9 +67599,9 @@ module \trap0
     connect \B 1'0
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67538,22 +67612,22 @@ module \trap0
     connect \B $45
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67564,9 +67638,9 @@ module \trap0
     connect \B \alu_trap0_n_ready_i
     connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67577,9 +67651,9 @@ module \trap0
     connect \B \alu_trap0_n_valid_o
     connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67587,25 +67661,25 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $53
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $55
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $47
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $55 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67613,7 +67687,7 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $57
   end
   process $group_11
@@ -67621,19 +67695,19 @@ module \trap0
     assign \reset $57
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $59
   end
   process $group_12
@@ -67641,19 +67715,19 @@ module \trap0
     assign \rst_r $59
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 5 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 5 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $61
   end
   process $group_13
@@ -67661,19 +67735,19 @@ module \trap0
     assign \reset_w $61
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 4 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 4 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $63
   end
   process $group_14
@@ -67683,12 +67757,12 @@ module \trap0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -67696,7 +67770,7 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_trap0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $65
   end
   process $group_16
@@ -67724,7 +67798,7 @@ module \trap0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -67750,7 +67824,7 @@ module \trap0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -67774,9 +67848,9 @@ module \trap0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 5 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -67784,7 +67858,7 @@ module \trap0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $67
   end
   process $group_23
@@ -67792,9 +67866,9 @@ module \trap0
     assign \req_l_s_req $67
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 5 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -67883,7 +67957,7 @@ module \trap0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -67897,19 +67971,19 @@ module \trap0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 5 \oper_r__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 13 \oper_r__trapaddr
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -67949,8 +68023,8 @@ module \trap0
   cell $mux $72
     parameter \WIDTH 197
     connect \A { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__cia \oper_l__msr \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__cia \oper_i__msr \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
+    connect \S \cu_issue_i
     connect \Y $71
   end
   process $group_25
@@ -67975,10 +68049,10 @@ module \trap0
     assign \oper_l__traptype$next \oper_l__traptype
     assign \oper_l__trapaddr$next \oper_l__trapaddr
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__cia$next \oper_l__msr$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__cia \oper_i__msr \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
+        assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__cia$next \oper_l__msr$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type }
     end
     sync init
       update \oper_l__insn_type 7'0000000
@@ -67999,9 +68073,9 @@ module \trap0
       update \oper_l__traptype \oper_l__traptype$next
       update \oper_l__trapaddr \oper_l__trapaddr$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__o_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__o
@@ -68068,9 +68142,9 @@ module \trap0
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r1__fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__fast1_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r1_l__fast1
@@ -68137,9 +68211,9 @@ module \trap0
       update \data_r1_l__fast1 \data_r1_l__fast1$next
       update \data_r1_l__fast1_ok \data_r1_l__fast1_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r2__fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__fast2_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r2_l__fast2
@@ -68206,9 +68280,9 @@ module \trap0
       update \data_r2_l__fast2 \data_r2_l__fast2$next
       update \data_r2_l__fast2_ok \data_r2_l__fast2_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r3__nia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r3__nia_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r3_l__nia
@@ -68275,9 +68349,9 @@ module \trap0
       update \data_r3_l__nia \data_r3_l__nia$next
       update \data_r3_l__nia_ok \data_r3_l__nia_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r4__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r4__msr_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r4_l__msr
@@ -68344,9 +68418,9 @@ module \trap0
       update \data_r4_l__msr \data_r4_l__msr$next
       update \data_r4_l__msr_ok \data_r4_l__msr_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68354,12 +68428,12 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__o_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $103
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68367,12 +68441,12 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__fast1_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $105
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68380,12 +68454,12 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__fast2_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $107
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68393,12 +68467,12 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r3__nia_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $109
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68406,24 +68480,24 @@ module \trap0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r4__msr_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $111
   end
   process $group_61
-    assign \wrmask 5'00000
-    assign \wrmask { $111 $109 $107 $105 $103 }
+    assign \cu_wrmask_o 5'00000
+    assign \cu_wrmask_o { $111 $109 $107 $105 $103 }
     sync init
   end
   process $group_62
-    assign \alu_trap0_op__insn_type 7'0000000
-    assign \alu_trap0_op__fn_unit 11'00000000000
-    assign \alu_trap0_op__insn 32'00000000000000000000000000000000
-    assign \alu_trap0_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_trap0_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_trap0_op__is_32bit 1'0
-    assign \alu_trap0_op__traptype 5'00000
-    assign \alu_trap0_op__trapaddr 13'0000000000000
-    assign { \alu_trap0_op__trapaddr \alu_trap0_op__traptype \alu_trap0_op__is_32bit \alu_trap0_op__cia \alu_trap0_op__msr \alu_trap0_op__insn \alu_trap0_op__fn_unit \alu_trap0_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__cia \oper_r__msr \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
+    assign \alu_trap0_trap_op__insn_type 7'0000000
+    assign \alu_trap0_trap_op__fn_unit 11'00000000000
+    assign \alu_trap0_trap_op__insn 32'00000000000000000000000000000000
+    assign \alu_trap0_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_trap0_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_trap0_trap_op__is_32bit 1'0
+    assign \alu_trap0_trap_op__traptype 5'00000
+    assign \alu_trap0_trap_op__trapaddr 13'0000000000000
+    assign { \alu_trap0_trap_op__trapaddr \alu_trap0_trap_op__traptype \alu_trap0_trap_op__is_32bit \alu_trap0_trap_op__cia \alu_trap0_trap_op__msr \alu_trap0_trap_op__insn \alu_trap0_trap_op__fn_unit \alu_trap0_trap_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__cia \oper_r__msr \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -68559,9 +68633,9 @@ module \trap0
     assign \alu_trap0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68595,9 +68669,9 @@ module \trap0
     assign \alu_trap0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68627,13 +68701,13 @@ module \trap0
     sync init
   end
   process $group_84
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -68641,12 +68715,12 @@ module \trap0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $125
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -68657,19 +68731,19 @@ module \trap0
     connect \B { 1'1 1'1 1'1 1'1 }
     connect \Y $127
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $129
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -68681,78 +68755,78 @@ module \trap0
     connect \Y $131
   end
   process $group_85
-    assign \rd__rel 4'0000
-    assign \rd__rel $131
+    assign \cu_rd__rel_o 4'0000
+    assign \cu_rd__rel_o $131
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $133
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $135
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $137
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $139
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $141
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 5 $143
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -68763,9 +68837,9 @@ module \trap0
     connect \B { $133 $135 $137 $139 $141 }
     connect \Y $143
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 5 $145
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $146
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -68773,124 +68847,124 @@ module \trap0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 5
     connect \A $143
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $145
   end
   process $group_86
-    assign \wr__rel 5'00000
-    assign \wr__rel $145
+    assign \cu_wr__rel_o 5'00000
+    assign \cu_wr__rel_o $145
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $147
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $148
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $147
   end
   process $group_87
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $147 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $149
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $150
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $149
   end
   process $group_88
     assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $149 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__fast1_ok \data_r1__fast1 } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $151
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $151
   end
   process $group_89
     assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $151 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__fast2_ok \data_r2__fast2 } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $153
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $154
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [3]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [3]
+    connect \B \cu_busy_o
     connect \Y $153
   end
   process $group_90
     assign \dest4_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $153 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest4_o { \data_r3__nia_ok \data_r3__nia } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $155
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [4]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [4]
+    connect \B \cu_busy_o
     connect \Y $155
   end
   process $group_91
     assign \dest5_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $155 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest5_o { \data_r4__msr_ok \data_r4__msr } [63:0]
     end
@@ -68934,9 +69008,9 @@ module \n$44
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -68990,9 +69064,9 @@ module \n$47
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -69012,7 +69086,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.input"
 module \input$48
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -69087,8 +69161,8 @@ module \input$48
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -69101,49 +69175,49 @@ module \input$48
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 11 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 17 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 18 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 11 \logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 19 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 20 \rb
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -69218,8 +69292,8 @@ module \input$48
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 22 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -69232,47 +69306,47 @@ module \input$48
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 23 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 24 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \logical_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \logical_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \logical_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \logical_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \logical_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \logical_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \logical_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \logical_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \logical_op__zero_a$11
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 32 \op__input_carry$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__invert_out$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__write_cr0$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 38 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 39 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 32 \logical_op__input_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \logical_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \logical_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \logical_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 38 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 39 \logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 40 \ra$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 41 \rb$21
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
   wire width 64 \a
@@ -69289,7 +69363,7 @@ module \input$48
   process $group_0
     assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
-    switch { \op__invert_a }
+    switch { \logical_op__invert_a }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
       case 1'1
         assign \a $22
@@ -69310,25 +69384,25 @@ module \input$48
     sync init
   end
   process $group_3
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__input_carry$12 2'00
-    assign \op__invert_out$13 1'0
-    assign \op__write_cr0$14 1'0
-    assign \op__output_carry$15 1'0
-    assign \op__is_32bit$16 1'0
-    assign \op__is_signed$17 1'0
-    assign \op__data_len$18 4'0000
-    assign \op__insn$19 32'00000000000000000000000000000000
-    assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__write_cr0$14 \op__invert_out$13 \op__input_carry$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
   process $group_21
@@ -75318,7 +75392,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main"
 module \main$49
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -75393,8 +75467,8 @@ module \main$49
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -75407,49 +75481,49 @@ module \main$49
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 11 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 17 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 18 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 11 \logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 19 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 20 \rb
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -75524,8 +75598,8 @@ module \main$49
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 22 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -75538,47 +75612,47 @@ module \main$49
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 23 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 24 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \logical_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \logical_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \logical_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \logical_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \logical_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \logical_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \logical_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \logical_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \logical_op__zero_a$11
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 32 \op__input_carry$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__invert_out$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__write_cr0$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 38 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 39 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 32 \logical_op__input_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \logical_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \logical_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \logical_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 38 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 39 \logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 40 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 41 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54"
   wire width 64 \bpermd_rs
@@ -75610,9 +75684,9 @@ module \main$49
     connect \sig_in \clz_sig_in
     connect \lz \clz_lz
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:51"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53"
   wire width 64 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:51"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53"
   cell $and $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -75623,9 +75697,9 @@ module \main$49
     connect \B \rb
     connect \Y $20
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55"
   wire width 64 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55"
   cell $or $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -75636,9 +75710,9 @@ module \main$49
     connect \B \rb
     connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57"
   wire width 64 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57"
   cell $xor $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -75649,9 +75723,9 @@ module \main$49
     connect \B \rb
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75662,9 +75736,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $26
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75675,9 +75749,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $28
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75688,9 +75762,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75701,9 +75775,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $32
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75714,9 +75788,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $34
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75727,9 +75801,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $36
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75740,9 +75814,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75753,9 +75827,9 @@ module \main$49
     connect \B \rb [7:0]
     connect \Y $40
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75766,9 +75840,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75779,9 +75853,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75792,9 +75866,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75805,9 +75879,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $48
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75818,9 +75892,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $50
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75831,9 +75905,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75844,9 +75918,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $54
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75857,9 +75931,9 @@ module \main$49
     connect \B \rb [15:8]
     connect \Y $56
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75870,9 +75944,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $58
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75883,9 +75957,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $60
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $63
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75896,9 +75970,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $62
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75909,9 +75983,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $64
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75922,9 +75996,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $66
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $69
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75935,9 +76009,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $68
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $71
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75948,9 +76022,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $70
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $73
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75961,9 +76035,9 @@ module \main$49
     connect \B \rb [23:16]
     connect \Y $72
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $75
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75974,9 +76048,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $74
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $77
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -75987,9 +76061,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $76
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $79
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76000,9 +76074,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $78
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $81
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76013,9 +76087,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $80
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $83
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76026,9 +76100,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $82
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $85
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76039,9 +76113,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $84
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $87
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76052,9 +76126,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $86
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $89
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76065,9 +76139,9 @@ module \main$49
     connect \B \rb [31:24]
     connect \Y $88
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $91
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76078,9 +76152,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $90
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $93
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76091,9 +76165,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $92
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $95
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76104,9 +76178,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $94
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $97
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76117,9 +76191,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $96
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $99
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76130,9 +76204,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $98
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $101
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76143,9 +76217,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $100
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $103
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76156,9 +76230,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $102
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $105
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76169,9 +76243,9 @@ module \main$49
     connect \B \rb [39:32]
     connect \Y $104
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $107
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76182,9 +76256,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $106
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76195,9 +76269,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $108
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $111
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76208,9 +76282,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $110
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $113
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76221,9 +76295,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $112
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $115
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76234,9 +76308,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $114
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76247,9 +76321,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $116
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76260,9 +76334,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $118
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76273,9 +76347,9 @@ module \main$49
     connect \B \rb [47:40]
     connect \Y $120
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76286,9 +76360,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $122
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76299,9 +76373,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $124
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76312,9 +76386,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $126
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76325,9 +76399,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $128
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76338,9 +76412,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $130
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76351,9 +76425,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $132
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76364,9 +76438,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $134
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76377,9 +76451,9 @@ module \main$49
     connect \B \rb [55:48]
     connect \Y $136
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $138
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76390,9 +76464,9 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $138
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $140
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76403,9 +76477,9 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $140
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76416,9 +76490,9 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $142
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $144
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76429,9 +76503,9 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $144
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $146
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76442,9 +76516,9 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $146
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $148
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76455,9 +76529,9 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $148
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $150
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76468,9 +76542,9 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $150
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   wire width 1 $152
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
   cell $eq $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76481,28 +76555,28 @@ module \main$49
     connect \B \rb [63:56]
     connect \Y $152
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87"
   wire width 1 $154
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87"
   cell $eq $155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \op__data_len [3]
+    connect \A \logical_op__data_len [3]
     connect \B 1'1
     connect \Y $154
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
   wire width 64 $156
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:75"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:83"
   wire width 1 \par0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84"
   wire width 1 \par1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
   wire width 1 $157
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
   cell $xor $158
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -76513,7 +76587,7 @@ module \main$49
     connect \B \par1
     connect \Y $157
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
   cell $pos $159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -76521,11 +76595,11 @@ module \main$49
     connect \A $157
     connect \Y $156
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112"
   wire width 64 $160
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112"
   wire width 8 $161
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112"
   cell $sub $162
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -76546,17 +76620,17 @@ module \main$49
     connect \A \clz_lz
     connect \Y $163
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112"
   wire width 8 $165
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112"
   cell $mux $166
     parameter \WIDTH 8
     connect \A $163
     connect \B $161
-    connect \S \op__is_32bit
+    connect \S \logical_op__is_32bit
     connect \Y $165
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112"
   cell $pos $167
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
@@ -76569,49 +76643,49 @@ module \main$49
     assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \o_ok 1'1
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
         assign \o $20
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
         assign \o $22
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
         assign \o $24
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
         assign \o { { $138 $140 $142 $144 $146 $148 $150 $152 } { $122 $124 $126 $128 $130 $132 $134 $136 } { $106 $108 $110 $112 $114 $116 $118 $120 } { $90 $92 $94 $96 $98 $100 $102 $104 } { $74 $76 $78 $80 $82 $84 $86 $88 } { $58 $60 $62 $64 $66 $68 $70 $72 } { $42 $44 $46 $48 $50 $52 $54 $56 } { $26 $28 $30 $32 $34 $36 $38 $40 } }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
         assign \o \popcount_o
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87"
         switch { $154 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87"
           case 1'1
             assign \o $156
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89"
           case
             assign { \o_ok \o } [0] \par0
             assign { \o_ok \o } [32] \par1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
         assign \o $160
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
         assign \o \bpermd_ra
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
         assign \o_ok 1'0
@@ -76621,33 +76695,33 @@ module \main$49
   process $group_2
     assign \popcount_a 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
         assign \popcount_a \ra
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
@@ -76658,86 +76732,86 @@ module \main$49
   process $group_3
     assign \b 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
         assign \b \rb
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 $168
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   cell $pos $169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 64
-    connect \A \op__data_len
+    connect \A \logical_op__data_len
     connect \Y $168
   end
   process $group_4
     assign \popcount_data_len 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
         assign \popcount_data_len $168
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:77"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85"
   wire width 1 $170
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:77"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85"
   cell $reduce_xor $171
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -76748,41 +76822,41 @@ module \main$49
   process $group_5
     assign \par0 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
         assign \par0 $170
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:78"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
   wire width 1 $172
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:78"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
   cell $reduce_xor $173
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -76793,119 +76867,119 @@ module \main$49
   process $group_6
     assign \par1 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
         assign \par1 $172
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98"
   wire width 1 \count_right
   process $group_7
     assign \count_right 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-        assign \count_right { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] } [9]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+        assign \count_right { \logical_op__insn [10] \logical_op__insn [9] \logical_op__insn [8] \logical_op__insn [7] \logical_op__insn [6] \logical_op__insn [5] \logical_op__insn [4] \logical_op__insn [3] \logical_op__insn [2] \logical_op__insn [1] } [9]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
   wire width 32 \a32
   process $group_8
     assign \a32 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
         assign \a32 \ra [31:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:101"
   wire width 64 \cntz_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106"
   wire width 64 $174
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106"
   wire width 32 $175
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106"
   cell $mux $176
     parameter \WIDTH 32
     connect \A \a32
@@ -76913,7 +76987,7 @@ module \main$49
     connect \S \count_right
     connect \Y $175
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106"
   cell $pos $177
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
@@ -76921,9 +76995,9 @@ module \main$49
     connect \A $175
     connect \Y $174
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108"
   wire width 64 $178
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108"
   cell $mux $179
     parameter \WIDTH 64
     connect \A \ra
@@ -76934,41 +77008,41 @@ module \main$49
   process $group_9
     assign \cntz_i 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:95"
-        switch { \op__is_32bit }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:95"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+        switch { \logical_op__is_32bit }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
           case 1'1
             assign \cntz_i $174
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107"
           case
             assign \cntz_i $178
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
@@ -76977,33 +77051,33 @@ module \main$49
   process $group_10
     assign \clz_sig_in 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
         assign \clz_sig_in \cntz_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
@@ -77012,33 +77086,33 @@ module \main$49
   process $group_11
     assign \bpermd_rs 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
         assign \bpermd_rs \ra
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
@@ -77047,33 +77121,33 @@ module \main$49
   process $group_12
     assign \bpermd_rb 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47"
-    switch \op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
       attribute \nmigen.decoding "OP_AND/4"
       case 7'0000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
       attribute \nmigen.decoding "OP_OR/53"
       case 7'0110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56"
       attribute \nmigen.decoding "OP_XOR/67"
       case 7'1000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
       attribute \nmigen.decoding "OP_CMPB/11"
       case 7'0001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72"
       attribute \nmigen.decoding "OP_POPCNT/54"
       case 7'0110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
       attribute \nmigen.decoding "OP_PRTY/55"
       case 7'0110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
       attribute \nmigen.decoding "OP_CNTZ/14"
       case 7'0001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117"
       attribute \nmigen.decoding "OP_BPERM/9"
       case 7'0001001
         assign \bpermd_rb \rb
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122"
       attribute \nmigen.decoding ""
       case
     end
@@ -77085,32 +77159,32 @@ module \main$49
     sync init
   end
   process $group_14
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__input_carry$12 2'00
-    assign \op__invert_out$13 1'0
-    assign \op__write_cr0$14 1'0
-    assign \op__output_carry$15 1'0
-    assign \op__is_32bit$16 1'0
-    assign \op__is_signed$17 1'0
-    assign \op__data_len$18 4'0000
-    assign \op__insn$19 32'00000000000000000000000000000000
-    assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__write_cr0$14 \op__invert_out$13 \op__input_carry$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.output"
 module \output$50
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -77185,8 +77259,8 @@ module \output$50
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -77199,53 +77273,53 @@ module \output$50
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 11 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 17 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 18 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 11 \logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 19 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 20 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 input 21 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 input 22 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 23 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -77320,8 +77394,8 @@ module \output$50
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 24 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 24 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -77334,55 +77408,55 @@ module \output$50
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 25 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 26 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 25 \logical_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 26 \logical_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \logical_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \logical_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \logical_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \logical_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \logical_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \logical_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \logical_op__zero_a$11
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 34 \op__input_carry$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__invert_out$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__write_cr0$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 38 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 40 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 41 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 34 \logical_op__input_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \logical_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \logical_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \logical_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 40 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 41 \logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 42 \o$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 43 \o_ok$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 44 \cr_a$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 45 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 46 \xer_ca$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 47 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
   wire width 65 \o$24
@@ -77406,9 +77480,9 @@ module \output$50
     connect \A $26
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 65 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   cell $pos $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -77419,7 +77493,7 @@ module \output$50
   process $group_0
     assign \o$24 65'00000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
-    switch { \op__invert_out }
+    switch { \logical_op__invert_out }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
       case 1'1
         assign \o$24 $25
@@ -77443,7 +77517,7 @@ module \output$50
   end
   process $group_3
     assign \xer_ca_ok 1'0
-    assign \xer_ca_ok \op__output_carry
+    assign \xer_ca_ok \logical_op__output_carry
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
@@ -77457,7 +77531,7 @@ module \output$50
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \logical_op__insn_type
     connect \B 7'0001010
     connect \Y $31
   end
@@ -77477,7 +77551,7 @@ module \output$50
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \logical_op__insn_type
     connect \B 7'0001100
     connect \Y $33
   end
@@ -77628,7 +77702,7 @@ module \output$50
   end
   process $group_14
     assign \cr_a_ok 1'0
-    assign \cr_a_ok \op__write_cr0
+    assign \cr_a_ok \logical_op__write_cr0
     sync init
   end
   process $group_15
@@ -77637,25 +77711,25 @@ module \output$50
     sync init
   end
   process $group_16
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__input_carry$12 2'00
-    assign \op__invert_out$13 1'0
-    assign \op__write_cr0$14 1'0
-    assign \op__output_carry$15 1'0
-    assign \op__is_32bit$16 1'0
-    assign \op__is_signed$17 1'0
-    assign \op__data_len$18 4'0000
-    assign \op__insn$19 32'00000000000000000000000000000000
-    assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__write_cr0$14 \op__invert_out$13 \op__input_carry$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
 end
@@ -77670,7 +77744,7 @@ module \pipe$45
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -77745,8 +77819,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -77759,55 +77833,55 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 7 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 15 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 20 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 21 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 22 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 15 \logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 21 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 22 \logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 23 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 24 \rb
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 25 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 26 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 27 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -77882,10 +77956,10 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 28 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 28 \logical_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \logical_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -77898,101 +77972,101 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 29 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 30 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 29 \logical_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \logical_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 30 \logical_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \logical_op__imm_data__imm$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \logical_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__imm_data__imm_ok$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \logical_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__rc__rc$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \logical_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__rc__rc_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \logical_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__oe__oe$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \logical_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \logical_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_a$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \logical_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__zero_a$11$next
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 38 \op__input_carry$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__invert_out$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$13$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 40 \op__write_cr0$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 41 \op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 42 \op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 43 \op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 44 \op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \op__data_len$18$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 45 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$19$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 38 \logical_op__input_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \logical_op__input_carry$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \logical_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_out$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \logical_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__write_cr0$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 41 \logical_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__output_carry$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 42 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_32bit$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 43 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_signed$17$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 44 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \logical_op__data_len$18$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 45 \logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \logical_op__insn$19$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 46 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 47 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 48 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 49 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 50 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 51 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$next
   cell \p$46 \p
     connect \p_valid_i \p_valid_i
@@ -78002,7 +78076,7 @@ module \pipe$45
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -78077,8 +78151,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -78091,49 +78165,49 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \input_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \input_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \input_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid$20
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -78208,8 +78282,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_logical_op__insn_type$21
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -78222,93 +78296,93 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_a$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__zero_a$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_logical_op__fn_unit$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_logical_op__imm_data__imm$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__imm_data__imm_ok$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__rc__rc$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__rc__rc_ok$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__oe__oe$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__oe__oe_ok$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__invert_a$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__zero_a$30
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \input_op__input_carry$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_out$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__write_cr0$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_carry$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \input_op__data_len$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_logical_op__input_carry$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__invert_out$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__write_cr0$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__output_carry$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__is_32bit$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__is_signed$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \input_logical_op__data_len$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_logical_op__insn$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb$40
   cell \input$48 \input
     connect \muxid \input_muxid
-    connect \op__insn_type \input_op__insn_type
-    connect \op__fn_unit \input_op__fn_unit
-    connect \op__imm_data__imm \input_op__imm_data__imm
-    connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
-    connect \op__rc__rc \input_op__rc__rc
-    connect \op__rc__rc_ok \input_op__rc__rc_ok
-    connect \op__oe__oe \input_op__oe__oe
-    connect \op__oe__oe_ok \input_op__oe__oe_ok
-    connect \op__invert_a \input_op__invert_a
-    connect \op__zero_a \input_op__zero_a
-    connect \op__input_carry \input_op__input_carry
-    connect \op__invert_out \input_op__invert_out
-    connect \op__write_cr0 \input_op__write_cr0
-    connect \op__output_carry \input_op__output_carry
-    connect \op__is_32bit \input_op__is_32bit
-    connect \op__is_signed \input_op__is_signed
-    connect \op__data_len \input_op__data_len
-    connect \op__insn \input_op__insn
+    connect \logical_op__insn_type \input_logical_op__insn_type
+    connect \logical_op__fn_unit \input_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \input_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \input_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \input_logical_op__invert_a
+    connect \logical_op__zero_a \input_logical_op__zero_a
+    connect \logical_op__input_carry \input_logical_op__input_carry
+    connect \logical_op__invert_out \input_logical_op__invert_out
+    connect \logical_op__write_cr0 \input_logical_op__write_cr0
+    connect \logical_op__output_carry \input_logical_op__output_carry
+    connect \logical_op__is_32bit \input_logical_op__is_32bit
+    connect \logical_op__is_signed \input_logical_op__is_signed
+    connect \logical_op__data_len \input_logical_op__data_len
+    connect \logical_op__insn \input_logical_op__insn
     connect \ra \input_ra
     connect \rb \input_rb
     connect \muxid$1 \input_muxid$20
-    connect \op__insn_type$2 \input_op__insn_type$21
-    connect \op__fn_unit$3 \input_op__fn_unit$22
-    connect \op__imm_data__imm$4 \input_op__imm_data__imm$23
-    connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$24
-    connect \op__rc__rc$6 \input_op__rc__rc$25
-    connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$26
-    connect \op__oe__oe$8 \input_op__oe__oe$27
-    connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$28
-    connect \op__invert_a$10 \input_op__invert_a$29
-    connect \op__zero_a$11 \input_op__zero_a$30
-    connect \op__input_carry$12 \input_op__input_carry$31
-    connect \op__invert_out$13 \input_op__invert_out$32
-    connect \op__write_cr0$14 \input_op__write_cr0$33
-    connect \op__output_carry$15 \input_op__output_carry$34
-    connect \op__is_32bit$16 \input_op__is_32bit$35
-    connect \op__is_signed$17 \input_op__is_signed$36
-    connect \op__data_len$18 \input_op__data_len$37
-    connect \op__insn$19 \input_op__insn$38
+    connect \logical_op__insn_type$2 \input_logical_op__insn_type$21
+    connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$22
+    connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$23
+    connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$24
+    connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$25
+    connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$26
+    connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$27
+    connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$28
+    connect \logical_op__invert_a$10 \input_logical_op__invert_a$29
+    connect \logical_op__zero_a$11 \input_logical_op__zero_a$30
+    connect \logical_op__input_carry$12 \input_logical_op__input_carry$31
+    connect \logical_op__invert_out$13 \input_logical_op__invert_out$32
+    connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$33
+    connect \logical_op__output_carry$15 \input_logical_op__output_carry$34
+    connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$35
+    connect \logical_op__is_signed$17 \input_logical_op__is_signed$36
+    connect \logical_op__data_len$18 \input_logical_op__data_len$37
+    connect \logical_op__insn$19 \input_logical_op__insn$38
     connect \ra$20 \input_ra$39
     connect \rb$21 \input_rb$40
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -78383,8 +78457,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -78397,49 +78471,49 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \main_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \main_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \main_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_rb
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid$41
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -78514,8 +78588,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_logical_op__insn_type$42
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -78528,93 +78602,93 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc_ok$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe_ok$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_a$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__zero_a$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_logical_op__fn_unit$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_logical_op__imm_data__imm$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__imm_data__imm_ok$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__rc__rc$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__rc__rc_ok$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__oe__oe$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__oe__oe_ok$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__invert_a$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__zero_a$51
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \main_op__input_carry$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__invert_out$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__write_cr0$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_carry$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_signed$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \main_op__data_len$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_logical_op__input_carry$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__invert_out$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__write_cr0$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__output_carry$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__is_32bit$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_logical_op__is_signed$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \main_logical_op__data_len$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_logical_op__insn$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_o_ok
   cell \main$49 \main
     connect \muxid \main_muxid
-    connect \op__insn_type \main_op__insn_type
-    connect \op__fn_unit \main_op__fn_unit
-    connect \op__imm_data__imm \main_op__imm_data__imm
-    connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
-    connect \op__rc__rc \main_op__rc__rc
-    connect \op__rc__rc_ok \main_op__rc__rc_ok
-    connect \op__oe__oe \main_op__oe__oe
-    connect \op__oe__oe_ok \main_op__oe__oe_ok
-    connect \op__invert_a \main_op__invert_a
-    connect \op__zero_a \main_op__zero_a
-    connect \op__input_carry \main_op__input_carry
-    connect \op__invert_out \main_op__invert_out
-    connect \op__write_cr0 \main_op__write_cr0
-    connect \op__output_carry \main_op__output_carry
-    connect \op__is_32bit \main_op__is_32bit
-    connect \op__is_signed \main_op__is_signed
-    connect \op__data_len \main_op__data_len
-    connect \op__insn \main_op__insn
+    connect \logical_op__insn_type \main_logical_op__insn_type
+    connect \logical_op__fn_unit \main_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \main_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \main_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \main_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \main_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \main_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \main_logical_op__invert_a
+    connect \logical_op__zero_a \main_logical_op__zero_a
+    connect \logical_op__input_carry \main_logical_op__input_carry
+    connect \logical_op__invert_out \main_logical_op__invert_out
+    connect \logical_op__write_cr0 \main_logical_op__write_cr0
+    connect \logical_op__output_carry \main_logical_op__output_carry
+    connect \logical_op__is_32bit \main_logical_op__is_32bit
+    connect \logical_op__is_signed \main_logical_op__is_signed
+    connect \logical_op__data_len \main_logical_op__data_len
+    connect \logical_op__insn \main_logical_op__insn
     connect \ra \main_ra
     connect \rb \main_rb
     connect \muxid$1 \main_muxid$41
-    connect \op__insn_type$2 \main_op__insn_type$42
-    connect \op__fn_unit$3 \main_op__fn_unit$43
-    connect \op__imm_data__imm$4 \main_op__imm_data__imm$44
-    connect \op__imm_data__imm_ok$5 \main_op__imm_data__imm_ok$45
-    connect \op__rc__rc$6 \main_op__rc__rc$46
-    connect \op__rc__rc_ok$7 \main_op__rc__rc_ok$47
-    connect \op__oe__oe$8 \main_op__oe__oe$48
-    connect \op__oe__oe_ok$9 \main_op__oe__oe_ok$49
-    connect \op__invert_a$10 \main_op__invert_a$50
-    connect \op__zero_a$11 \main_op__zero_a$51
-    connect \op__input_carry$12 \main_op__input_carry$52
-    connect \op__invert_out$13 \main_op__invert_out$53
-    connect \op__write_cr0$14 \main_op__write_cr0$54
-    connect \op__output_carry$15 \main_op__output_carry$55
-    connect \op__is_32bit$16 \main_op__is_32bit$56
-    connect \op__is_signed$17 \main_op__is_signed$57
-    connect \op__data_len$18 \main_op__data_len$58
-    connect \op__insn$19 \main_op__insn$59
+    connect \logical_op__insn_type$2 \main_logical_op__insn_type$42
+    connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$43
+    connect \logical_op__imm_data__imm$4 \main_logical_op__imm_data__imm$44
+    connect \logical_op__imm_data__imm_ok$5 \main_logical_op__imm_data__imm_ok$45
+    connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$46
+    connect \logical_op__rc__rc_ok$7 \main_logical_op__rc__rc_ok$47
+    connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$48
+    connect \logical_op__oe__oe_ok$9 \main_logical_op__oe__oe_ok$49
+    connect \logical_op__invert_a$10 \main_logical_op__invert_a$50
+    connect \logical_op__zero_a$11 \main_logical_op__zero_a$51
+    connect \logical_op__input_carry$12 \main_logical_op__input_carry$52
+    connect \logical_op__invert_out$13 \main_logical_op__invert_out$53
+    connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$54
+    connect \logical_op__output_carry$15 \main_logical_op__output_carry$55
+    connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$56
+    connect \logical_op__is_signed$17 \main_logical_op__is_signed$57
+    connect \logical_op__data_len$18 \main_logical_op__data_len$58
+    connect \logical_op__insn$19 \main_logical_op__insn$59
     connect \o \main_o
     connect \o_ok \main_o_ok
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -78689,8 +78763,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -78703,53 +78777,53 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \output_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \output_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid$60
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -78824,8 +78898,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_logical_op__insn_type$61
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -78838,99 +78912,99 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_a$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__zero_a$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_logical_op__fn_unit$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_logical_op__imm_data__imm$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__imm_data__imm_ok$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__rc__rc$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__rc__rc_ok$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__oe__oe$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__oe__oe_ok$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__invert_a$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__zero_a$70
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \output_op__input_carry$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_out$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__write_cr0$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_carry$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \output_op__data_len$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_logical_op__input_carry$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__invert_out$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__write_cr0$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__output_carry$74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__is_32bit$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__is_signed$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_logical_op__data_len$77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_logical_op__insn$78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ca$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_ca_ok
   cell \output$50 \output
     connect \muxid \output_muxid
-    connect \op__insn_type \output_op__insn_type
-    connect \op__fn_unit \output_op__fn_unit
-    connect \op__imm_data__imm \output_op__imm_data__imm
-    connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
-    connect \op__rc__rc \output_op__rc__rc
-    connect \op__rc__rc_ok \output_op__rc__rc_ok
-    connect \op__oe__oe \output_op__oe__oe
-    connect \op__oe__oe_ok \output_op__oe__oe_ok
-    connect \op__invert_a \output_op__invert_a
-    connect \op__zero_a \output_op__zero_a
-    connect \op__input_carry \output_op__input_carry
-    connect \op__invert_out \output_op__invert_out
-    connect \op__write_cr0 \output_op__write_cr0
-    connect \op__output_carry \output_op__output_carry
-    connect \op__is_32bit \output_op__is_32bit
-    connect \op__is_signed \output_op__is_signed
-    connect \op__data_len \output_op__data_len
-    connect \op__insn \output_op__insn
+    connect \logical_op__insn_type \output_logical_op__insn_type
+    connect \logical_op__fn_unit \output_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \output_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \output_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \output_logical_op__invert_a
+    connect \logical_op__zero_a \output_logical_op__zero_a
+    connect \logical_op__input_carry \output_logical_op__input_carry
+    connect \logical_op__invert_out \output_logical_op__invert_out
+    connect \logical_op__write_cr0 \output_logical_op__write_cr0
+    connect \logical_op__output_carry \output_logical_op__output_carry
+    connect \logical_op__is_32bit \output_logical_op__is_32bit
+    connect \logical_op__is_signed \output_logical_op__is_signed
+    connect \logical_op__data_len \output_logical_op__data_len
+    connect \logical_op__insn \output_logical_op__insn
     connect \o \output_o
     connect \o_ok \output_o_ok
     connect \cr_a \output_cr_a
     connect \xer_ca \output_xer_ca
     connect \muxid$1 \output_muxid$60
-    connect \op__insn_type$2 \output_op__insn_type$61
-    connect \op__fn_unit$3 \output_op__fn_unit$62
-    connect \op__imm_data__imm$4 \output_op__imm_data__imm$63
-    connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$64
-    connect \op__rc__rc$6 \output_op__rc__rc$65
-    connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$66
-    connect \op__oe__oe$8 \output_op__oe__oe$67
-    connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$68
-    connect \op__invert_a$10 \output_op__invert_a$69
-    connect \op__zero_a$11 \output_op__zero_a$70
-    connect \op__input_carry$12 \output_op__input_carry$71
-    connect \op__invert_out$13 \output_op__invert_out$72
-    connect \op__write_cr0$14 \output_op__write_cr0$73
-    connect \op__output_carry$15 \output_op__output_carry$74
-    connect \op__is_32bit$16 \output_op__is_32bit$75
-    connect \op__is_signed$17 \output_op__is_signed$76
-    connect \op__data_len$18 \output_op__data_len$77
-    connect \op__insn$19 \output_op__insn$78
+    connect \logical_op__insn_type$2 \output_logical_op__insn_type$61
+    connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$62
+    connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$63
+    connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$64
+    connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$65
+    connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$66
+    connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$67
+    connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$68
+    connect \logical_op__invert_a$10 \output_logical_op__invert_a$69
+    connect \logical_op__zero_a$11 \output_logical_op__zero_a$70
+    connect \logical_op__input_carry$12 \output_logical_op__input_carry$71
+    connect \logical_op__invert_out$13 \output_logical_op__invert_out$72
+    connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$73
+    connect \logical_op__output_carry$15 \output_logical_op__output_carry$74
+    connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$75
+    connect \logical_op__is_signed$17 \output_logical_op__is_signed$76
+    connect \logical_op__data_len$18 \output_logical_op__data_len$77
+    connect \logical_op__insn$19 \output_logical_op__insn$78
     connect \o$20 \output_o$79
     connect \o_ok$21 \output_o_ok$80
     connect \cr_a$22 \output_cr_a$81
@@ -78944,25 +79018,25 @@ module \pipe$45
     sync init
   end
   process $group_1
-    assign \input_op__insn_type 7'0000000
-    assign \input_op__fn_unit 11'00000000000
-    assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_op__imm_data__imm_ok 1'0
-    assign \input_op__rc__rc 1'0
-    assign \input_op__rc__rc_ok 1'0
-    assign \input_op__oe__oe 1'0
-    assign \input_op__oe__oe_ok 1'0
-    assign \input_op__invert_a 1'0
-    assign \input_op__zero_a 1'0
-    assign \input_op__input_carry 2'00
-    assign \input_op__invert_out 1'0
-    assign \input_op__write_cr0 1'0
-    assign \input_op__output_carry 1'0
-    assign \input_op__is_32bit 1'0
-    assign \input_op__is_signed 1'0
-    assign \input_op__data_len 4'0000
-    assign \input_op__insn 32'00000000000000000000000000000000
-    assign { \input_op__insn \input_op__data_len \input_op__is_signed \input_op__is_32bit \input_op__output_carry \input_op__write_cr0 \input_op__invert_out \input_op__input_carry \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \input_logical_op__insn_type 7'0000000
+    assign \input_logical_op__fn_unit 11'00000000000
+    assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_logical_op__imm_data__imm_ok 1'0
+    assign \input_logical_op__rc__rc 1'0
+    assign \input_logical_op__rc__rc_ok 1'0
+    assign \input_logical_op__oe__oe 1'0
+    assign \input_logical_op__oe__oe_ok 1'0
+    assign \input_logical_op__invert_a 1'0
+    assign \input_logical_op__zero_a 1'0
+    assign \input_logical_op__input_carry 2'00
+    assign \input_logical_op__invert_out 1'0
+    assign \input_logical_op__write_cr0 1'0
+    assign \input_logical_op__output_carry 1'0
+    assign \input_logical_op__is_32bit 1'0
+    assign \input_logical_op__is_signed 1'0
+    assign \input_logical_op__data_len 4'0000
+    assign \input_logical_op__insn 32'00000000000000000000000000000000
+    assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_a { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
   process $group_19
@@ -78981,25 +79055,25 @@ module \pipe$45
     sync init
   end
   process $group_22
-    assign \main_op__insn_type 7'0000000
-    assign \main_op__fn_unit 11'00000000000
-    assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_op__imm_data__imm_ok 1'0
-    assign \main_op__rc__rc 1'0
-    assign \main_op__rc__rc_ok 1'0
-    assign \main_op__oe__oe 1'0
-    assign \main_op__oe__oe_ok 1'0
-    assign \main_op__invert_a 1'0
-    assign \main_op__zero_a 1'0
-    assign \main_op__input_carry 2'00
-    assign \main_op__invert_out 1'0
-    assign \main_op__write_cr0 1'0
-    assign \main_op__output_carry 1'0
-    assign \main_op__is_32bit 1'0
-    assign \main_op__is_signed 1'0
-    assign \main_op__data_len 4'0000
-    assign \main_op__insn 32'00000000000000000000000000000000
-    assign { \main_op__insn \main_op__data_len \main_op__is_signed \main_op__is_32bit \main_op__output_carry \main_op__write_cr0 \main_op__invert_out \main_op__input_carry \main_op__zero_a \main_op__invert_a { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$38 \input_op__data_len$37 \input_op__is_signed$36 \input_op__is_32bit$35 \input_op__output_carry$34 \input_op__write_cr0$33 \input_op__invert_out$32 \input_op__input_carry$31 \input_op__zero_a$30 \input_op__invert_a$29 { \input_op__oe__oe_ok$28 \input_op__oe__oe$27 } { \input_op__rc__rc_ok$26 \input_op__rc__rc$25 } { \input_op__imm_data__imm_ok$24 \input_op__imm_data__imm$23 } \input_op__fn_unit$22 \input_op__insn_type$21 }
+    assign \main_logical_op__insn_type 7'0000000
+    assign \main_logical_op__fn_unit 11'00000000000
+    assign \main_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_logical_op__imm_data__imm_ok 1'0
+    assign \main_logical_op__rc__rc 1'0
+    assign \main_logical_op__rc__rc_ok 1'0
+    assign \main_logical_op__oe__oe 1'0
+    assign \main_logical_op__oe__oe_ok 1'0
+    assign \main_logical_op__invert_a 1'0
+    assign \main_logical_op__zero_a 1'0
+    assign \main_logical_op__input_carry 2'00
+    assign \main_logical_op__invert_out 1'0
+    assign \main_logical_op__write_cr0 1'0
+    assign \main_logical_op__output_carry 1'0
+    assign \main_logical_op__is_32bit 1'0
+    assign \main_logical_op__is_signed 1'0
+    assign \main_logical_op__data_len 4'0000
+    assign \main_logical_op__insn 32'00000000000000000000000000000000
+    assign { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_a { \main_logical_op__oe__oe_ok \main_logical_op__oe__oe } { \main_logical_op__rc__rc_ok \main_logical_op__rc__rc } { \main_logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm } \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$38 \input_logical_op__data_len$37 \input_logical_op__is_signed$36 \input_logical_op__is_32bit$35 \input_logical_op__output_carry$34 \input_logical_op__write_cr0$33 \input_logical_op__invert_out$32 \input_logical_op__input_carry$31 \input_logical_op__zero_a$30 \input_logical_op__invert_a$29 { \input_logical_op__oe__oe_ok$28 \input_logical_op__oe__oe$27 } { \input_logical_op__rc__rc_ok$26 \input_logical_op__rc__rc$25 } { \input_logical_op__imm_data__imm_ok$24 \input_logical_op__imm_data__imm$23 } \input_logical_op__fn_unit$22 \input_logical_op__insn_type$21 }
     sync init
   end
   process $group_40
@@ -79018,25 +79092,25 @@ module \pipe$45
     sync init
   end
   process $group_43
-    assign \output_op__insn_type 7'0000000
-    assign \output_op__fn_unit 11'00000000000
-    assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_op__imm_data__imm_ok 1'0
-    assign \output_op__rc__rc 1'0
-    assign \output_op__rc__rc_ok 1'0
-    assign \output_op__oe__oe 1'0
-    assign \output_op__oe__oe_ok 1'0
-    assign \output_op__invert_a 1'0
-    assign \output_op__zero_a 1'0
-    assign \output_op__input_carry 2'00
-    assign \output_op__invert_out 1'0
-    assign \output_op__write_cr0 1'0
-    assign \output_op__output_carry 1'0
-    assign \output_op__is_32bit 1'0
-    assign \output_op__is_signed 1'0
-    assign \output_op__data_len 4'0000
-    assign \output_op__insn 32'00000000000000000000000000000000
-    assign { \output_op__insn \output_op__data_len \output_op__is_signed \output_op__is_32bit \output_op__output_carry \output_op__write_cr0 \output_op__invert_out \output_op__input_carry \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$59 \main_op__data_len$58 \main_op__is_signed$57 \main_op__is_32bit$56 \main_op__output_carry$55 \main_op__write_cr0$54 \main_op__invert_out$53 \main_op__input_carry$52 \main_op__zero_a$51 \main_op__invert_a$50 { \main_op__oe__oe_ok$49 \main_op__oe__oe$48 } { \main_op__rc__rc_ok$47 \main_op__rc__rc$46 } { \main_op__imm_data__imm_ok$45 \main_op__imm_data__imm$44 } \main_op__fn_unit$43 \main_op__insn_type$42 }
+    assign \output_logical_op__insn_type 7'0000000
+    assign \output_logical_op__fn_unit 11'00000000000
+    assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_logical_op__imm_data__imm_ok 1'0
+    assign \output_logical_op__rc__rc 1'0
+    assign \output_logical_op__rc__rc_ok 1'0
+    assign \output_logical_op__oe__oe 1'0
+    assign \output_logical_op__oe__oe_ok 1'0
+    assign \output_logical_op__invert_a 1'0
+    assign \output_logical_op__zero_a 1'0
+    assign \output_logical_op__input_carry 2'00
+    assign \output_logical_op__invert_out 1'0
+    assign \output_logical_op__write_cr0 1'0
+    assign \output_logical_op__output_carry 1'0
+    assign \output_logical_op__is_32bit 1'0
+    assign \output_logical_op__is_signed 1'0
+    assign \output_logical_op__data_len 4'0000
+    assign \output_logical_op__insn 32'00000000000000000000000000000000
+    assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_a { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \main_logical_op__insn$59 \main_logical_op__data_len$58 \main_logical_op__is_signed$57 \main_logical_op__is_32bit$56 \main_logical_op__output_carry$55 \main_logical_op__write_cr0$54 \main_logical_op__invert_out$53 \main_logical_op__input_carry$52 \main_logical_op__zero_a$51 \main_logical_op__invert_a$50 { \main_logical_op__oe__oe_ok$49 \main_logical_op__oe__oe$48 } { \main_logical_op__rc__rc_ok$47 \main_logical_op__rc__rc$46 } { \main_logical_op__imm_data__imm_ok$45 \main_logical_op__imm_data__imm$44 } \main_logical_op__fn_unit$43 \main_logical_op__insn_type$42 }
     sync init
   end
   process $group_61
@@ -79045,11 +79119,11 @@ module \pipe$45
     assign { \output_o_ok \output_o } { \main_o_ok \main_o }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$85
   process $group_63
     assign \output_cr_a 4'0000
@@ -79057,11 +79131,11 @@ module \pipe$45
     assign { \cr_a_ok$83 \output_cr_a } { \cr_a_ok$85 \cr_a$84 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$88
   process $group_65
     assign \output_xer_ca 2'00
@@ -79103,7 +79177,7 @@ module \pipe$45
     assign \p_valid_i_p_ready_o $90
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$92
   process $group_70
     assign \muxid$92 2'00
@@ -79183,8 +79257,8 @@ module \pipe$45
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \logical_op__insn_type$93
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -79197,69 +79271,69 @@ module \pipe$45
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$102
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \logical_op__fn_unit$94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \logical_op__imm_data__imm$95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__imm_data__imm_ok$96
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__rc__rc$97
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__rc__rc_ok$98
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__oe__oe$99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__oe__oe_ok$100
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_a$101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__zero_a$102
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \op__data_len$109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$110
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \logical_op__input_carry$103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_out$104
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__write_cr0$105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__output_carry$106
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_32bit$107
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_signed$108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \logical_op__data_len$109
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \logical_op__insn$110
   process $group_71
-    assign \op__insn_type$93 7'0000000
-    assign \op__fn_unit$94 11'00000000000
-    assign \op__imm_data__imm$95 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$96 1'0
-    assign \op__rc__rc$97 1'0
-    assign \op__rc__rc_ok$98 1'0
-    assign \op__oe__oe$99 1'0
-    assign \op__oe__oe_ok$100 1'0
-    assign \op__invert_a$101 1'0
-    assign \op__zero_a$102 1'0
-    assign \op__input_carry$103 2'00
-    assign \op__invert_out$104 1'0
-    assign \op__write_cr0$105 1'0
-    assign \op__output_carry$106 1'0
-    assign \op__is_32bit$107 1'0
-    assign \op__is_signed$108 1'0
-    assign \op__data_len$109 4'0000
-    assign \op__insn$110 32'00000000000000000000000000000000
-    assign { \op__insn$110 \op__data_len$109 \op__is_signed$108 \op__is_32bit$107 \op__output_carry$106 \op__write_cr0$105 \op__invert_out$104 \op__input_carry$103 \op__zero_a$102 \op__invert_a$101 { \op__oe__oe_ok$100 \op__oe__oe$99 } { \op__rc__rc_ok$98 \op__rc__rc$97 } { \op__imm_data__imm_ok$96 \op__imm_data__imm$95 } \op__fn_unit$94 \op__insn_type$93 } { \output_op__insn$78 \output_op__data_len$77 \output_op__is_signed$76 \output_op__is_32bit$75 \output_op__output_carry$74 \output_op__write_cr0$73 \output_op__invert_out$72 \output_op__input_carry$71 \output_op__zero_a$70 \output_op__invert_a$69 { \output_op__oe__oe_ok$68 \output_op__oe__oe$67 } { \output_op__rc__rc_ok$66 \output_op__rc__rc$65 } { \output_op__imm_data__imm_ok$64 \output_op__imm_data__imm$63 } \output_op__fn_unit$62 \output_op__insn_type$61 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+    assign \logical_op__insn_type$93 7'0000000
+    assign \logical_op__fn_unit$94 11'00000000000
+    assign \logical_op__imm_data__imm$95 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$96 1'0
+    assign \logical_op__rc__rc$97 1'0
+    assign \logical_op__rc__rc_ok$98 1'0
+    assign \logical_op__oe__oe$99 1'0
+    assign \logical_op__oe__oe_ok$100 1'0
+    assign \logical_op__invert_a$101 1'0
+    assign \logical_op__zero_a$102 1'0
+    assign \logical_op__input_carry$103 2'00
+    assign \logical_op__invert_out$104 1'0
+    assign \logical_op__write_cr0$105 1'0
+    assign \logical_op__output_carry$106 1'0
+    assign \logical_op__is_32bit$107 1'0
+    assign \logical_op__is_signed$108 1'0
+    assign \logical_op__data_len$109 4'0000
+    assign \logical_op__insn$110 32'00000000000000000000000000000000
+    assign { \logical_op__insn$110 \logical_op__data_len$109 \logical_op__is_signed$108 \logical_op__is_32bit$107 \logical_op__output_carry$106 \logical_op__write_cr0$105 \logical_op__invert_out$104 \logical_op__input_carry$103 \logical_op__zero_a$102 \logical_op__invert_a$101 { \logical_op__oe__oe_ok$100 \logical_op__oe__oe$99 } { \logical_op__rc__rc_ok$98 \logical_op__rc__rc$97 } { \logical_op__imm_data__imm_ok$96 \logical_op__imm_data__imm$95 } \logical_op__fn_unit$94 \logical_op__insn_type$93 } { \output_logical_op__insn$78 \output_logical_op__data_len$77 \output_logical_op__is_signed$76 \output_logical_op__is_32bit$75 \output_logical_op__output_carry$74 \output_logical_op__write_cr0$73 \output_logical_op__invert_out$72 \output_logical_op__input_carry$71 \output_logical_op__zero_a$70 \output_logical_op__invert_a$69 { \output_logical_op__oe__oe_ok$68 \output_logical_op__oe__oe$67 } { \output_logical_op__rc__rc_ok$66 \output_logical_op__rc__rc$65 } { \output_logical_op__imm_data__imm_ok$64 \output_logical_op__imm_data__imm$63 } \output_logical_op__fn_unit$62 \output_logical_op__insn_type$61 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$112
   process $group_89
     assign \o$111 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -79267,9 +79341,9 @@ module \pipe$45
     assign { \o_ok$112 \o$111 } { \output_o_ok$80 \output_o$79 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$114
   process $group_91
     assign \cr_a$113 4'0000
@@ -79277,9 +79351,9 @@ module \pipe$45
     assign { \cr_a_ok$114 \cr_a$113 } { \output_cr_a_ok \output_cr_a$81 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$116
   process $group_93
     assign \xer_ca$115 2'00
@@ -79329,81 +79403,81 @@ module \pipe$45
       update \muxid$1 \muxid$1$next
   end
   process $group_97
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__imm_data__imm$4$next \op__imm_data__imm$4
-    assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
-    assign \op__rc__rc$6$next \op__rc__rc$6
-    assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
-    assign \op__oe__oe$8$next \op__oe__oe$8
-    assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
-    assign \op__invert_a$10$next \op__invert_a$10
-    assign \op__zero_a$11$next \op__zero_a$11
-    assign \op__input_carry$12$next \op__input_carry$12
-    assign \op__invert_out$13$next \op__invert_out$13
-    assign \op__write_cr0$14$next \op__write_cr0$14
-    assign \op__output_carry$15$next \op__output_carry$15
-    assign \op__is_32bit$16$next \op__is_32bit$16
-    assign \op__is_signed$17$next \op__is_signed$17
-    assign \op__data_len$18$next \op__data_len$18
-    assign \op__insn$19$next \op__insn$19
+    assign \logical_op__insn_type$2$next \logical_op__insn_type$2
+    assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3
+    assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4
+    assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5
+    assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6
+    assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7
+    assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8
+    assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9
+    assign \logical_op__invert_a$10$next \logical_op__invert_a$10
+    assign \logical_op__zero_a$11$next \logical_op__zero_a$11
+    assign \logical_op__input_carry$12$next \logical_op__input_carry$12
+    assign \logical_op__invert_out$13$next \logical_op__invert_out$13
+    assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14
+    assign \logical_op__output_carry$15$next \logical_op__output_carry$15
+    assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16
+    assign \logical_op__is_signed$17$next \logical_op__is_signed$17
+    assign \logical_op__data_len$18$next \logical_op__data_len$18
+    assign \logical_op__insn$19$next \logical_op__insn$19
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__write_cr0$14$next \op__invert_out$13$next \op__input_carry$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$110 \op__data_len$109 \op__is_signed$108 \op__is_32bit$107 \op__output_carry$106 \op__write_cr0$105 \op__invert_out$104 \op__input_carry$103 \op__zero_a$102 \op__invert_a$101 { \op__oe__oe_ok$100 \op__oe__oe$99 } { \op__rc__rc_ok$98 \op__rc__rc$97 } { \op__imm_data__imm_ok$96 \op__imm_data__imm$95 } \op__fn_unit$94 \op__insn_type$93 }
+        assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$110 \logical_op__data_len$109 \logical_op__is_signed$108 \logical_op__is_32bit$107 \logical_op__output_carry$106 \logical_op__write_cr0$105 \logical_op__invert_out$104 \logical_op__input_carry$103 \logical_op__zero_a$102 \logical_op__invert_a$101 { \logical_op__oe__oe_ok$100 \logical_op__oe__oe$99 } { \logical_op__rc__rc_ok$98 \logical_op__rc__rc$97 } { \logical_op__imm_data__imm_ok$96 \logical_op__imm_data__imm$95 } \logical_op__fn_unit$94 \logical_op__insn_type$93 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__write_cr0$14$next \op__invert_out$13$next \op__input_carry$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$110 \op__data_len$109 \op__is_signed$108 \op__is_32bit$107 \op__output_carry$106 \op__write_cr0$105 \op__invert_out$104 \op__input_carry$103 \op__zero_a$102 \op__invert_a$101 { \op__oe__oe_ok$100 \op__oe__oe$99 } { \op__rc__rc_ok$98 \op__rc__rc$97 } { \op__imm_data__imm_ok$96 \op__imm_data__imm$95 } \op__fn_unit$94 \op__insn_type$93 }
+        assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$110 \logical_op__data_len$109 \logical_op__is_signed$108 \logical_op__is_32bit$107 \logical_op__output_carry$106 \logical_op__write_cr0$105 \logical_op__invert_out$104 \logical_op__input_carry$103 \logical_op__zero_a$102 \logical_op__invert_a$101 { \logical_op__oe__oe_ok$100 \logical_op__oe__oe$99 } { \logical_op__rc__rc_ok$98 \logical_op__rc__rc$97 } { \logical_op__imm_data__imm_ok$96 \logical_op__imm_data__imm$95 } \logical_op__fn_unit$94 \logical_op__insn_type$93 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \op__imm_data__imm_ok$5$next 1'0
-        assign \op__rc__rc$6$next 1'0
-        assign \op__rc__rc_ok$7$next 1'0
-        assign \op__oe__oe$8$next 1'0
-        assign \op__oe__oe_ok$9$next 1'0
-    end
-    sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__imm_data__imm_ok$5 1'0
-      update \op__rc__rc$6 1'0
-      update \op__rc__rc_ok$7 1'0
-      update \op__oe__oe$8 1'0
-      update \op__oe__oe_ok$9 1'0
-      update \op__invert_a$10 1'0
-      update \op__zero_a$11 1'0
-      update \op__input_carry$12 2'00
-      update \op__invert_out$13 1'0
-      update \op__write_cr0$14 1'0
-      update \op__output_carry$15 1'0
-      update \op__is_32bit$16 1'0
-      update \op__is_signed$17 1'0
-      update \op__data_len$18 4'0000
-      update \op__insn$19 32'00000000000000000000000000000000
+        assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \logical_op__imm_data__imm_ok$5$next 1'0
+        assign \logical_op__rc__rc$6$next 1'0
+        assign \logical_op__rc__rc_ok$7$next 1'0
+        assign \logical_op__oe__oe$8$next 1'0
+        assign \logical_op__oe__oe_ok$9$next 1'0
+    end
+    sync init
+      update \logical_op__insn_type$2 7'0000000
+      update \logical_op__fn_unit$3 11'00000000000
+      update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \logical_op__imm_data__imm_ok$5 1'0
+      update \logical_op__rc__rc$6 1'0
+      update \logical_op__rc__rc_ok$7 1'0
+      update \logical_op__oe__oe$8 1'0
+      update \logical_op__oe__oe_ok$9 1'0
+      update \logical_op__invert_a$10 1'0
+      update \logical_op__zero_a$11 1'0
+      update \logical_op__input_carry$12 2'00
+      update \logical_op__invert_out$13 1'0
+      update \logical_op__write_cr0$14 1'0
+      update \logical_op__output_carry$15 1'0
+      update \logical_op__is_32bit$16 1'0
+      update \logical_op__is_signed$17 1'0
+      update \logical_op__data_len$18 4'0000
+      update \logical_op__insn$19 32'00000000000000000000000000000000
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__imm_data__imm$4 \op__imm_data__imm$4$next
-      update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
-      update \op__rc__rc$6 \op__rc__rc$6$next
-      update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
-      update \op__oe__oe$8 \op__oe__oe$8$next
-      update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
-      update \op__invert_a$10 \op__invert_a$10$next
-      update \op__zero_a$11 \op__zero_a$11$next
-      update \op__input_carry$12 \op__input_carry$12$next
-      update \op__invert_out$13 \op__invert_out$13$next
-      update \op__write_cr0$14 \op__write_cr0$14$next
-      update \op__output_carry$15 \op__output_carry$15$next
-      update \op__is_32bit$16 \op__is_32bit$16$next
-      update \op__is_signed$17 \op__is_signed$17$next
-      update \op__data_len$18 \op__data_len$18$next
-      update \op__insn$19 \op__insn$19$next
+      update \logical_op__insn_type$2 \logical_op__insn_type$2$next
+      update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next
+      update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next
+      update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next
+      update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next
+      update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next
+      update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next
+      update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next
+      update \logical_op__invert_a$10 \logical_op__invert_a$10$next
+      update \logical_op__zero_a$11 \logical_op__zero_a$11$next
+      update \logical_op__input_carry$12 \logical_op__input_carry$12$next
+      update \logical_op__invert_out$13 \logical_op__invert_out$13$next
+      update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next
+      update \logical_op__output_carry$15 \logical_op__output_carry$15$next
+      update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next
+      update \logical_op__is_signed$17 \logical_op__is_signed$17$next
+      update \logical_op__data_len$18 \logical_op__data_len$18$next
+      update \logical_op__insn$19 \logical_op__insn$19$next
   end
   process $group_115
     assign \o$next \o
@@ -79499,21 +79573,21 @@ module \alu_logical0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 6 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 7 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 8 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 9 \xer_ca
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -79588,8 +79662,8 @@ module \alu_logical0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 10 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 10 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -79602,47 +79676,47 @@ module \alu_logical0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 11 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 12 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 11 \logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 12 \logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 20 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 21 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 22 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 23 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 24 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 25 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 26 \op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 27 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 20 \logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 21 \logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 22 \logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 23 \logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 24 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 25 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 26 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 27 \logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 28 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 29 \rb
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 30 \p_valid_i
@@ -79660,7 +79734,7 @@ module \alu_logical0
   wire width 1 \pipe_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -79735,8 +79809,8 @@ module \alu_logical0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -79749,53 +79823,53 @@ module \alu_logical0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \pipe_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \pipe_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_rb
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \pipe_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \pipe_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -79870,8 +79944,8 @@ module \alu_logical0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -79884,55 +79958,55 @@ module \alu_logical0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_logical_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_logical_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__zero_a$11
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \pipe_op__input_carry$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__invert_out$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__write_cr0$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_carry$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_signed$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \pipe_op__data_len$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_logical_op__input_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \pipe_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \pipe_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ca_ok
   cell \pipe$45 \pipe
     connect \rst \rst
@@ -79940,47 +80014,47 @@ module \alu_logical0
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
-    connect \op__insn_type \pipe_op__insn_type
-    connect \op__fn_unit \pipe_op__fn_unit
-    connect \op__imm_data__imm \pipe_op__imm_data__imm
-    connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
-    connect \op__rc__rc \pipe_op__rc__rc
-    connect \op__rc__rc_ok \pipe_op__rc__rc_ok
-    connect \op__oe__oe \pipe_op__oe__oe
-    connect \op__oe__oe_ok \pipe_op__oe__oe_ok
-    connect \op__invert_a \pipe_op__invert_a
-    connect \op__zero_a \pipe_op__zero_a
-    connect \op__input_carry \pipe_op__input_carry
-    connect \op__invert_out \pipe_op__invert_out
-    connect \op__write_cr0 \pipe_op__write_cr0
-    connect \op__output_carry \pipe_op__output_carry
-    connect \op__is_32bit \pipe_op__is_32bit
-    connect \op__is_signed \pipe_op__is_signed
-    connect \op__data_len \pipe_op__data_len
-    connect \op__insn \pipe_op__insn
+    connect \logical_op__insn_type \pipe_logical_op__insn_type
+    connect \logical_op__fn_unit \pipe_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \pipe_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \pipe_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \pipe_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \pipe_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \pipe_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \pipe_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \pipe_logical_op__invert_a
+    connect \logical_op__zero_a \pipe_logical_op__zero_a
+    connect \logical_op__input_carry \pipe_logical_op__input_carry
+    connect \logical_op__invert_out \pipe_logical_op__invert_out
+    connect \logical_op__write_cr0 \pipe_logical_op__write_cr0
+    connect \logical_op__output_carry \pipe_logical_op__output_carry
+    connect \logical_op__is_32bit \pipe_logical_op__is_32bit
+    connect \logical_op__is_signed \pipe_logical_op__is_signed
+    connect \logical_op__data_len \pipe_logical_op__data_len
+    connect \logical_op__insn \pipe_logical_op__insn
     connect \ra \pipe_ra
     connect \rb \pipe_rb
     connect \n_valid_o \pipe_n_valid_o
     connect \n_ready_i \pipe_n_ready_i
     connect \muxid$1 \pipe_muxid$1
-    connect \op__insn_type$2 \pipe_op__insn_type$2
-    connect \op__fn_unit$3 \pipe_op__fn_unit$3
-    connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$4
-    connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$5
-    connect \op__rc__rc$6 \pipe_op__rc__rc$6
-    connect \op__rc__rc_ok$7 \pipe_op__rc__rc_ok$7
-    connect \op__oe__oe$8 \pipe_op__oe__oe$8
-    connect \op__oe__oe_ok$9 \pipe_op__oe__oe_ok$9
-    connect \op__invert_a$10 \pipe_op__invert_a$10
-    connect \op__zero_a$11 \pipe_op__zero_a$11
-    connect \op__input_carry$12 \pipe_op__input_carry$12
-    connect \op__invert_out$13 \pipe_op__invert_out$13
-    connect \op__write_cr0$14 \pipe_op__write_cr0$14
-    connect \op__output_carry$15 \pipe_op__output_carry$15
-    connect \op__is_32bit$16 \pipe_op__is_32bit$16
-    connect \op__is_signed$17 \pipe_op__is_signed$17
-    connect \op__data_len$18 \pipe_op__data_len$18
-    connect \op__insn$19 \pipe_op__insn$19
+    connect \logical_op__insn_type$2 \pipe_logical_op__insn_type$2
+    connect \logical_op__fn_unit$3 \pipe_logical_op__fn_unit$3
+    connect \logical_op__imm_data__imm$4 \pipe_logical_op__imm_data__imm$4
+    connect \logical_op__imm_data__imm_ok$5 \pipe_logical_op__imm_data__imm_ok$5
+    connect \logical_op__rc__rc$6 \pipe_logical_op__rc__rc$6
+    connect \logical_op__rc__rc_ok$7 \pipe_logical_op__rc__rc_ok$7
+    connect \logical_op__oe__oe$8 \pipe_logical_op__oe__oe$8
+    connect \logical_op__oe__oe_ok$9 \pipe_logical_op__oe__oe_ok$9
+    connect \logical_op__invert_a$10 \pipe_logical_op__invert_a$10
+    connect \logical_op__zero_a$11 \pipe_logical_op__zero_a$11
+    connect \logical_op__input_carry$12 \pipe_logical_op__input_carry$12
+    connect \logical_op__invert_out$13 \pipe_logical_op__invert_out$13
+    connect \logical_op__write_cr0$14 \pipe_logical_op__write_cr0$14
+    connect \logical_op__output_carry$15 \pipe_logical_op__output_carry$15
+    connect \logical_op__is_32bit$16 \pipe_logical_op__is_32bit$16
+    connect \logical_op__is_signed$17 \pipe_logical_op__is_signed$17
+    connect \logical_op__data_len$18 \pipe_logical_op__data_len$18
+    connect \logical_op__insn$19 \pipe_logical_op__insn$19
     connect \o \pipe_o
     connect \o_ok \pipe_o_ok
     connect \cr_a \pipe_cr_a
@@ -79998,7 +80072,7 @@ module \alu_logical0
     assign \p_ready_o \pipe_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_2
     assign \pipe_muxid 2'00
@@ -80006,25 +80080,25 @@ module \alu_logical0
     sync init
   end
   process $group_3
-    assign \pipe_op__insn_type 7'0000000
-    assign \pipe_op__fn_unit 11'00000000000
-    assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_op__imm_data__imm_ok 1'0
-    assign \pipe_op__rc__rc 1'0
-    assign \pipe_op__rc__rc_ok 1'0
-    assign \pipe_op__oe__oe 1'0
-    assign \pipe_op__oe__oe_ok 1'0
-    assign \pipe_op__invert_a 1'0
-    assign \pipe_op__zero_a 1'0
-    assign \pipe_op__input_carry 2'00
-    assign \pipe_op__invert_out 1'0
-    assign \pipe_op__write_cr0 1'0
-    assign \pipe_op__output_carry 1'0
-    assign \pipe_op__is_32bit 1'0
-    assign \pipe_op__is_signed 1'0
-    assign \pipe_op__data_len 4'0000
-    assign \pipe_op__insn 32'00000000000000000000000000000000
-    assign { \pipe_op__insn \pipe_op__data_len \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_carry \pipe_op__write_cr0 \pipe_op__invert_out \pipe_op__input_carry \pipe_op__zero_a \pipe_op__invert_a { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \pipe_logical_op__insn_type 7'0000000
+    assign \pipe_logical_op__fn_unit 11'00000000000
+    assign \pipe_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_logical_op__imm_data__imm_ok 1'0
+    assign \pipe_logical_op__rc__rc 1'0
+    assign \pipe_logical_op__rc__rc_ok 1'0
+    assign \pipe_logical_op__oe__oe 1'0
+    assign \pipe_logical_op__oe__oe_ok 1'0
+    assign \pipe_logical_op__invert_a 1'0
+    assign \pipe_logical_op__zero_a 1'0
+    assign \pipe_logical_op__input_carry 2'00
+    assign \pipe_logical_op__invert_out 1'0
+    assign \pipe_logical_op__write_cr0 1'0
+    assign \pipe_logical_op__output_carry 1'0
+    assign \pipe_logical_op__is_32bit 1'0
+    assign \pipe_logical_op__is_signed 1'0
+    assign \pipe_logical_op__data_len 4'0000
+    assign \pipe_logical_op__insn 32'00000000000000000000000000000000
+    assign { \pipe_logical_op__insn \pipe_logical_op__data_len \pipe_logical_op__is_signed \pipe_logical_op__is_32bit \pipe_logical_op__output_carry \pipe_logical_op__write_cr0 \pipe_logical_op__invert_out \pipe_logical_op__input_carry \pipe_logical_op__zero_a \pipe_logical_op__invert_a { \pipe_logical_op__oe__oe_ok \pipe_logical_op__oe__oe } { \pipe_logical_op__rc__rc_ok \pipe_logical_op__rc__rc } { \pipe_logical_op__imm_data__imm_ok \pipe_logical_op__imm_data__imm } \pipe_logical_op__fn_unit \pipe_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
   process $group_21
@@ -80047,7 +80121,7 @@ module \alu_logical0
     assign \pipe_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$20
   process $group_25
     assign \muxid$20 2'00
@@ -80127,8 +80201,8 @@ module \alu_logical0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \logical_op__insn_type$21
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -80141,64 +80215,64 @@ module \alu_logical0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \logical_op__fn_unit$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \logical_op__imm_data__imm$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__imm_data__imm_ok$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__rc__rc$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__rc__rc_ok$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__oe__oe$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__oe__oe_ok$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_a$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__zero_a$30
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \op__data_len$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \logical_op__input_carry$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_out$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__write_cr0$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__output_carry$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_32bit$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_signed$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \logical_op__data_len$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \logical_op__insn$38
   process $group_26
-    assign \op__insn_type$21 7'0000000
-    assign \op__fn_unit$22 11'00000000000
-    assign \op__imm_data__imm$23 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$24 1'0
-    assign \op__rc__rc$25 1'0
-    assign \op__rc__rc_ok$26 1'0
-    assign \op__oe__oe$27 1'0
-    assign \op__oe__oe_ok$28 1'0
-    assign \op__invert_a$29 1'0
-    assign \op__zero_a$30 1'0
-    assign \op__input_carry$31 2'00
-    assign \op__invert_out$32 1'0
-    assign \op__write_cr0$33 1'0
-    assign \op__output_carry$34 1'0
-    assign \op__is_32bit$35 1'0
-    assign \op__is_signed$36 1'0
-    assign \op__data_len$37 4'0000
-    assign \op__insn$38 32'00000000000000000000000000000000
-    assign { \op__insn$38 \op__data_len$37 \op__is_signed$36 \op__is_32bit$35 \op__output_carry$34 \op__write_cr0$33 \op__invert_out$32 \op__input_carry$31 \op__zero_a$30 \op__invert_a$29 { \op__oe__oe_ok$28 \op__oe__oe$27 } { \op__rc__rc_ok$26 \op__rc__rc$25 } { \op__imm_data__imm_ok$24 \op__imm_data__imm$23 } \op__fn_unit$22 \op__insn_type$21 } { \pipe_op__insn$19 \pipe_op__data_len$18 \pipe_op__is_signed$17 \pipe_op__is_32bit$16 \pipe_op__output_carry$15 \pipe_op__write_cr0$14 \pipe_op__invert_out$13 \pipe_op__input_carry$12 \pipe_op__zero_a$11 \pipe_op__invert_a$10 { \pipe_op__oe__oe_ok$9 \pipe_op__oe__oe$8 } { \pipe_op__rc__rc_ok$7 \pipe_op__rc__rc$6 } { \pipe_op__imm_data__imm_ok$5 \pipe_op__imm_data__imm$4 } \pipe_op__fn_unit$3 \pipe_op__insn_type$2 }
+    assign \logical_op__insn_type$21 7'0000000
+    assign \logical_op__fn_unit$22 11'00000000000
+    assign \logical_op__imm_data__imm$23 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$24 1'0
+    assign \logical_op__rc__rc$25 1'0
+    assign \logical_op__rc__rc_ok$26 1'0
+    assign \logical_op__oe__oe$27 1'0
+    assign \logical_op__oe__oe_ok$28 1'0
+    assign \logical_op__invert_a$29 1'0
+    assign \logical_op__zero_a$30 1'0
+    assign \logical_op__input_carry$31 2'00
+    assign \logical_op__invert_out$32 1'0
+    assign \logical_op__write_cr0$33 1'0
+    assign \logical_op__output_carry$34 1'0
+    assign \logical_op__is_32bit$35 1'0
+    assign \logical_op__is_signed$36 1'0
+    assign \logical_op__data_len$37 4'0000
+    assign \logical_op__insn$38 32'00000000000000000000000000000000
+    assign { \logical_op__insn$38 \logical_op__data_len$37 \logical_op__is_signed$36 \logical_op__is_32bit$35 \logical_op__output_carry$34 \logical_op__write_cr0$33 \logical_op__invert_out$32 \logical_op__input_carry$31 \logical_op__zero_a$30 \logical_op__invert_a$29 { \logical_op__oe__oe_ok$28 \logical_op__oe__oe$27 } { \logical_op__rc__rc_ok$26 \logical_op__rc__rc$25 } { \logical_op__imm_data__imm_ok$24 \logical_op__imm_data__imm$23 } \logical_op__fn_unit$22 \logical_op__insn_type$21 } { \pipe_logical_op__insn$19 \pipe_logical_op__data_len$18 \pipe_logical_op__is_signed$17 \pipe_logical_op__is_32bit$16 \pipe_logical_op__output_carry$15 \pipe_logical_op__write_cr0$14 \pipe_logical_op__invert_out$13 \pipe_logical_op__input_carry$12 \pipe_logical_op__zero_a$11 \pipe_logical_op__invert_a$10 { \pipe_logical_op__oe__oe_ok$9 \pipe_logical_op__oe__oe$8 } { \pipe_logical_op__rc__rc_ok$7 \pipe_logical_op__rc__rc$6 } { \pipe_logical_op__imm_data__imm_ok$5 \pipe_logical_op__imm_data__imm$4 } \pipe_logical_op__fn_unit$3 \pipe_logical_op__insn_type$2 }
     sync init
   end
   process $group_44
@@ -81316,8 +81390,8 @@ module \logical0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \oper_i_alu_logical0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -81330,87 +81404,87 @@ module \logical0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 4 \oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \oper_i__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \oper_i__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \oper_i__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \oper_i__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \oper_i__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \oper_i__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \oper_i_alu_logical0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 4 \oper_i_alu_logical0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \oper_i_alu_logical0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \oper_i_alu_logical0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_alu_logical0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_alu_logical0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_alu_logical0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \oper_i_alu_logical0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_alu_logical0__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 12 \oper_i__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \oper_i__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \oper_i__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \oper_i__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \oper_i__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 18 \oper_i__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 19 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 20 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 12 \oper_i_alu_logical0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_alu_logical0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_alu_logical0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_alu_logical0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \oper_i_alu_logical0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \oper_i_alu_logical0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 18 \oper_i_alu_logical0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 19 \oper_i_alu_logical0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 21 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 2 input 22 \rdmaskn
+  wire width 1 input 20 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 21 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 2 input 22 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 23 \rd__rel
+  wire width 2 output 23 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 input 24 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 2 input 24 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 25 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 26 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 28 \wr__rel
+  wire width 3 output 28 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 29 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 3 input 29 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 30 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 31 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 output 32 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 34 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 35 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 36 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 35 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 36 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_logical0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_logical0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_logical0_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \alu_logical0_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \alu_logical0_xer_ca
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -81485,8 +81559,8 @@ module \logical0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_logical0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_logical0_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -81499,47 +81573,47 @@ module \logical0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_logical0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_logical0_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_logical0_logical_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_logical0_logical_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \alu_logical0_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_logical0_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 \alu_logical0_op__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_logical0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \alu_logical0_logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_logical0_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \alu_logical0_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_logical0_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_logical0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_logical0_rb
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_logical0_p_valid_i
@@ -81556,24 +81630,24 @@ module \logical0
     connect \o \alu_logical0_o
     connect \cr_a \alu_logical0_cr_a
     connect \xer_ca \alu_logical0_xer_ca
-    connect \op__insn_type \alu_logical0_op__insn_type
-    connect \op__fn_unit \alu_logical0_op__fn_unit
-    connect \op__imm_data__imm \alu_logical0_op__imm_data__imm
-    connect \op__imm_data__imm_ok \alu_logical0_op__imm_data__imm_ok
-    connect \op__rc__rc \alu_logical0_op__rc__rc
-    connect \op__rc__rc_ok \alu_logical0_op__rc__rc_ok
-    connect \op__oe__oe \alu_logical0_op__oe__oe
-    connect \op__oe__oe_ok \alu_logical0_op__oe__oe_ok
-    connect \op__invert_a \alu_logical0_op__invert_a
-    connect \op__zero_a \alu_logical0_op__zero_a
-    connect \op__input_carry \alu_logical0_op__input_carry
-    connect \op__invert_out \alu_logical0_op__invert_out
-    connect \op__write_cr0 \alu_logical0_op__write_cr0
-    connect \op__output_carry \alu_logical0_op__output_carry
-    connect \op__is_32bit \alu_logical0_op__is_32bit
-    connect \op__is_signed \alu_logical0_op__is_signed
-    connect \op__data_len \alu_logical0_op__data_len
-    connect \op__insn \alu_logical0_op__insn
+    connect \logical_op__insn_type \alu_logical0_logical_op__insn_type
+    connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \alu_logical0_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \alu_logical0_logical_op__invert_a
+    connect \logical_op__zero_a \alu_logical0_logical_op__zero_a
+    connect \logical_op__input_carry \alu_logical0_logical_op__input_carry
+    connect \logical_op__invert_out \alu_logical0_logical_op__invert_out
+    connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0
+    connect \logical_op__output_carry \alu_logical0_logical_op__output_carry
+    connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit
+    connect \logical_op__is_signed \alu_logical0_logical_op__is_signed
+    connect \logical_op__data_len \alu_logical0_logical_op__data_len
+    connect \logical_op__insn \alu_logical0_logical_op__insn
     connect \ra \alu_logical0_ra
     connect \rb \alu_logical0_rb
     connect \p_valid_i \alu_logical0_p_valid_i
@@ -81681,36 +81755,36 @@ module \logical0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 2 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 2 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -81718,10 +81792,10 @@ module \logical0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A $4
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $6
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -81729,9 +81803,9 @@ module \logical0
     connect \A $6
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81747,9 +81821,9 @@ module \logical0
     assign \all_rd $9
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -81759,11 +81833,11 @@ module \logical0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81771,9 +81845,9 @@ module \logical0
     connect \A \all_rd_dly
     connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81789,16 +81863,16 @@ module \logical0
     assign \all_rd_pulse $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_logical0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -81808,11 +81882,11 @@ module \logical0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81820,9 +81894,9 @@ module \logical0
     connect \A \alu_done_dly
     connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81838,28 +81912,28 @@ module \logical0
     assign \alu_pulse $17
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 3 \alu_pulsem
   process $group_6
     assign \alu_pulsem 3'000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 3 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $19
   end
   process $group_7
@@ -81875,38 +81949,38 @@ module \logical0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 3 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 3 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $23
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -81914,7 +81988,7 @@ module \logical0
     connect \A $25
     connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81922,39 +81996,39 @@ module \logical0
     connect \A $22
     connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $21
     connect \Y $29
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $29
+    assign \cu_done_o 1'0
+    assign \cu_done_o $29
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -81962,9 +82036,9 @@ module \logical0
     connect \A \prev_wr_go
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81980,11 +82054,11 @@ module \logical0
     assign \wr_any $35
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -81992,9 +82066,9 @@ module \logical0
     connect \A \alu_logical0_n_ready_i
     connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82005,9 +82079,9 @@ module \logical0
     connect \B $37
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 3 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -82015,12 +82089,12 @@ module \logical0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -82031,9 +82105,9 @@ module \logical0
     connect \B 1'0
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82044,22 +82118,22 @@ module \logical0
     connect \B $43
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82070,9 +82144,9 @@ module \logical0
     connect \B \alu_logical0_n_ready_i
     connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82083,9 +82157,9 @@ module \logical0
     connect \B \alu_logical0_n_valid_o
     connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82093,25 +82167,25 @@ module \logical0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $51
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $53
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $45
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $53 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82119,7 +82193,7 @@ module \logical0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $55
   end
   process $group_11
@@ -82127,19 +82201,19 @@ module \logical0
     assign \reset $55
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $57
   end
   process $group_12
@@ -82147,19 +82221,19 @@ module \logical0
     assign \rst_r $57
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 3 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 3 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $59
   end
   process $group_13
@@ -82167,19 +82241,19 @@ module \logical0
     assign \reset_w $59
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 2 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 2 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i }
     connect \Y $61
   end
   process $group_14
@@ -82189,12 +82263,12 @@ module \logical0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82202,7 +82276,7 @@ module \logical0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_logical0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $63
   end
   process $group_16
@@ -82230,7 +82304,7 @@ module \logical0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -82256,7 +82330,7 @@ module \logical0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -82280,9 +82354,9 @@ module \logical0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 3 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -82290,7 +82364,7 @@ module \logical0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $65
   end
   process $group_23
@@ -82298,9 +82372,9 @@ module \logical0
     assign \req_l_s_req $65
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 3 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -82389,7 +82463,7 @@ module \logical0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -82403,43 +82477,43 @@ module \logical0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 2 \oper_r__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 4 \oper_r__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -82519,8 +82593,8 @@ module \logical0
   cell $mux $70
     parameter \WIDTH 132
     connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_a { \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type }
+    connect \S \cu_issue_i
     connect \Y $69
   end
   process $group_25
@@ -82565,10 +82639,10 @@ module \logical0
     assign \oper_l__data_len$next \oper_l__data_len
     assign \oper_l__insn$next \oper_l__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+        assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_a { \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -82619,9 +82693,9 @@ module \logical0
       update \oper_l__data_len \oper_l__data_len$next
       update \oper_l__insn \oper_l__insn$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__o_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__o
@@ -82688,9 +82762,9 @@ module \logical0
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 4 \data_r1__cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 4 \data_r1_l__cr_a
@@ -82757,9 +82831,9 @@ module \logical0
       update \data_r1_l__cr_a \data_r1_l__cr_a$next
       update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 2 \data_r2__xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \data_r2_l__xer_ca
@@ -82826,9 +82900,9 @@ module \logical0
       update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
       update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $90
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82836,12 +82910,12 @@ module \logical0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__o_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $89
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $92
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82849,12 +82923,12 @@ module \logical0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__cr_a_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $94
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -82862,41 +82936,41 @@ module \logical0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__xer_ca_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $93
   end
   process $group_73
-    assign \wrmask 3'000
-    assign \wrmask { $93 $91 $89 }
+    assign \cu_wrmask_o 3'000
+    assign \cu_wrmask_o { $93 $91 $89 }
     sync init
   end
   process $group_74
-    assign \alu_logical0_op__insn_type 7'0000000
-    assign \alu_logical0_op__fn_unit 11'00000000000
-    assign \alu_logical0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_logical0_op__imm_data__imm_ok 1'0
-    assign \alu_logical0_op__rc__rc 1'0
-    assign \alu_logical0_op__rc__rc_ok 1'0
-    assign \alu_logical0_op__oe__oe 1'0
-    assign \alu_logical0_op__oe__oe_ok 1'0
-    assign \alu_logical0_op__invert_a 1'0
-    assign \alu_logical0_op__zero_a 1'0
-    assign \alu_logical0_op__input_carry 2'00
-    assign \alu_logical0_op__invert_out 1'0
-    assign \alu_logical0_op__write_cr0 1'0
-    assign \alu_logical0_op__output_carry 1'0
-    assign \alu_logical0_op__is_32bit 1'0
-    assign \alu_logical0_op__is_signed 1'0
-    assign \alu_logical0_op__data_len 4'0000
-    assign \alu_logical0_op__insn 32'00000000000000000000000000000000
-    assign { \alu_logical0_op__insn \alu_logical0_op__data_len \alu_logical0_op__is_signed \alu_logical0_op__is_32bit \alu_logical0_op__output_carry \alu_logical0_op__write_cr0 \alu_logical0_op__invert_out \alu_logical0_op__input_carry \alu_logical0_op__zero_a \alu_logical0_op__invert_a { \alu_logical0_op__oe__oe_ok \alu_logical0_op__oe__oe } { \alu_logical0_op__rc__rc_ok \alu_logical0_op__rc__rc } { \alu_logical0_op__imm_data__imm_ok \alu_logical0_op__imm_data__imm } \alu_logical0_op__fn_unit \alu_logical0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+    assign \alu_logical0_logical_op__insn_type 7'0000000
+    assign \alu_logical0_logical_op__fn_unit 11'00000000000
+    assign \alu_logical0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_logical0_logical_op__imm_data__imm_ok 1'0
+    assign \alu_logical0_logical_op__rc__rc 1'0
+    assign \alu_logical0_logical_op__rc__rc_ok 1'0
+    assign \alu_logical0_logical_op__oe__oe 1'0
+    assign \alu_logical0_logical_op__oe__oe_ok 1'0
+    assign \alu_logical0_logical_op__invert_a 1'0
+    assign \alu_logical0_logical_op__zero_a 1'0
+    assign \alu_logical0_logical_op__input_carry 2'00
+    assign \alu_logical0_logical_op__invert_out 1'0
+    assign \alu_logical0_logical_op__write_cr0 1'0
+    assign \alu_logical0_logical_op__output_carry 1'0
+    assign \alu_logical0_logical_op__is_32bit 1'0
+    assign \alu_logical0_logical_op__is_signed 1'0
+    assign \alu_logical0_logical_op__data_len 4'0000
+    assign \alu_logical0_logical_op__insn 32'00000000000000000000000000000000
+    assign { \alu_logical0_logical_op__insn \alu_logical0_logical_op__data_len \alu_logical0_logical_op__is_signed \alu_logical0_logical_op__is_32bit \alu_logical0_logical_op__output_carry \alu_logical0_logical_op__write_cr0 \alu_logical0_logical_op__invert_out \alu_logical0_logical_op__input_carry \alu_logical0_logical_op__zero_a \alu_logical0_logical_op__invert_a { \alu_logical0_logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe } { \alu_logical0_logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc } { \alu_logical0_logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm } \alu_logical0_logical_op__fn_unit \alu_logical0_logical_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $96
     parameter \WIDTH 1
     connect \A \src_l_q_src [0]
@@ -82909,11 +82983,11 @@ module \logical0
     assign \src_sel $95
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $98
     parameter \WIDTH 64
     connect \A \src1_i
@@ -82926,11 +83000,11 @@ module \logical0
     assign \src_or_imm $97
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $101
     parameter \WIDTH 1
     connect \A \src_l_q_src [1]
@@ -82943,11 +83017,11 @@ module \logical0
     assign \src_sel$99 $100
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $104
     parameter \WIDTH 64
     connect \A \src2_i
@@ -83029,9 +83103,9 @@ module \logical0
     assign \alu_logical0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -83065,9 +83139,9 @@ module \logical0
     assign \alu_logical0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -83097,13 +83171,13 @@ module \logical0
     sync init
   end
   process $group_106
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 2 $113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -83111,12 +83185,12 @@ module \logical0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o }
     connect \Y $113
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -83124,9 +83198,9 @@ module \logical0
     connect \A \oper_r__zero_a
     connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -83134,9 +83208,9 @@ module \logical0
     connect \A \oper_r__imm_data__imm_ok
     connect \Y $117
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 2 $119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -83147,19 +83221,19 @@ module \logical0
     connect \B { $117 $115 }
     connect \Y $119
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 2 $121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $121
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 2 $123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -83171,52 +83245,52 @@ module \logical0
     connect \Y $123
   end
   process $group_107
-    assign \rd__rel 2'00
-    assign \rd__rel $123
+    assign \cu_rd__rel_o 2'00
+    assign \cu_rd__rel_o $123
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $125
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $127
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $129
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -83227,9 +83301,9 @@ module \logical0
     connect \B { $125 $127 $129 }
     connect \Y $131
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $134
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -83237,78 +83311,78 @@ module \logical0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A $131
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $133
   end
   process $group_108
-    assign \wr__rel 3'000
-    assign \wr__rel $133
+    assign \cu_wr__rel_o 3'000
+    assign \cu_wr__rel_o $133
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $135
   end
   process $group_109
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $135 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $137
   end
   process $group_110
     assign \dest2_o 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $137 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $139
   end
   process $group_111
     assign \dest3_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $139 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
     end
@@ -83352,9 +83426,9 @@ module \n$59
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -83408,9 +83482,9 @@ module \n$62
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -83430,7 +83504,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main"
 module \spr_main
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -83505,8 +83579,8 @@ module \spr_main
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \spr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -83519,23 +83593,23 @@ module \spr_main
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 3 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \spr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 3 \spr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \spr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 5 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 6 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 7 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 8 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 9 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 10 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -83610,8 +83684,8 @@ module \spr_main
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 11 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 11 \spr_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -83624,43 +83698,43 @@ module \spr_main
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 12 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 13 \op__insn$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 14 \op__is_32bit$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 12 \spr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 13 \spr_op__insn$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 14 \spr_op__is_32bit$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 15 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 16 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 17 \fast1$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 18 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 19 \xer_so$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 20 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 21 \xer_ov$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 22 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 23 \xer_ca$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 24 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42"
   wire width 10 \spr
   process $group_0
     assign \spr 10'0000000000
-    assign \spr { { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] } { \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] } }
+    assign \spr { { \spr_op__insn [15] \spr_op__insn [14] \spr_op__insn [13] \spr_op__insn [12] \spr_op__insn [11] } { \spr_op__insn [20] \spr_op__insn [19] \spr_op__insn [18] \spr_op__insn [17] \spr_op__insn [16] } }
     sync init
   end
   process $group_1
     assign \fast1$6 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83681,7 +83755,7 @@ module \spr_main
   process $group_2
     assign \fast1_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83702,7 +83776,7 @@ module \spr_main
   process $group_3
     assign \xer_so$7 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83723,7 +83797,7 @@ module \spr_main
   process $group_4
     assign \xer_so_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83744,7 +83818,7 @@ module \spr_main
   process $group_5
     assign \xer_ov$8 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83766,7 +83840,7 @@ module \spr_main
   process $group_6
     assign \xer_ov_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83787,7 +83861,7 @@ module \spr_main
   process $group_7
     assign \xer_ca$9 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83809,7 +83883,7 @@ module \spr_main
   process $group_8
     assign \xer_ca_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83831,7 +83905,7 @@ module \spr_main
     assign \o_ok 1'0
     assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46"
-    switch \op__insn_type
+    switch \spr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48"
       attribute \nmigen.decoding "OP_MTSPR/49"
       case 7'0110001
@@ -83861,11 +83935,11 @@ module \spr_main
     sync init
   end
   process $group_12
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__insn$4 32'00000000000000000000000000000000
-    assign \op__is_32bit$5 1'0
-    assign { \op__is_32bit$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
+    assign \spr_op__insn_type$2 7'0000000
+    assign \spr_op__fn_unit$3 11'00000000000
+    assign \spr_op__insn$4 32'00000000000000000000000000000000
+    assign \spr_op__is_32bit$5 1'0
+    assign { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
     sync init
   end
 end
@@ -83880,7 +83954,7 @@ module \pipe$60
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -83955,8 +84029,8 @@ module \pipe$60
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \spr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -83969,31 +84043,31 @@ module \pipe$60
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 7 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \spr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 7 \spr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \spr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 9 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 10 \spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 11 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 12 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 13 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 14 \xer_ca
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 15 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 16 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 17 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -84068,10 +84142,10 @@ module \pipe$60
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 18 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 18 \spr_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \spr_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -84084,65 +84158,65 @@ module \pipe$60
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 19 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 20 \op__insn$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 21 \op__is_32bit$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 19 \spr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \spr_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 20 \spr_op__insn$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \spr_op__insn$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 21 \spr_op__is_32bit$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \spr_op__is_32bit$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 22 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 23 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 24 \spr1$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \spr1$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 25 \spr1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr1_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 26 \fast1$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast1$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast1_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 28 \xer_so$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 30 \xer_ov$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ov$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 31 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 32 \xer_ca$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$next
   cell \p$61 \p
     connect \p_valid_i \p_valid_i
@@ -84152,7 +84226,7 @@ module \pipe$60
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \spr_main_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -84227,8 +84301,8 @@ module \pipe$60
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \spr_main_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \spr_main_spr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -84241,23 +84315,23 @@ module \pipe$60
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \spr_main_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \spr_main_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \spr_main_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \spr_main_spr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \spr_main_spr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \spr_main_spr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \spr_main_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \spr_main_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \spr_main_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \spr_main_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \spr_main_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \spr_main_muxid$11
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -84332,8 +84406,8 @@ module \pipe$60
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \spr_main_op__insn_type$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \spr_main_spr_op__insn_type$12
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -84346,48 +84420,48 @@ module \pipe$60
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \spr_main_op__fn_unit$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \spr_main_op__insn$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \spr_main_op__is_32bit$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \spr_main_spr_op__fn_unit$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \spr_main_spr_op__insn$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \spr_main_spr_op__is_32bit$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \spr_main_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr_main_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \spr_main_fast1$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr_main_fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr_main_xer_so$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr_main_xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \spr_main_xer_ov$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr_main_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \spr_main_xer_ca$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr_main_xer_ca_ok
   cell \spr_main \spr_main
     connect \muxid \spr_main_muxid
-    connect \op__insn_type \spr_main_op__insn_type
-    connect \op__fn_unit \spr_main_op__fn_unit
-    connect \op__insn \spr_main_op__insn
-    connect \op__is_32bit \spr_main_op__is_32bit
+    connect \spr_op__insn_type \spr_main_spr_op__insn_type
+    connect \spr_op__fn_unit \spr_main_spr_op__fn_unit
+    connect \spr_op__insn \spr_main_spr_op__insn
+    connect \spr_op__is_32bit \spr_main_spr_op__is_32bit
     connect \ra \spr_main_ra
     connect \fast1 \spr_main_fast1
     connect \xer_so \spr_main_xer_so
     connect \xer_ov \spr_main_xer_ov
     connect \xer_ca \spr_main_xer_ca
     connect \muxid$1 \spr_main_muxid$11
-    connect \op__insn_type$2 \spr_main_op__insn_type$12
-    connect \op__fn_unit$3 \spr_main_op__fn_unit$13
-    connect \op__insn$4 \spr_main_op__insn$14
-    connect \op__is_32bit$5 \spr_main_op__is_32bit$15
+    connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12
+    connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13
+    connect \spr_op__insn$4 \spr_main_spr_op__insn$14
+    connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15
     connect \o \spr_main_o
     connect \o_ok \spr_main_o_ok
     connect \fast1$6 \spr_main_fast1$16
@@ -84405,11 +84479,11 @@ module \pipe$60
     sync init
   end
   process $group_1
-    assign \spr_main_op__insn_type 7'0000000
-    assign \spr_main_op__fn_unit 11'00000000000
-    assign \spr_main_op__insn 32'00000000000000000000000000000000
-    assign \spr_main_op__is_32bit 1'0
-    assign { \spr_main_op__is_32bit \spr_main_op__insn \spr_main_op__fn_unit \spr_main_op__insn_type } { \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
+    assign \spr_main_spr_op__insn_type 7'0000000
+    assign \spr_main_spr_op__fn_unit 11'00000000000
+    assign \spr_main_spr_op__insn 32'00000000000000000000000000000000
+    assign \spr_main_spr_op__is_32bit 1'0
+    assign { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
     sync init
   end
   process $group_5
@@ -84417,7 +84491,7 @@ module \pipe$60
     assign \spr_main_ra \ra
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \spr1$20
   process $group_6
     assign \spr1$20 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -84478,7 +84552,7 @@ module \pipe$60
     assign \p_valid_i_p_ready_o $22
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$24
   process $group_14
     assign \muxid$24 2'00
@@ -84558,8 +84632,8 @@ module \pipe$60
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \spr_op__insn_type$25
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -84572,23 +84646,23 @@ module \pipe$60
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \spr_op__fn_unit$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \spr_op__insn$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \spr_op__is_32bit$28
   process $group_15
-    assign \op__insn_type$25 7'0000000
-    assign \op__fn_unit$26 11'00000000000
-    assign \op__insn$27 32'00000000000000000000000000000000
-    assign \op__is_32bit$28 1'0
-    assign { \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 } { \spr_main_op__is_32bit$15 \spr_main_op__insn$14 \spr_main_op__fn_unit$13 \spr_main_op__insn_type$12 }
+    assign \spr_op__insn_type$25 7'0000000
+    assign \spr_op__fn_unit$26 11'00000000000
+    assign \spr_op__insn$27 32'00000000000000000000000000000000
+    assign \spr_op__is_32bit$28 1'0
+    assign { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$30
   process $group_19
     assign \o$29 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -84596,13 +84670,13 @@ module \pipe$60
     assign { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \spr1$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr1_ok$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \spr1$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \spr1_ok$34
   process $group_21
     assign \spr1$31 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -84610,9 +84684,9 @@ module \pipe$60
     assign { \spr1_ok$32 \spr1$31 } { \spr1_ok$34 \spr1$33 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fast1$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fast1_ok$36
   process $group_23
     assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -84620,9 +84694,9 @@ module \pipe$60
     assign { \fast1_ok$36 \fast1$35 } { \spr_main_fast1_ok \spr_main_fast1$16 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$38
   process $group_25
     assign \xer_so$37 1'0
@@ -84630,9 +84704,9 @@ module \pipe$60
     assign { \xer_so_ok$38 \xer_so$37 } { \spr_main_xer_so_ok \spr_main_xer_so$17 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ov$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$40
   process $group_27
     assign \xer_ov$39 2'00
@@ -84640,9 +84714,9 @@ module \pipe$60
     assign { \xer_ov_ok$40 \xer_ov$39 } { \spr_main_xer_ov_ok \spr_main_xer_ov$18 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$42
   process $group_29
     assign \xer_ca$41 2'00
@@ -84692,29 +84766,29 @@ module \pipe$60
       update \muxid$1 \muxid$1$next
   end
   process $group_33
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__insn$4$next \op__insn$4
-    assign \op__is_32bit$5$next \op__is_32bit$5
+    assign \spr_op__insn_type$2$next \spr_op__insn_type$2
+    assign \spr_op__fn_unit$3$next \spr_op__fn_unit$3
+    assign \spr_op__insn$4$next \spr_op__insn$4
+    assign \spr_op__is_32bit$5$next \spr_op__is_32bit$5
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 }
+        assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 }
+        assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 }
     end
     sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__insn$4 32'00000000000000000000000000000000
-      update \op__is_32bit$5 1'0
+      update \spr_op__insn_type$2 7'0000000
+      update \spr_op__fn_unit$3 11'00000000000
+      update \spr_op__insn$4 32'00000000000000000000000000000000
+      update \spr_op__is_32bit$5 1'0
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__insn$4 \op__insn$4$next
-      update \op__is_32bit$5 \op__is_32bit$5$next
+      update \spr_op__insn_type$2 \spr_op__insn_type$2$next
+      update \spr_op__fn_unit$3 \spr_op__fn_unit$3$next
+      update \spr_op__insn$4 \spr_op__insn$4$next
+      update \spr_op__is_32bit$5 \spr_op__is_32bit$5$next
   end
   process $group_37
     assign \o$next \o
@@ -84880,33 +84954,33 @@ module \alu_spr0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 6 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 7 \spr1_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 8 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 9 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 10 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 11 \spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 12 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 13 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 14 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 15 \xer_ca
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -84981,8 +85055,8 @@ module \alu_spr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 16 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 16 \spr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -84995,23 +85069,23 @@ module \alu_spr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 17 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 18 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 17 \spr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \spr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \spr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 20 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 21 \spr1$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 22 \fast1$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 23 \xer_so$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 24 \xer_ov$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 25 \xer_ca$5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 26 \p_valid_i
@@ -85029,7 +85103,7 @@ module \alu_spr0
   wire width 1 \pipe_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -85104,8 +85178,8 @@ module \alu_spr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_spr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -85118,29 +85192,29 @@ module \alu_spr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_spr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_spr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_spr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \pipe_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \pipe_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \pipe_xer_ca
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \pipe_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \pipe_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid$6
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -85215,8 +85289,8 @@ module \alu_spr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_spr_op__insn_type$7
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -85229,35 +85303,35 @@ module \alu_spr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_spr_op__fn_unit$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_spr_op__insn$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_spr_op__is_32bit$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_spr1$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_spr1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_fast1$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_so$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \pipe_xer_ov$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \pipe_xer_ca$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ca_ok
   cell \pipe$60 \pipe
     connect \rst \rst
@@ -85265,10 +85339,10 @@ module \alu_spr0
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
-    connect \op__insn_type \pipe_op__insn_type
-    connect \op__fn_unit \pipe_op__fn_unit
-    connect \op__insn \pipe_op__insn
-    connect \op__is_32bit \pipe_op__is_32bit
+    connect \spr_op__insn_type \pipe_spr_op__insn_type
+    connect \spr_op__fn_unit \pipe_spr_op__fn_unit
+    connect \spr_op__insn \pipe_spr_op__insn
+    connect \spr_op__is_32bit \pipe_spr_op__is_32bit
     connect \ra \pipe_ra
     connect \spr1 \pipe_spr1
     connect \fast1 \pipe_fast1
@@ -85278,10 +85352,10 @@ module \alu_spr0
     connect \n_valid_o \pipe_n_valid_o
     connect \n_ready_i \pipe_n_ready_i
     connect \muxid$1 \pipe_muxid$6
-    connect \op__insn_type$2 \pipe_op__insn_type$7
-    connect \op__fn_unit$3 \pipe_op__fn_unit$8
-    connect \op__insn$4 \pipe_op__insn$9
-    connect \op__is_32bit$5 \pipe_op__is_32bit$10
+    connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7
+    connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8
+    connect \spr_op__insn$4 \pipe_spr_op__insn$9
+    connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10
     connect \o \pipe_o
     connect \o_ok \pipe_o_ok
     connect \spr1$6 \pipe_spr1$11
@@ -85305,7 +85379,7 @@ module \alu_spr0
     assign \p_ready_o \pipe_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_2
     assign \pipe_muxid 2'00
@@ -85313,11 +85387,11 @@ module \alu_spr0
     sync init
   end
   process $group_3
-    assign \pipe_op__insn_type 7'0000000
-    assign \pipe_op__fn_unit 11'00000000000
-    assign \pipe_op__insn 32'00000000000000000000000000000000
-    assign \pipe_op__is_32bit 1'0
-    assign { \pipe_op__is_32bit \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
+    assign \pipe_spr_op__insn_type 7'0000000
+    assign \pipe_spr_op__fn_unit 11'00000000000
+    assign \pipe_spr_op__insn 32'00000000000000000000000000000000
+    assign \pipe_spr_op__is_32bit 1'0
+    assign { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type }
     sync init
   end
   process $group_7
@@ -85360,7 +85434,7 @@ module \alu_spr0
     assign \pipe_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$16
   process $group_15
     assign \muxid$16 2'00
@@ -85440,8 +85514,8 @@ module \alu_spr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \spr_op__insn_type$17
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -85454,18 +85528,18 @@ module \alu_spr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \spr_op__fn_unit$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \spr_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \spr_op__is_32bit$20
   process $group_16
-    assign \op__insn_type$17 7'0000000
-    assign \op__fn_unit$18 11'00000000000
-    assign \op__insn$19 32'00000000000000000000000000000000
-    assign \op__is_32bit$20 1'0
-    assign { \op__is_32bit$20 \op__insn$19 \op__fn_unit$18 \op__insn_type$17 } { \pipe_op__is_32bit$10 \pipe_op__insn$9 \pipe_op__fn_unit$8 \pipe_op__insn_type$7 }
+    assign \spr_op__insn_type$17 7'0000000
+    assign \spr_op__fn_unit$18 11'00000000000
+    assign \spr_op__insn$19 32'00000000000000000000000000000000
+    assign \spr_op__is_32bit$20 1'0
+    assign { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 }
     sync init
   end
   process $group_20
@@ -86601,8 +86675,8 @@ module \spr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \oper_i_alu_spr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -86615,81 +86689,81 @@ module \spr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 4 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 6 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \oper_i_alu_spr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 4 \oper_i_alu_spr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \oper_i_alu_spr0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 7 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 6 input 8 \rdmaskn
+  wire width 1 input 6 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 7 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 input 8 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 9 \rd__rel
+  wire width 6 output 9 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 10 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 6 input 10 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 11 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 1 input 12 \src4_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 input 13 \src6_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 input 14 \src5_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 15 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 16 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 17 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 18 \wr__rel
+  wire width 6 output 18 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 19 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 6 input 19 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 20 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 21 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 22 \dest6_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 23 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 24 \dest5_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 25 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 26 \dest4_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 28 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \spr1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 30 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 31 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 32 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 31 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 32 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_spr0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_spr0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_spr0_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_spr0_spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_spr0_fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \alu_spr0_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \alu_spr0_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \alu_spr0_xer_ca
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -86764,8 +86838,8 @@ module \spr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_spr0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_spr0_spr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -86778,23 +86852,23 @@ module \spr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_spr0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_spr0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_spr0_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_spr0_spr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_spr0_spr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_spr0_spr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_spr0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_spr0_spr1$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_spr0_fast1$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \alu_spr0_xer_so$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \alu_spr0_xer_ov$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \alu_spr0_xer_ca$5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_spr0_p_valid_i
@@ -86817,10 +86891,10 @@ module \spr0
     connect \xer_so \alu_spr0_xer_so
     connect \xer_ov \alu_spr0_xer_ov
     connect \xer_ca \alu_spr0_xer_ca
-    connect \op__insn_type \alu_spr0_op__insn_type
-    connect \op__fn_unit \alu_spr0_op__fn_unit
-    connect \op__insn \alu_spr0_op__insn
-    connect \op__is_32bit \alu_spr0_op__is_32bit
+    connect \spr_op__insn_type \alu_spr0_spr_op__insn_type
+    connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit
+    connect \spr_op__insn \alu_spr0_spr_op__insn
+    connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit
     connect \ra \alu_spr0_ra
     connect \spr1$1 \alu_spr0_spr1$1
     connect \fast1$2 \alu_spr0_fast1$2
@@ -86932,36 +87006,36 @@ module \spr0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $6
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 6 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 6 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -86969,10 +87043,10 @@ module \spr0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A $9
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -86980,9 +87054,9 @@ module \spr0
     connect \A $11
     connect \Y $8
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -86998,9 +87072,9 @@ module \spr0
     assign \all_rd $14
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -87010,11 +87084,11 @@ module \spr0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87022,9 +87096,9 @@ module \spr0
     connect \A \all_rd_dly
     connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87040,16 +87114,16 @@ module \spr0
     assign \all_rd_pulse $18
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_spr0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -87059,11 +87133,11 @@ module \spr0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87071,9 +87145,9 @@ module \spr0
     connect \A \alu_done_dly
     connect \Y $20
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87089,28 +87163,28 @@ module \spr0
     assign \alu_pulse $22
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 6 \alu_pulsem
   process $group_6
     assign \alu_pulsem 6'000000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 6 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 6 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 6 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $24
   end
   process $group_7
@@ -87126,38 +87200,38 @@ module \spr0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 6 $28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 6 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 6 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $28
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 6 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $28
     connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -87165,7 +87239,7 @@ module \spr0
     connect \A $30
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87173,39 +87247,39 @@ module \spr0
     connect \A $27
     connect \Y $26
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $26
     connect \Y $34
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $34
+    assign \cu_done_o 1'0
+    assign \cu_done_o $34
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $36
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -87213,9 +87287,9 @@ module \spr0
     connect \A \prev_wr_go
     connect \Y $38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87231,11 +87305,11 @@ module \spr0
     assign \wr_any $40
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87243,9 +87317,9 @@ module \spr0
     connect \A \alu_spr0_n_ready_i
     connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87256,9 +87330,9 @@ module \spr0
     connect \B $42
     connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 6 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -87266,12 +87340,12 @@ module \spr0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -87282,9 +87356,9 @@ module \spr0
     connect \B 1'0
     connect \Y $48
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87295,22 +87369,22 @@ module \spr0
     connect \B $48
     connect \Y $50
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87321,9 +87395,9 @@ module \spr0
     connect \B \alu_spr0_n_ready_i
     connect \Y $54
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87334,9 +87408,9 @@ module \spr0
     connect \B \alu_spr0_n_valid_o
     connect \Y $56
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87344,25 +87418,25 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $56
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $58
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $50
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $58 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87370,7 +87444,7 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $60
   end
   process $group_11
@@ -87378,19 +87452,19 @@ module \spr0
     assign \reset $60
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $63
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $62
   end
   process $group_12
@@ -87398,19 +87472,19 @@ module \spr0
     assign \rst_r $62
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 6 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 6 $64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $64
   end
   process $group_13
@@ -87418,19 +87492,19 @@ module \spr0
     assign \reset_w $64
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 6 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 6 $66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \B_SIGNED 0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $66
   end
   process $group_14
@@ -87440,12 +87514,12 @@ module \spr0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $69
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -87453,7 +87527,7 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_spr0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $68
   end
   process $group_16
@@ -87481,7 +87555,7 @@ module \spr0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -87507,7 +87581,7 @@ module \spr0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -87531,9 +87605,9 @@ module \spr0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 6 $70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $71
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -87541,7 +87615,7 @@ module \spr0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $70
   end
   process $group_23
@@ -87549,9 +87623,9 @@ module \spr0
     assign \req_l_s_req $70
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 6 $72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $73
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -87640,7 +87714,7 @@ module \spr0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -87654,11 +87728,11 @@ module \spr0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -87682,8 +87756,8 @@ module \spr0
   cell $mux $75
     parameter \WIDTH 51
     connect \A { \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
+    connect \S \cu_issue_i
     connect \Y $74
   end
   process $group_25
@@ -87700,10 +87774,10 @@ module \spr0
     assign \oper_l__insn$next \oper_l__insn
     assign \oper_l__is_32bit$next \oper_l__is_32bit
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
+        assign { \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type }
     end
     sync init
       update \oper_l__insn_type 7'0000000
@@ -87716,9 +87790,9 @@ module \spr0
       update \oper_l__insn \oper_l__insn$next
       update \oper_l__is_32bit \oper_l__is_32bit$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__o_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__o
@@ -87785,9 +87859,9 @@ module \spr0
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r1__spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__spr1_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r1_l__spr1
@@ -87854,9 +87928,9 @@ module \spr0
       update \data_r1_l__spr1 \data_r1_l__spr1$next
       update \data_r1_l__spr1_ok \data_r1_l__spr1_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r2__fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__fast1_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r2_l__fast1
@@ -87923,9 +87997,9 @@ module \spr0
       update \data_r2_l__fast1 \data_r2_l__fast1$next
       update \data_r2_l__fast1_ok \data_r2_l__fast1_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r3__xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r3__xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \data_r3_l__xer_so
@@ -87992,9 +88066,9 @@ module \spr0
       update \data_r3_l__xer_so \data_r3_l__xer_so$next
       update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 2 \data_r4__xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r4__xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \data_r4_l__xer_ov
@@ -88061,9 +88135,9 @@ module \spr0
       update \data_r4_l__xer_ov \data_r4_l__xer_ov$next
       update \data_r4_l__xer_ov_ok \data_r4_l__xer_ov_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 2 \data_r5__xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r5__xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \data_r5_l__xer_ca
@@ -88130,9 +88204,9 @@ module \spr0
       update \data_r5_l__xer_ca \data_r5_l__xer_ca$next
       update \data_r5_l__xer_ca_ok \data_r5_l__xer_ca_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $113
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88140,12 +88214,12 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__o_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $112
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $115
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88153,12 +88227,12 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__spr1_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $114
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88166,12 +88240,12 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__fast1_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $116
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88179,12 +88253,12 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r3__xer_so_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $118
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88192,12 +88266,12 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r4__xer_ov_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $120
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88205,20 +88279,20 @@ module \spr0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r5__xer_ca_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $122
   end
   process $group_57
-    assign \wrmask 6'000000
-    assign \wrmask { $122 $120 $118 $116 $114 $112 }
+    assign \cu_wrmask_o 6'000000
+    assign \cu_wrmask_o { $122 $120 $118 $116 $114 $112 }
     sync init
   end
   process $group_58
-    assign \alu_spr0_op__insn_type 7'0000000
-    assign \alu_spr0_op__fn_unit 11'00000000000
-    assign \alu_spr0_op__insn 32'00000000000000000000000000000000
-    assign \alu_spr0_op__is_32bit 1'0
-    assign { \alu_spr0_op__is_32bit \alu_spr0_op__insn \alu_spr0_op__fn_unit \alu_spr0_op__insn_type } { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
+    assign \alu_spr0_spr_op__insn_type 7'0000000
+    assign \alu_spr0_spr_op__fn_unit 11'00000000000
+    assign \alu_spr0_spr_op__insn 32'00000000000000000000000000000000
+    assign \alu_spr0_spr_op__is_32bit 1'0
+    assign { \alu_spr0_spr_op__is_32bit \alu_spr0_spr_op__insn \alu_spr0_spr_op__fn_unit \alu_spr0_spr_op__insn_type } { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -88418,9 +88492,9 @@ module \spr0
     assign \alu_spr0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88454,9 +88528,9 @@ module \spr0
     assign \alu_spr0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $138
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88486,13 +88560,13 @@ module \spr0
     sync init
   end
   process $group_80
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $140
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -88500,12 +88574,12 @@ module \spr0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $140
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -88516,19 +88590,19 @@ module \spr0
     connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 }
     connect \Y $142
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $144
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $144
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 6 $146
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -88540,91 +88614,91 @@ module \spr0
     connect \Y $146
   end
   process $group_81
-    assign \rd__rel 6'000000
-    assign \rd__rel $146
+    assign \cu_rd__rel_o 6'000000
+    assign \cu_rd__rel_o $146
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $148
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $148
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $150
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $150
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $152
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $152
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $154
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $154
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $156
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $156
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $158
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $158
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 6 $160
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -88635,9 +88709,9 @@ module \spr0
     connect \B { $148 $150 $152 $154 $156 $158 }
     connect \Y $160
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 6 $162
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $163
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -88645,147 +88719,147 @@ module \spr0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 6
     connect \A $160
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $162
   end
   process $group_82
-    assign \wr__rel 6'000000
-    assign \wr__rel $162
+    assign \cu_wr__rel_o 6'000000
+    assign \cu_wr__rel_o $162
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $164
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $164
   end
   process $group_83
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $164 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $166
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $167
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $166
   end
   process $group_84
     assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $166 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $168
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $168
   end
   process $group_85
     assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $168 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__fast1_ok \data_r2__fast1 } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $170
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $171
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [3]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [3]
+    connect \B \cu_busy_o
     connect \Y $170
   end
   process $group_86
     assign \dest4_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $170 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $172
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $173
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [4]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [4]
+    connect \B \cu_busy_o
     connect \Y $172
   end
   process $group_87
     assign \dest5_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $172 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest5_o { \data_r4__xer_ov_ok \data_r4__xer_ov } [1:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $174
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $175
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [5]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [5]
+    connect \B \cu_busy_o
     connect \Y $174
   end
   process $group_88
     assign \dest6_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $174 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest6_o { \data_r5__xer_ca_ok \data_r5__xer_ca } [1:0]
     end
@@ -88829,9 +88903,9 @@ module \n$71
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88885,9 +88959,9 @@ module \n$73
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -88907,7 +88981,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input"
 module \input$74
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -88982,8 +89056,8 @@ module \input$74
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -88996,41 +89070,41 @@ module \input$74
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 15 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 16 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 17 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 18 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 19 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -89105,8 +89179,8 @@ module \input$74
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 20 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 20 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89119,39 +89193,39 @@ module \input$74
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 21 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 22 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 23 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 24 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 34 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 21 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 22 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 24 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 34 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 35 \ra$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 36 \rb$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 output 37 \xer_so$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
   wire width 64 \a
@@ -89168,7 +89242,7 @@ module \input$74
   process $group_0
     assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
-    switch { \op__invert_a }
+    switch { \mul_op__invert_a }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
       case 1'1
         assign \a $20
@@ -89186,7 +89260,7 @@ module \input$74
   process $group_2
     assign \xer_so$19 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
-    switch { \op__oe__oe_ok }
+    switch { \mul_op__oe__oe_ok }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
       case 1'1
         assign \xer_so$19 \xer_so
@@ -89199,22 +89273,22 @@ module \input$74
     sync init
   end
   process $group_4
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
   process $group_19
@@ -89226,7 +89300,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1"
 module \mul1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -89301,8 +89375,8 @@ module \mul1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89315,41 +89389,41 @@ module \mul1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 15 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 16 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 17 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 18 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 19 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -89424,8 +89498,8 @@ module \mul1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 20 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 20 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89438,39 +89512,39 @@ module \mul1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 21 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 22 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 23 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 24 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 34 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 21 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 22 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 24 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 34 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 35 \ra$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 36 \rb$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 output 37 \xer_so$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 output 38 \neg_res
@@ -89480,7 +89554,7 @@ module \mul1
   wire width 1 \is_32bit
   process $group_0
     assign \is_32bit 1'0
-    assign \is_32bit \op__is_32bit
+    assign \is_32bit \mul_op__is_32bit
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31"
@@ -89492,7 +89566,7 @@ module \mul1
     parameter \WIDTH 1
     connect \A \ra [63]
     connect \B \ra [31]
-    connect \S \op__is_32bit
+    connect \S \mul_op__is_32bit
     connect \Y $20
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
@@ -89505,7 +89579,7 @@ module \mul1
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $20
-    connect \B \op__is_signed
+    connect \B \mul_op__is_signed
     connect \Y $22
   end
   process $group_1
@@ -89522,7 +89596,7 @@ module \mul1
     parameter \WIDTH 1
     connect \A \rb [63]
     connect \B \rb [31]
-    connect \S \op__is_32bit
+    connect \S \mul_op__is_32bit
     connect \Y $24
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
@@ -89535,7 +89609,7 @@ module \mul1
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $24
-    connect \B \op__is_signed
+    connect \B \mul_op__is_signed
     connect \Y $26
   end
   process $group_2
@@ -89555,7 +89629,7 @@ module \mul1
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \ra [31]
-    connect \B \op__is_signed
+    connect \B \mul_op__is_signed
     connect \Y $28
   end
   process $group_3
@@ -89575,7 +89649,7 @@ module \mul1
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \rb [31]
-    connect \B \op__is_signed
+    connect \B \mul_op__is_signed
     connect \Y $30
   end
   process $group_4
@@ -89633,9 +89707,9 @@ module \mul1
     connect \A \ra
     connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 65 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   cell $pos $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -89673,9 +89747,9 @@ module \mul1
     connect \A \rb
     connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 65 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   cell $pos $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -89742,22 +89816,22 @@ module \mul1
     sync init
   end
   process $group_13
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
 end
@@ -89772,9 +89846,9 @@ module \mul_pipe1
   wire width 1 output 2 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 3 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 4 \muxid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -89849,10 +89923,10 @@ module \mul_pipe1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 5 \op__insn_type
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 5 \mul_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89865,73 +89939,73 @@ module \mul_pipe1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 7 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 8 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 9 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 10 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 11 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 12 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 13 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 14 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 15 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 16 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 17 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 18 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 19 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 6 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 7 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 8 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 9 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 10 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 11 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 12 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 13 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 14 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 15 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 16 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 17 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 18 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 19 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 20 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \ra$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 21 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \rb$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 output 22 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \xer_so$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 output 23 \neg_res
@@ -89945,7 +90019,7 @@ module \mul_pipe1
   wire width 1 input 25 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 26 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 27 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -90020,8 +90094,8 @@ module \mul_pipe1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 28 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 28 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90034,39 +90108,39 @@ module \mul_pipe1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 29 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 30 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 31 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 32 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 33 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 34 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 35 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 36 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 37 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 38 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 39 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 40 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 41 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 42 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 29 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 30 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 31 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 32 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 33 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 34 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 35 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 36 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 37 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 38 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 39 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 40 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 41 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 42 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 43 \ra$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 44 \rb$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 45 \xer_so$19
   cell \p$72 \p
     connect \p_valid_i \p_valid_i
@@ -90076,7 +90150,7 @@ module \mul_pipe1
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -90151,8 +90225,8 @@ module \mul_pipe1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90165,41 +90239,41 @@ module \mul_pipe1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \input_xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid$20
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -90274,8 +90348,8 @@ module \mul_pipe1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_mul_op__insn_type$21
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90288,81 +90362,81 @@ module \mul_pipe1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_a$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__zero_a$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__invert_out$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__write_cr0$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_mul_op__fn_unit$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_mul_op__imm_data__imm$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__imm_data__imm_ok$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__rc__rc$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__rc__rc_ok$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__oe__oe$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__oe__oe_ok$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__invert_a$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__zero_a$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__invert_out$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__write_cr0$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__is_32bit$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_mul_op__is_signed$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_mul_op__insn$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \input_xer_so$38
   cell \input$74 \input
     connect \muxid \input_muxid
-    connect \op__insn_type \input_op__insn_type
-    connect \op__fn_unit \input_op__fn_unit
-    connect \op__imm_data__imm \input_op__imm_data__imm
-    connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
-    connect \op__rc__rc \input_op__rc__rc
-    connect \op__rc__rc_ok \input_op__rc__rc_ok
-    connect \op__oe__oe \input_op__oe__oe
-    connect \op__oe__oe_ok \input_op__oe__oe_ok
-    connect \op__invert_a \input_op__invert_a
-    connect \op__zero_a \input_op__zero_a
-    connect \op__invert_out \input_op__invert_out
-    connect \op__write_cr0 \input_op__write_cr0
-    connect \op__is_32bit \input_op__is_32bit
-    connect \op__is_signed \input_op__is_signed
-    connect \op__insn \input_op__insn
+    connect \mul_op__insn_type \input_mul_op__insn_type
+    connect \mul_op__fn_unit \input_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \input_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \input_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \input_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \input_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \input_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \input_mul_op__invert_a
+    connect \mul_op__zero_a \input_mul_op__zero_a
+    connect \mul_op__invert_out \input_mul_op__invert_out
+    connect \mul_op__write_cr0 \input_mul_op__write_cr0
+    connect \mul_op__is_32bit \input_mul_op__is_32bit
+    connect \mul_op__is_signed \input_mul_op__is_signed
+    connect \mul_op__insn \input_mul_op__insn
     connect \ra \input_ra
     connect \rb \input_rb
     connect \xer_so \input_xer_so
     connect \muxid$1 \input_muxid$20
-    connect \op__insn_type$2 \input_op__insn_type$21
-    connect \op__fn_unit$3 \input_op__fn_unit$22
-    connect \op__imm_data__imm$4 \input_op__imm_data__imm$23
-    connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$24
-    connect \op__rc__rc$6 \input_op__rc__rc$25
-    connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$26
-    connect \op__oe__oe$8 \input_op__oe__oe$27
-    connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$28
-    connect \op__invert_a$10 \input_op__invert_a$29
-    connect \op__zero_a$11 \input_op__zero_a$30
-    connect \op__invert_out$12 \input_op__invert_out$31
-    connect \op__write_cr0$13 \input_op__write_cr0$32
-    connect \op__is_32bit$14 \input_op__is_32bit$33
-    connect \op__is_signed$15 \input_op__is_signed$34
-    connect \op__insn$16 \input_op__insn$35
+    connect \mul_op__insn_type$2 \input_mul_op__insn_type$21
+    connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$22
+    connect \mul_op__imm_data__imm$4 \input_mul_op__imm_data__imm$23
+    connect \mul_op__imm_data__imm_ok$5 \input_mul_op__imm_data__imm_ok$24
+    connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$25
+    connect \mul_op__rc__rc_ok$7 \input_mul_op__rc__rc_ok$26
+    connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$27
+    connect \mul_op__oe__oe_ok$9 \input_mul_op__oe__oe_ok$28
+    connect \mul_op__invert_a$10 \input_mul_op__invert_a$29
+    connect \mul_op__zero_a$11 \input_mul_op__zero_a$30
+    connect \mul_op__invert_out$12 \input_mul_op__invert_out$31
+    connect \mul_op__write_cr0$13 \input_mul_op__write_cr0$32
+    connect \mul_op__is_32bit$14 \input_mul_op__is_32bit$33
+    connect \mul_op__is_signed$15 \input_mul_op__is_signed$34
+    connect \mul_op__insn$16 \input_mul_op__insn$35
     connect \ra$17 \input_ra$36
     connect \rb$18 \input_rb$37
     connect \xer_so$19 \input_xer_so$38
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul1_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -90437,8 +90511,8 @@ module \mul_pipe1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul1_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul1_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90451,41 +90525,41 @@ module \mul_pipe1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul1_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul1_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul1_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul1_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul1_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul1_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul1_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul1_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul1_xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul1_muxid$39
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -90560,8 +90634,8 @@ module \mul_pipe1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul1_op__insn_type$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul1_mul_op__insn_type$40
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90574,39 +90648,39 @@ module \mul_pipe1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul1_op__fn_unit$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul1_op__imm_data__imm$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__imm_data__imm_ok$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__rc__rc$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__rc__rc_ok$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__oe__oe$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__oe__oe_ok$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__invert_a$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__zero_a$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__invert_out$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__write_cr0$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__is_32bit$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul1_op__is_signed$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul1_op__insn$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul1_mul_op__fn_unit$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul1_mul_op__imm_data__imm$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__imm_data__imm_ok$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__rc__rc$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__rc__rc_ok$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__oe__oe$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__oe__oe_ok$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__invert_a$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__zero_a$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__invert_out$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__write_cr0$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__is_32bit$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul1_mul_op__is_signed$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul1_mul_op__insn$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul1_ra$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul1_rb$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul1_xer_so$57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 \mul1_neg_res
@@ -90614,40 +90688,40 @@ module \mul_pipe1
   wire width 1 \mul1_neg_res32
   cell \mul1 \mul1
     connect \muxid \mul1_muxid
-    connect \op__insn_type \mul1_op__insn_type
-    connect \op__fn_unit \mul1_op__fn_unit
-    connect \op__imm_data__imm \mul1_op__imm_data__imm
-    connect \op__imm_data__imm_ok \mul1_op__imm_data__imm_ok
-    connect \op__rc__rc \mul1_op__rc__rc
-    connect \op__rc__rc_ok \mul1_op__rc__rc_ok
-    connect \op__oe__oe \mul1_op__oe__oe
-    connect \op__oe__oe_ok \mul1_op__oe__oe_ok
-    connect \op__invert_a \mul1_op__invert_a
-    connect \op__zero_a \mul1_op__zero_a
-    connect \op__invert_out \mul1_op__invert_out
-    connect \op__write_cr0 \mul1_op__write_cr0
-    connect \op__is_32bit \mul1_op__is_32bit
-    connect \op__is_signed \mul1_op__is_signed
-    connect \op__insn \mul1_op__insn
+    connect \mul_op__insn_type \mul1_mul_op__insn_type
+    connect \mul_op__fn_unit \mul1_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul1_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul1_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul1_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul1_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul1_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul1_mul_op__invert_a
+    connect \mul_op__zero_a \mul1_mul_op__zero_a
+    connect \mul_op__invert_out \mul1_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul1_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul1_mul_op__is_32bit
+    connect \mul_op__is_signed \mul1_mul_op__is_signed
+    connect \mul_op__insn \mul1_mul_op__insn
     connect \ra \mul1_ra
     connect \rb \mul1_rb
     connect \xer_so \mul1_xer_so
     connect \muxid$1 \mul1_muxid$39
-    connect \op__insn_type$2 \mul1_op__insn_type$40
-    connect \op__fn_unit$3 \mul1_op__fn_unit$41
-    connect \op__imm_data__imm$4 \mul1_op__imm_data__imm$42
-    connect \op__imm_data__imm_ok$5 \mul1_op__imm_data__imm_ok$43
-    connect \op__rc__rc$6 \mul1_op__rc__rc$44
-    connect \op__rc__rc_ok$7 \mul1_op__rc__rc_ok$45
-    connect \op__oe__oe$8 \mul1_op__oe__oe$46
-    connect \op__oe__oe_ok$9 \mul1_op__oe__oe_ok$47
-    connect \op__invert_a$10 \mul1_op__invert_a$48
-    connect \op__zero_a$11 \mul1_op__zero_a$49
-    connect \op__invert_out$12 \mul1_op__invert_out$50
-    connect \op__write_cr0$13 \mul1_op__write_cr0$51
-    connect \op__is_32bit$14 \mul1_op__is_32bit$52
-    connect \op__is_signed$15 \mul1_op__is_signed$53
-    connect \op__insn$16 \mul1_op__insn$54
+    connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$40
+    connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$41
+    connect \mul_op__imm_data__imm$4 \mul1_mul_op__imm_data__imm$42
+    connect \mul_op__imm_data__imm_ok$5 \mul1_mul_op__imm_data__imm_ok$43
+    connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$44
+    connect \mul_op__rc__rc_ok$7 \mul1_mul_op__rc__rc_ok$45
+    connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$46
+    connect \mul_op__oe__oe_ok$9 \mul1_mul_op__oe__oe_ok$47
+    connect \mul_op__invert_a$10 \mul1_mul_op__invert_a$48
+    connect \mul_op__zero_a$11 \mul1_mul_op__zero_a$49
+    connect \mul_op__invert_out$12 \mul1_mul_op__invert_out$50
+    connect \mul_op__write_cr0$13 \mul1_mul_op__write_cr0$51
+    connect \mul_op__is_32bit$14 \mul1_mul_op__is_32bit$52
+    connect \mul_op__is_signed$15 \mul1_mul_op__is_signed$53
+    connect \mul_op__insn$16 \mul1_mul_op__insn$54
     connect \ra$17 \mul1_ra$55
     connect \rb$18 \mul1_rb$56
     connect \xer_so$19 \mul1_xer_so$57
@@ -90660,22 +90734,22 @@ module \mul_pipe1
     sync init
   end
   process $group_1
-    assign \input_op__insn_type 7'0000000
-    assign \input_op__fn_unit 11'00000000000
-    assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_op__imm_data__imm_ok 1'0
-    assign \input_op__rc__rc 1'0
-    assign \input_op__rc__rc_ok 1'0
-    assign \input_op__oe__oe 1'0
-    assign \input_op__oe__oe_ok 1'0
-    assign \input_op__invert_a 1'0
-    assign \input_op__zero_a 1'0
-    assign \input_op__invert_out 1'0
-    assign \input_op__write_cr0 1'0
-    assign \input_op__is_32bit 1'0
-    assign \input_op__is_signed 1'0
-    assign \input_op__insn 32'00000000000000000000000000000000
-    assign { \input_op__insn \input_op__is_signed \input_op__is_32bit \input_op__write_cr0 \input_op__invert_out \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 }
+    assign \input_mul_op__insn_type 7'0000000
+    assign \input_mul_op__fn_unit 11'00000000000
+    assign \input_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_mul_op__imm_data__imm_ok 1'0
+    assign \input_mul_op__rc__rc 1'0
+    assign \input_mul_op__rc__rc_ok 1'0
+    assign \input_mul_op__oe__oe 1'0
+    assign \input_mul_op__oe__oe_ok 1'0
+    assign \input_mul_op__invert_a 1'0
+    assign \input_mul_op__zero_a 1'0
+    assign \input_mul_op__invert_out 1'0
+    assign \input_mul_op__write_cr0 1'0
+    assign \input_mul_op__is_32bit 1'0
+    assign \input_mul_op__is_signed 1'0
+    assign \input_mul_op__insn 32'00000000000000000000000000000000
+    assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__invert_out \input_mul_op__zero_a \input_mul_op__invert_a { \input_mul_op__oe__oe_ok \input_mul_op__oe__oe } { \input_mul_op__rc__rc_ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 }
     sync init
   end
   process $group_16
@@ -90699,22 +90773,22 @@ module \mul_pipe1
     sync init
   end
   process $group_20
-    assign \mul1_op__insn_type 7'0000000
-    assign \mul1_op__fn_unit 11'00000000000
-    assign \mul1_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul1_op__imm_data__imm_ok 1'0
-    assign \mul1_op__rc__rc 1'0
-    assign \mul1_op__rc__rc_ok 1'0
-    assign \mul1_op__oe__oe 1'0
-    assign \mul1_op__oe__oe_ok 1'0
-    assign \mul1_op__invert_a 1'0
-    assign \mul1_op__zero_a 1'0
-    assign \mul1_op__invert_out 1'0
-    assign \mul1_op__write_cr0 1'0
-    assign \mul1_op__is_32bit 1'0
-    assign \mul1_op__is_signed 1'0
-    assign \mul1_op__insn 32'00000000000000000000000000000000
-    assign { \mul1_op__insn \mul1_op__is_signed \mul1_op__is_32bit \mul1_op__write_cr0 \mul1_op__invert_out \mul1_op__zero_a \mul1_op__invert_a { \mul1_op__oe__oe_ok \mul1_op__oe__oe } { \mul1_op__rc__rc_ok \mul1_op__rc__rc } { \mul1_op__imm_data__imm_ok \mul1_op__imm_data__imm } \mul1_op__fn_unit \mul1_op__insn_type } { \input_op__insn$35 \input_op__is_signed$34 \input_op__is_32bit$33 \input_op__write_cr0$32 \input_op__invert_out$31 \input_op__zero_a$30 \input_op__invert_a$29 { \input_op__oe__oe_ok$28 \input_op__oe__oe$27 } { \input_op__rc__rc_ok$26 \input_op__rc__rc$25 } { \input_op__imm_data__imm_ok$24 \input_op__imm_data__imm$23 } \input_op__fn_unit$22 \input_op__insn_type$21 }
+    assign \mul1_mul_op__insn_type 7'0000000
+    assign \mul1_mul_op__fn_unit 11'00000000000
+    assign \mul1_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul1_mul_op__imm_data__imm_ok 1'0
+    assign \mul1_mul_op__rc__rc 1'0
+    assign \mul1_mul_op__rc__rc_ok 1'0
+    assign \mul1_mul_op__oe__oe 1'0
+    assign \mul1_mul_op__oe__oe_ok 1'0
+    assign \mul1_mul_op__invert_a 1'0
+    assign \mul1_mul_op__zero_a 1'0
+    assign \mul1_mul_op__invert_out 1'0
+    assign \mul1_mul_op__write_cr0 1'0
+    assign \mul1_mul_op__is_32bit 1'0
+    assign \mul1_mul_op__is_signed 1'0
+    assign \mul1_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__invert_out \mul1_mul_op__zero_a \mul1_mul_op__invert_a { \mul1_mul_op__oe__oe_ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__rc_ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$35 \input_mul_op__is_signed$34 \input_mul_op__is_32bit$33 \input_mul_op__write_cr0$32 \input_mul_op__invert_out$31 \input_mul_op__zero_a$30 \input_mul_op__invert_a$29 { \input_mul_op__oe__oe_ok$28 \input_mul_op__oe__oe$27 } { \input_mul_op__rc__rc_ok$26 \input_mul_op__rc__rc$25 } { \input_mul_op__imm_data__imm_ok$24 \input_mul_op__imm_data__imm$23 } \input_mul_op__fn_unit$22 \input_mul_op__insn_type$21 }
     sync init
   end
   process $group_35
@@ -90766,7 +90840,7 @@ module \mul_pipe1
     assign \p_valid_i_p_ready_o $59
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$61
   process $group_41
     assign \muxid$61 2'00
@@ -90846,8 +90920,8 @@ module \mul_pipe1
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$62
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90860,68 +90934,68 @@ module \mul_pipe1
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$76
   process $group_42
-    assign \op__insn_type$62 7'0000000
-    assign \op__fn_unit$63 11'00000000000
-    assign \op__imm_data__imm$64 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$65 1'0
-    assign \op__rc__rc$66 1'0
-    assign \op__rc__rc_ok$67 1'0
-    assign \op__oe__oe$68 1'0
-    assign \op__oe__oe_ok$69 1'0
-    assign \op__invert_a$70 1'0
-    assign \op__zero_a$71 1'0
-    assign \op__invert_out$72 1'0
-    assign \op__write_cr0$73 1'0
-    assign \op__is_32bit$74 1'0
-    assign \op__is_signed$75 1'0
-    assign \op__insn$76 32'00000000000000000000000000000000
-    assign { \op__insn$76 \op__is_signed$75 \op__is_32bit$74 \op__write_cr0$73 \op__invert_out$72 \op__zero_a$71 \op__invert_a$70 { \op__oe__oe_ok$69 \op__oe__oe$68 } { \op__rc__rc_ok$67 \op__rc__rc$66 } { \op__imm_data__imm_ok$65 \op__imm_data__imm$64 } \op__fn_unit$63 \op__insn_type$62 } { \mul1_op__insn$54 \mul1_op__is_signed$53 \mul1_op__is_32bit$52 \mul1_op__write_cr0$51 \mul1_op__invert_out$50 \mul1_op__zero_a$49 \mul1_op__invert_a$48 { \mul1_op__oe__oe_ok$47 \mul1_op__oe__oe$46 } { \mul1_op__rc__rc_ok$45 \mul1_op__rc__rc$44 } { \mul1_op__imm_data__imm_ok$43 \mul1_op__imm_data__imm$42 } \mul1_op__fn_unit$41 \mul1_op__insn_type$40 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+    assign \mul_op__insn_type$62 7'0000000
+    assign \mul_op__fn_unit$63 11'00000000000
+    assign \mul_op__imm_data__imm$64 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$65 1'0
+    assign \mul_op__rc__rc$66 1'0
+    assign \mul_op__rc__rc_ok$67 1'0
+    assign \mul_op__oe__oe$68 1'0
+    assign \mul_op__oe__oe_ok$69 1'0
+    assign \mul_op__invert_a$70 1'0
+    assign \mul_op__zero_a$71 1'0
+    assign \mul_op__invert_out$72 1'0
+    assign \mul_op__write_cr0$73 1'0
+    assign \mul_op__is_32bit$74 1'0
+    assign \mul_op__is_signed$75 1'0
+    assign \mul_op__insn$76 32'00000000000000000000000000000000
+    assign { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 } { \mul1_mul_op__insn$54 \mul1_mul_op__is_signed$53 \mul1_mul_op__is_32bit$52 \mul1_mul_op__write_cr0$51 \mul1_mul_op__invert_out$50 \mul1_mul_op__zero_a$49 \mul1_mul_op__invert_a$48 { \mul1_mul_op__oe__oe_ok$47 \mul1_mul_op__oe__oe$46 } { \mul1_mul_op__rc__rc_ok$45 \mul1_mul_op__rc__rc$44 } { \mul1_mul_op__imm_data__imm_ok$43 \mul1_mul_op__imm_data__imm$42 } \mul1_mul_op__fn_unit$41 \mul1_mul_op__insn_type$40 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \ra$77
   process $group_57
     assign \ra$77 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \ra$77 \mul1_ra$55
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \rb$78
   process $group_58
     assign \rb$78 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \rb$78 \mul1_rb$56
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \xer_so$79
   process $group_59
     assign \xer_so$79 1'0
@@ -90984,72 +91058,72 @@ module \mul_pipe1
       update \muxid \muxid$next
   end
   process $group_64
-    assign \op__insn_type$next \op__insn_type
-    assign \op__fn_unit$next \op__fn_unit
-    assign \op__imm_data__imm$next \op__imm_data__imm
-    assign \op__imm_data__imm_ok$next \op__imm_data__imm_ok
-    assign \op__rc__rc$next \op__rc__rc
-    assign \op__rc__rc_ok$next \op__rc__rc_ok
-    assign \op__oe__oe$next \op__oe__oe
-    assign \op__oe__oe_ok$next \op__oe__oe_ok
-    assign \op__invert_a$next \op__invert_a
-    assign \op__zero_a$next \op__zero_a
-    assign \op__invert_out$next \op__invert_out
-    assign \op__write_cr0$next \op__write_cr0
-    assign \op__is_32bit$next \op__is_32bit
-    assign \op__is_signed$next \op__is_signed
-    assign \op__insn$next \op__insn
+    assign \mul_op__insn_type$next \mul_op__insn_type
+    assign \mul_op__fn_unit$next \mul_op__fn_unit
+    assign \mul_op__imm_data__imm$next \mul_op__imm_data__imm
+    assign \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm_ok
+    assign \mul_op__rc__rc$next \mul_op__rc__rc
+    assign \mul_op__rc__rc_ok$next \mul_op__rc__rc_ok
+    assign \mul_op__oe__oe$next \mul_op__oe__oe
+    assign \mul_op__oe__oe_ok$next \mul_op__oe__oe_ok
+    assign \mul_op__invert_a$next \mul_op__invert_a
+    assign \mul_op__zero_a$next \mul_op__zero_a
+    assign \mul_op__invert_out$next \mul_op__invert_out
+    assign \mul_op__write_cr0$next \mul_op__write_cr0
+    assign \mul_op__is_32bit$next \mul_op__is_32bit
+    assign \mul_op__is_signed$next \mul_op__is_signed
+    assign \mul_op__insn$next \mul_op__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__insn$next \op__is_signed$next \op__is_32bit$next \op__write_cr0$next \op__invert_out$next \op__zero_a$next \op__invert_a$next { \op__oe__oe_ok$next \op__oe__oe$next } { \op__rc__rc_ok$next \op__rc__rc$next } { \op__imm_data__imm_ok$next \op__imm_data__imm$next } \op__fn_unit$next \op__insn_type$next } { \op__insn$76 \op__is_signed$75 \op__is_32bit$74 \op__write_cr0$73 \op__invert_out$72 \op__zero_a$71 \op__invert_a$70 { \op__oe__oe_ok$69 \op__oe__oe$68 } { \op__rc__rc_ok$67 \op__rc__rc$66 } { \op__imm_data__imm_ok$65 \op__imm_data__imm$64 } \op__fn_unit$63 \op__insn_type$62 }
+        assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__insn$next \op__is_signed$next \op__is_32bit$next \op__write_cr0$next \op__invert_out$next \op__zero_a$next \op__invert_a$next { \op__oe__oe_ok$next \op__oe__oe$next } { \op__rc__rc_ok$next \op__rc__rc$next } { \op__imm_data__imm_ok$next \op__imm_data__imm$next } \op__fn_unit$next \op__insn_type$next } { \op__insn$76 \op__is_signed$75 \op__is_32bit$74 \op__write_cr0$73 \op__invert_out$72 \op__zero_a$71 \op__invert_a$70 { \op__oe__oe_ok$69 \op__oe__oe$68 } { \op__rc__rc_ok$67 \op__rc__rc$66 } { \op__imm_data__imm_ok$65 \op__imm_data__imm$64 } \op__fn_unit$63 \op__insn_type$62 }
+        assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \op__imm_data__imm_ok$next 1'0
-        assign \op__rc__rc$next 1'0
-        assign \op__rc__rc_ok$next 1'0
-        assign \op__oe__oe$next 1'0
-        assign \op__oe__oe_ok$next 1'0
-    end
-    sync init
-      update \op__insn_type 7'0000000
-      update \op__fn_unit 11'00000000000
-      update \op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__imm_data__imm_ok 1'0
-      update \op__rc__rc 1'0
-      update \op__rc__rc_ok 1'0
-      update \op__oe__oe 1'0
-      update \op__oe__oe_ok 1'0
-      update \op__invert_a 1'0
-      update \op__zero_a 1'0
-      update \op__invert_out 1'0
-      update \op__write_cr0 1'0
-      update \op__is_32bit 1'0
-      update \op__is_signed 1'0
-      update \op__insn 32'00000000000000000000000000000000
+        assign \mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \mul_op__imm_data__imm_ok$next 1'0
+        assign \mul_op__rc__rc$next 1'0
+        assign \mul_op__rc__rc_ok$next 1'0
+        assign \mul_op__oe__oe$next 1'0
+        assign \mul_op__oe__oe_ok$next 1'0
+    end
+    sync init
+      update \mul_op__insn_type 7'0000000
+      update \mul_op__fn_unit 11'00000000000
+      update \mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \mul_op__imm_data__imm_ok 1'0
+      update \mul_op__rc__rc 1'0
+      update \mul_op__rc__rc_ok 1'0
+      update \mul_op__oe__oe 1'0
+      update \mul_op__oe__oe_ok 1'0
+      update \mul_op__invert_a 1'0
+      update \mul_op__zero_a 1'0
+      update \mul_op__invert_out 1'0
+      update \mul_op__write_cr0 1'0
+      update \mul_op__is_32bit 1'0
+      update \mul_op__is_signed 1'0
+      update \mul_op__insn 32'00000000000000000000000000000000
     sync posedge \clk
-      update \op__insn_type \op__insn_type$next
-      update \op__fn_unit \op__fn_unit$next
-      update \op__imm_data__imm \op__imm_data__imm$next
-      update \op__imm_data__imm_ok \op__imm_data__imm_ok$next
-      update \op__rc__rc \op__rc__rc$next
-      update \op__rc__rc_ok \op__rc__rc_ok$next
-      update \op__oe__oe \op__oe__oe$next
-      update \op__oe__oe_ok \op__oe__oe_ok$next
-      update \op__invert_a \op__invert_a$next
-      update \op__zero_a \op__zero_a$next
-      update \op__invert_out \op__invert_out$next
-      update \op__write_cr0 \op__write_cr0$next
-      update \op__is_32bit \op__is_32bit$next
-      update \op__is_signed \op__is_signed$next
-      update \op__insn \op__insn$next
+      update \mul_op__insn_type \mul_op__insn_type$next
+      update \mul_op__fn_unit \mul_op__fn_unit$next
+      update \mul_op__imm_data__imm \mul_op__imm_data__imm$next
+      update \mul_op__imm_data__imm_ok \mul_op__imm_data__imm_ok$next
+      update \mul_op__rc__rc \mul_op__rc__rc$next
+      update \mul_op__rc__rc_ok \mul_op__rc__rc_ok$next
+      update \mul_op__oe__oe \mul_op__oe__oe$next
+      update \mul_op__oe__oe_ok \mul_op__oe__oe_ok$next
+      update \mul_op__invert_a \mul_op__invert_a$next
+      update \mul_op__zero_a \mul_op__zero_a$next
+      update \mul_op__invert_out \mul_op__invert_out$next
+      update \mul_op__write_cr0 \mul_op__write_cr0$next
+      update \mul_op__is_32bit \mul_op__is_32bit$next
+      update \mul_op__is_signed \mul_op__is_signed$next
+      update \mul_op__insn \mul_op__insn$next
   end
   process $group_79
     assign \ra$next \ra
@@ -91179,9 +91253,9 @@ module \n$76
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -91201,7 +91275,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2"
 module \mul2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -91276,8 +91350,8 @@ module \mul2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91290,45 +91364,45 @@ module \mul2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 15 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 16 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 17 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 18 \xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 input 19 \neg_res
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
   wire width 1 input 20 \neg_res32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -91403,8 +91477,8 @@ module \mul2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 22 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91417,37 +91491,37 @@ module \mul2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 23 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 24 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 36 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 36 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 output 37 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 output 38 \xer_so$17
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 output 39 \neg_res$18
@@ -91502,22 +91576,22 @@ module \mul2
     sync init
   end
   process $group_5
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
 end
@@ -91532,7 +91606,7 @@ module \mul_pipe2
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -91607,8 +91681,8 @@ module \mul_pipe2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91621,39 +91695,39 @@ module \mul_pipe2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 7 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 19 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 19 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 20 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 21 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 22 \xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 input 23 \neg_res
@@ -91663,9 +91737,9 @@ module \mul_pipe2
   wire width 1 output 25 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 26 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 27 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -91740,10 +91814,10 @@ module \mul_pipe2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 28 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 28 \mul_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91756,69 +91830,69 @@ module \mul_pipe2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 29 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 30 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 38 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$13$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 40 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 41 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 42 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 29 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 30 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 41 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 42 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 output 43 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 output 44 \xer_so$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \xer_so$17$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 output 45 \neg_res$18
@@ -91836,7 +91910,7 @@ module \mul_pipe2
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul2_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -91911,8 +91985,8 @@ module \mul_pipe2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul2_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul2_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91925,45 +91999,45 @@ module \mul_pipe2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul2_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul2_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul2_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul2_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul2_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul2_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul2_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul2_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul2_xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 \mul2_neg_res
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
   wire width 1 \mul2_neg_res32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul2_muxid$20
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -92038,8 +92112,8 @@ module \mul_pipe2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul2_op__insn_type$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul2_mul_op__insn_type$21
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92052,37 +92126,37 @@ module \mul_pipe2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul2_op__fn_unit$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul2_op__imm_data__imm$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__imm_data__imm_ok$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__rc__rc$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__rc__rc_ok$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__oe__oe$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__oe__oe_ok$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__invert_a$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__zero_a$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__invert_out$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__write_cr0$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__is_32bit$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul2_op__is_signed$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul2_op__insn$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul2_mul_op__fn_unit$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul2_mul_op__imm_data__imm$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__imm_data__imm_ok$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__rc__rc$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__rc__rc_ok$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__oe__oe$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__oe__oe_ok$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__invert_a$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__zero_a$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__invert_out$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__write_cr0$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__is_32bit$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul2_mul_op__is_signed$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul2_mul_op__insn$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 \mul2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul2_xer_so$36
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 \mul2_neg_res$37
@@ -92090,42 +92164,42 @@ module \mul_pipe2
   wire width 1 \mul2_neg_res32$38
   cell \mul2 \mul2
     connect \muxid \mul2_muxid
-    connect \op__insn_type \mul2_op__insn_type
-    connect \op__fn_unit \mul2_op__fn_unit
-    connect \op__imm_data__imm \mul2_op__imm_data__imm
-    connect \op__imm_data__imm_ok \mul2_op__imm_data__imm_ok
-    connect \op__rc__rc \mul2_op__rc__rc
-    connect \op__rc__rc_ok \mul2_op__rc__rc_ok
-    connect \op__oe__oe \mul2_op__oe__oe
-    connect \op__oe__oe_ok \mul2_op__oe__oe_ok
-    connect \op__invert_a \mul2_op__invert_a
-    connect \op__zero_a \mul2_op__zero_a
-    connect \op__invert_out \mul2_op__invert_out
-    connect \op__write_cr0 \mul2_op__write_cr0
-    connect \op__is_32bit \mul2_op__is_32bit
-    connect \op__is_signed \mul2_op__is_signed
-    connect \op__insn \mul2_op__insn
+    connect \mul_op__insn_type \mul2_mul_op__insn_type
+    connect \mul_op__fn_unit \mul2_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul2_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul2_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul2_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul2_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul2_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul2_mul_op__invert_a
+    connect \mul_op__zero_a \mul2_mul_op__zero_a
+    connect \mul_op__invert_out \mul2_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul2_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul2_mul_op__is_32bit
+    connect \mul_op__is_signed \mul2_mul_op__is_signed
+    connect \mul_op__insn \mul2_mul_op__insn
     connect \ra \mul2_ra
     connect \rb \mul2_rb
     connect \xer_so \mul2_xer_so
     connect \neg_res \mul2_neg_res
     connect \neg_res32 \mul2_neg_res32
     connect \muxid$1 \mul2_muxid$20
-    connect \op__insn_type$2 \mul2_op__insn_type$21
-    connect \op__fn_unit$3 \mul2_op__fn_unit$22
-    connect \op__imm_data__imm$4 \mul2_op__imm_data__imm$23
-    connect \op__imm_data__imm_ok$5 \mul2_op__imm_data__imm_ok$24
-    connect \op__rc__rc$6 \mul2_op__rc__rc$25
-    connect \op__rc__rc_ok$7 \mul2_op__rc__rc_ok$26
-    connect \op__oe__oe$8 \mul2_op__oe__oe$27
-    connect \op__oe__oe_ok$9 \mul2_op__oe__oe_ok$28
-    connect \op__invert_a$10 \mul2_op__invert_a$29
-    connect \op__zero_a$11 \mul2_op__zero_a$30
-    connect \op__invert_out$12 \mul2_op__invert_out$31
-    connect \op__write_cr0$13 \mul2_op__write_cr0$32
-    connect \op__is_32bit$14 \mul2_op__is_32bit$33
-    connect \op__is_signed$15 \mul2_op__is_signed$34
-    connect \op__insn$16 \mul2_op__insn$35
+    connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$21
+    connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$22
+    connect \mul_op__imm_data__imm$4 \mul2_mul_op__imm_data__imm$23
+    connect \mul_op__imm_data__imm_ok$5 \mul2_mul_op__imm_data__imm_ok$24
+    connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$25
+    connect \mul_op__rc__rc_ok$7 \mul2_mul_op__rc__rc_ok$26
+    connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$27
+    connect \mul_op__oe__oe_ok$9 \mul2_mul_op__oe__oe_ok$28
+    connect \mul_op__invert_a$10 \mul2_mul_op__invert_a$29
+    connect \mul_op__zero_a$11 \mul2_mul_op__zero_a$30
+    connect \mul_op__invert_out$12 \mul2_mul_op__invert_out$31
+    connect \mul_op__write_cr0$13 \mul2_mul_op__write_cr0$32
+    connect \mul_op__is_32bit$14 \mul2_mul_op__is_32bit$33
+    connect \mul_op__is_signed$15 \mul2_mul_op__is_signed$34
+    connect \mul_op__insn$16 \mul2_mul_op__insn$35
     connect \o \mul2_o
     connect \xer_so$17 \mul2_xer_so$36
     connect \neg_res$18 \mul2_neg_res$37
@@ -92137,22 +92211,22 @@ module \mul_pipe2
     sync init
   end
   process $group_1
-    assign \mul2_op__insn_type 7'0000000
-    assign \mul2_op__fn_unit 11'00000000000
-    assign \mul2_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul2_op__imm_data__imm_ok 1'0
-    assign \mul2_op__rc__rc 1'0
-    assign \mul2_op__rc__rc_ok 1'0
-    assign \mul2_op__oe__oe 1'0
-    assign \mul2_op__oe__oe_ok 1'0
-    assign \mul2_op__invert_a 1'0
-    assign \mul2_op__zero_a 1'0
-    assign \mul2_op__invert_out 1'0
-    assign \mul2_op__write_cr0 1'0
-    assign \mul2_op__is_32bit 1'0
-    assign \mul2_op__is_signed 1'0
-    assign \mul2_op__insn 32'00000000000000000000000000000000
-    assign { \mul2_op__insn \mul2_op__is_signed \mul2_op__is_32bit \mul2_op__write_cr0 \mul2_op__invert_out \mul2_op__zero_a \mul2_op__invert_a { \mul2_op__oe__oe_ok \mul2_op__oe__oe } { \mul2_op__rc__rc_ok \mul2_op__rc__rc } { \mul2_op__imm_data__imm_ok \mul2_op__imm_data__imm } \mul2_op__fn_unit \mul2_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul2_mul_op__insn_type 7'0000000
+    assign \mul2_mul_op__fn_unit 11'00000000000
+    assign \mul2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul2_mul_op__imm_data__imm_ok 1'0
+    assign \mul2_mul_op__rc__rc 1'0
+    assign \mul2_mul_op__rc__rc_ok 1'0
+    assign \mul2_mul_op__oe__oe 1'0
+    assign \mul2_mul_op__oe__oe_ok 1'0
+    assign \mul2_mul_op__invert_a 1'0
+    assign \mul2_mul_op__zero_a 1'0
+    assign \mul2_mul_op__invert_out 1'0
+    assign \mul2_mul_op__write_cr0 1'0
+    assign \mul2_mul_op__is_32bit 1'0
+    assign \mul2_mul_op__is_signed 1'0
+    assign \mul2_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__invert_out \mul2_mul_op__zero_a \mul2_mul_op__invert_a { \mul2_mul_op__oe__oe_ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__rc_ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
   process $group_16
@@ -92214,7 +92288,7 @@ module \mul_pipe2
     assign \p_valid_i_p_ready_o $40
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$42
   process $group_24
     assign \muxid$42 2'00
@@ -92294,8 +92368,8 @@ module \mul_pipe2
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$43
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92308,61 +92382,61 @@ module \mul_pipe2
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$57
   process $group_25
-    assign \op__insn_type$43 7'0000000
-    assign \op__fn_unit$44 11'00000000000
-    assign \op__imm_data__imm$45 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$46 1'0
-    assign \op__rc__rc$47 1'0
-    assign \op__rc__rc_ok$48 1'0
-    assign \op__oe__oe$49 1'0
-    assign \op__oe__oe_ok$50 1'0
-    assign \op__invert_a$51 1'0
-    assign \op__zero_a$52 1'0
-    assign \op__invert_out$53 1'0
-    assign \op__write_cr0$54 1'0
-    assign \op__is_32bit$55 1'0
-    assign \op__is_signed$56 1'0
-    assign \op__insn$57 32'00000000000000000000000000000000
-    assign { \op__insn$57 \op__is_signed$56 \op__is_32bit$55 \op__write_cr0$54 \op__invert_out$53 \op__zero_a$52 \op__invert_a$51 { \op__oe__oe_ok$50 \op__oe__oe$49 } { \op__rc__rc_ok$48 \op__rc__rc$47 } { \op__imm_data__imm_ok$46 \op__imm_data__imm$45 } \op__fn_unit$44 \op__insn_type$43 } { \mul2_op__insn$35 \mul2_op__is_signed$34 \mul2_op__is_32bit$33 \mul2_op__write_cr0$32 \mul2_op__invert_out$31 \mul2_op__zero_a$30 \mul2_op__invert_a$29 { \mul2_op__oe__oe_ok$28 \mul2_op__oe__oe$27 } { \mul2_op__rc__rc_ok$26 \mul2_op__rc__rc$25 } { \mul2_op__imm_data__imm_ok$24 \mul2_op__imm_data__imm$23 } \mul2_op__fn_unit$22 \mul2_op__insn_type$21 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+    assign \mul_op__insn_type$43 7'0000000
+    assign \mul_op__fn_unit$44 11'00000000000
+    assign \mul_op__imm_data__imm$45 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$46 1'0
+    assign \mul_op__rc__rc$47 1'0
+    assign \mul_op__rc__rc_ok$48 1'0
+    assign \mul_op__oe__oe$49 1'0
+    assign \mul_op__oe__oe_ok$50 1'0
+    assign \mul_op__invert_a$51 1'0
+    assign \mul_op__zero_a$52 1'0
+    assign \mul_op__invert_out$53 1'0
+    assign \mul_op__write_cr0$54 1'0
+    assign \mul_op__is_32bit$55 1'0
+    assign \mul_op__is_signed$56 1'0
+    assign \mul_op__insn$57 32'00000000000000000000000000000000
+    assign { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 } { \mul2_mul_op__insn$35 \mul2_mul_op__is_signed$34 \mul2_mul_op__is_32bit$33 \mul2_mul_op__write_cr0$32 \mul2_mul_op__invert_out$31 \mul2_mul_op__zero_a$30 \mul2_mul_op__invert_a$29 { \mul2_mul_op__oe__oe_ok$28 \mul2_mul_op__oe__oe$27 } { \mul2_mul_op__rc__rc_ok$26 \mul2_mul_op__rc__rc$25 } { \mul2_mul_op__imm_data__imm_ok$24 \mul2_mul_op__imm_data__imm$23 } \mul2_mul_op__fn_unit$22 \mul2_mul_op__insn_type$21 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 \o$58
   process $group_40
     assign \o$58 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
     assign \o$58 \mul2_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \xer_so$59
   process $group_41
     assign \xer_so$59 1'0
@@ -92425,72 +92499,72 @@ module \mul_pipe2
       update \muxid$1 \muxid$1$next
   end
   process $group_46
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__imm_data__imm$4$next \op__imm_data__imm$4
-    assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
-    assign \op__rc__rc$6$next \op__rc__rc$6
-    assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
-    assign \op__oe__oe$8$next \op__oe__oe$8
-    assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
-    assign \op__invert_a$10$next \op__invert_a$10
-    assign \op__zero_a$11$next \op__zero_a$11
-    assign \op__invert_out$12$next \op__invert_out$12
-    assign \op__write_cr0$13$next \op__write_cr0$13
-    assign \op__is_32bit$14$next \op__is_32bit$14
-    assign \op__is_signed$15$next \op__is_signed$15
-    assign \op__insn$16$next \op__insn$16
+    assign \mul_op__insn_type$2$next \mul_op__insn_type$2
+    assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3
+    assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4
+    assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5
+    assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6
+    assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7
+    assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8
+    assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9
+    assign \mul_op__invert_a$10$next \mul_op__invert_a$10
+    assign \mul_op__zero_a$11$next \mul_op__zero_a$11
+    assign \mul_op__invert_out$12$next \mul_op__invert_out$12
+    assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13
+    assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14
+    assign \mul_op__is_signed$15$next \mul_op__is_signed$15
+    assign \mul_op__insn$16$next \mul_op__insn$16
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$57 \op__is_signed$56 \op__is_32bit$55 \op__write_cr0$54 \op__invert_out$53 \op__zero_a$52 \op__invert_a$51 { \op__oe__oe_ok$50 \op__oe__oe$49 } { \op__rc__rc_ok$48 \op__rc__rc$47 } { \op__imm_data__imm_ok$46 \op__imm_data__imm$45 } \op__fn_unit$44 \op__insn_type$43 }
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$57 \op__is_signed$56 \op__is_32bit$55 \op__write_cr0$54 \op__invert_out$53 \op__zero_a$52 \op__invert_a$51 { \op__oe__oe_ok$50 \op__oe__oe$49 } { \op__rc__rc_ok$48 \op__rc__rc$47 } { \op__imm_data__imm_ok$46 \op__imm_data__imm$45 } \op__fn_unit$44 \op__insn_type$43 }
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \op__imm_data__imm_ok$5$next 1'0
-        assign \op__rc__rc$6$next 1'0
-        assign \op__rc__rc_ok$7$next 1'0
-        assign \op__oe__oe$8$next 1'0
-        assign \op__oe__oe_ok$9$next 1'0
-    end
-    sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__imm_data__imm_ok$5 1'0
-      update \op__rc__rc$6 1'0
-      update \op__rc__rc_ok$7 1'0
-      update \op__oe__oe$8 1'0
-      update \op__oe__oe_ok$9 1'0
-      update \op__invert_a$10 1'0
-      update \op__zero_a$11 1'0
-      update \op__invert_out$12 1'0
-      update \op__write_cr0$13 1'0
-      update \op__is_32bit$14 1'0
-      update \op__is_signed$15 1'0
-      update \op__insn$16 32'00000000000000000000000000000000
+        assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \mul_op__imm_data__imm_ok$5$next 1'0
+        assign \mul_op__rc__rc$6$next 1'0
+        assign \mul_op__rc__rc_ok$7$next 1'0
+        assign \mul_op__oe__oe$8$next 1'0
+        assign \mul_op__oe__oe_ok$9$next 1'0
+    end
+    sync init
+      update \mul_op__insn_type$2 7'0000000
+      update \mul_op__fn_unit$3 11'00000000000
+      update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \mul_op__imm_data__imm_ok$5 1'0
+      update \mul_op__rc__rc$6 1'0
+      update \mul_op__rc__rc_ok$7 1'0
+      update \mul_op__oe__oe$8 1'0
+      update \mul_op__oe__oe_ok$9 1'0
+      update \mul_op__invert_a$10 1'0
+      update \mul_op__zero_a$11 1'0
+      update \mul_op__invert_out$12 1'0
+      update \mul_op__write_cr0$13 1'0
+      update \mul_op__is_32bit$14 1'0
+      update \mul_op__is_signed$15 1'0
+      update \mul_op__insn$16 32'00000000000000000000000000000000
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__imm_data__imm$4 \op__imm_data__imm$4$next
-      update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
-      update \op__rc__rc$6 \op__rc__rc$6$next
-      update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
-      update \op__oe__oe$8 \op__oe__oe$8$next
-      update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
-      update \op__invert_a$10 \op__invert_a$10$next
-      update \op__zero_a$11 \op__zero_a$11$next
-      update \op__invert_out$12 \op__invert_out$12$next
-      update \op__write_cr0$13 \op__write_cr0$13$next
-      update \op__is_32bit$14 \op__is_32bit$14$next
-      update \op__is_signed$15 \op__is_signed$15$next
-      update \op__insn$16 \op__insn$16$next
+      update \mul_op__insn_type$2 \mul_op__insn_type$2$next
+      update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next
+      update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next
+      update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next
+      update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next
+      update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next
+      update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next
+      update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next
+      update \mul_op__invert_a$10 \mul_op__invert_a$10$next
+      update \mul_op__zero_a$11 \mul_op__zero_a$11$next
+      update \mul_op__invert_out$12 \mul_op__invert_out$12$next
+      update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next
+      update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next
+      update \mul_op__is_signed$15 \mul_op__is_signed$15$next
+      update \mul_op__insn$16 \mul_op__insn$16$next
   end
   process $group_61
     assign \o$next \o
@@ -92604,9 +92678,9 @@ module \n$78
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -92626,7 +92700,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3"
 module \mul3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -92701,8 +92775,8 @@ module \mul3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92715,41 +92789,41 @@ module \mul3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 15 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 input 16 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 17 \xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 input 18 \neg_res
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 19 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -92824,8 +92898,8 @@ module \mul3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 20 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 20 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92838,49 +92912,49 @@ module \mul3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 21 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 22 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 23 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 24 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 34 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 21 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 22 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 24 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 34 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 35 \o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 36 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 37 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 38 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 39 \xer_so$18
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36"
   wire width 1 \is_32bit
   process $group_0
     assign \is_32bit 1'0
-    assign \is_32bit \op__is_32bit
+    assign \is_32bit \mul_op__is_32bit
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40"
@@ -92897,9 +92971,9 @@ module \mul3
     connect \A \o
     connect \Y $20
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 130 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   cell $pos $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 129
@@ -92934,7 +93008,7 @@ module \mul3
   process $group_3
     assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \op__insn_type
+    switch \mul_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
       attribute \nmigen.decoding "OP_MUL_H32/52"
       case 7'0110100
@@ -93041,7 +93115,7 @@ module \mul3
   process $group_4
     assign \mul_ov 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \op__insn_type
+    switch \mul_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
       attribute \nmigen.decoding "OP_MUL_H32/52"
       case 7'0110100
@@ -93066,7 +93140,7 @@ module \mul3
   process $group_5
     assign \xer_ov 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \op__insn_type
+    switch \mul_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
       attribute \nmigen.decoding "OP_MUL_H32/52"
       case 7'0110100
@@ -93083,7 +93157,7 @@ module \mul3
   process $group_6
     assign \xer_ov_ok 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \op__insn_type
+    switch \mul_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
       attribute \nmigen.decoding "OP_MUL_H32/52"
       case 7'0110100
@@ -93108,29 +93182,29 @@ module \mul3
     sync init
   end
   process $group_9
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output"
 module \output$79
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -93205,8 +93279,8 @@ module \output$79
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -93219,45 +93293,45 @@ module \output$79
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 15 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 16 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 17 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 input 18 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 input 19 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 20 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -93332,8 +93406,8 @@ module \output$79
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 22 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -93346,49 +93420,49 @@ module \output$79
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 23 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 24 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 36 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 36 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 37 \o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 38 \o_ok$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 39 \cr_a$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 40 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 41 \xer_ov$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 42 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 43 \xer_so$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 44 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
   wire width 65 \o$22
@@ -93412,9 +93486,9 @@ module \output$79
     connect \A $24
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 65 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   cell $pos $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -93425,7 +93499,7 @@ module \output$79
   process $group_0
     assign \o$22 65'00000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
-    switch { \op__invert_out }
+    switch { \mul_op__invert_out }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
       case 1'1
         assign \o$22 $23
@@ -93453,7 +93527,7 @@ module \output$79
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \mul_op__insn_type
     connect \B 7'0001010
     connect \Y $29
   end
@@ -93473,7 +93547,7 @@ module \output$79
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \mul_op__insn_type
     connect \B 7'0001100
     connect \Y $31
   end
@@ -93624,7 +93698,7 @@ module \output$79
   end
   process $group_12
     assign \cr_a_ok 1'0
-    assign \cr_a_ok \op__write_cr0
+    assign \cr_a_ok \mul_op__write_cr0
     sync init
   end
   process $group_13
@@ -93633,22 +93707,22 @@ module \output$79
     sync init
   end
   process $group_14
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
-    assign \op__invert_a$10 1'0
-    assign \op__zero_a$11 1'0
-    assign \op__invert_out$12 1'0
-    assign \op__write_cr0$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28"
@@ -93662,8 +93736,8 @@ module \output$79
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \op__oe__oe
-    connect \B \op__oe__oe_ok
+    connect \A \mul_op__oe__oe
+    connect \B \mul_op__oe__oe_ok
     connect \Y $45
   end
   process $group_29
@@ -93748,7 +93822,7 @@ module \mul_pipe3
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -93823,8 +93897,8 @@ module \mul_pipe3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -93837,37 +93911,37 @@ module \mul_pipe3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 7 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 19 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 19 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 input 20 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 21 \xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 input 22 \neg_res
@@ -93877,9 +93951,9 @@ module \mul_pipe3
   wire width 1 output 24 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 25 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 26 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -93954,10 +94028,10 @@ module \mul_pipe3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 27 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 27 \mul_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -93970,93 +94044,93 @@ module \mul_pipe3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 28 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 29 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 30 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__invert_a$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 38 \op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$13$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 40 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 41 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 28 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 29 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 41 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 42 \o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 43 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 44 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 45 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 46 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ov$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 47 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 48 \xer_so$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so$18$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 49 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$next
   cell \p$77 \p
     connect \p_valid_i \p_valid_i
@@ -94066,7 +94140,7 @@ module \mul_pipe3
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul3_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -94141,8 +94215,8 @@ module \mul_pipe3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul3_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul3_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94155,41 +94229,41 @@ module \mul_pipe3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul3_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul3_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul3_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul3_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul3_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul3_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 \mul3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul3_xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 \mul3_neg_res
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul3_muxid$19
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -94264,8 +94338,8 @@ module \mul_pipe3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul3_op__insn_type$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul3_mul_op__insn_type$20
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94278,87 +94352,87 @@ module \mul_pipe3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul3_op__fn_unit$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul3_op__imm_data__imm$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__imm_data__imm_ok$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__rc__rc$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__rc__rc_ok$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__oe__oe$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__oe__oe_ok$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__invert_a$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__zero_a$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__invert_out$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__write_cr0$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__is_32bit$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul3_op__is_signed$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul3_op__insn$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul3_mul_op__fn_unit$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul3_mul_op__imm_data__imm$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__imm_data__imm_ok$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__rc__rc$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__rc__rc_ok$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__oe__oe$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__oe__oe_ok$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__invert_a$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__zero_a$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__invert_out$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__write_cr0$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__is_32bit$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__is_signed$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul3_mul_op__insn$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \mul3_o$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul3_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \mul3_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul3_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul3_xer_so$36
   cell \mul3 \mul3
     connect \muxid \mul3_muxid
-    connect \op__insn_type \mul3_op__insn_type
-    connect \op__fn_unit \mul3_op__fn_unit
-    connect \op__imm_data__imm \mul3_op__imm_data__imm
-    connect \op__imm_data__imm_ok \mul3_op__imm_data__imm_ok
-    connect \op__rc__rc \mul3_op__rc__rc
-    connect \op__rc__rc_ok \mul3_op__rc__rc_ok
-    connect \op__oe__oe \mul3_op__oe__oe
-    connect \op__oe__oe_ok \mul3_op__oe__oe_ok
-    connect \op__invert_a \mul3_op__invert_a
-    connect \op__zero_a \mul3_op__zero_a
-    connect \op__invert_out \mul3_op__invert_out
-    connect \op__write_cr0 \mul3_op__write_cr0
-    connect \op__is_32bit \mul3_op__is_32bit
-    connect \op__is_signed \mul3_op__is_signed
-    connect \op__insn \mul3_op__insn
+    connect \mul_op__insn_type \mul3_mul_op__insn_type
+    connect \mul_op__fn_unit \mul3_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul3_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul3_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul3_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul3_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul3_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul3_mul_op__invert_a
+    connect \mul_op__zero_a \mul3_mul_op__zero_a
+    connect \mul_op__invert_out \mul3_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul3_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul3_mul_op__is_32bit
+    connect \mul_op__is_signed \mul3_mul_op__is_signed
+    connect \mul_op__insn \mul3_mul_op__insn
     connect \o \mul3_o
     connect \xer_so \mul3_xer_so
     connect \neg_res \mul3_neg_res
     connect \muxid$1 \mul3_muxid$19
-    connect \op__insn_type$2 \mul3_op__insn_type$20
-    connect \op__fn_unit$3 \mul3_op__fn_unit$21
-    connect \op__imm_data__imm$4 \mul3_op__imm_data__imm$22
-    connect \op__imm_data__imm_ok$5 \mul3_op__imm_data__imm_ok$23
-    connect \op__rc__rc$6 \mul3_op__rc__rc$24
-    connect \op__rc__rc_ok$7 \mul3_op__rc__rc_ok$25
-    connect \op__oe__oe$8 \mul3_op__oe__oe$26
-    connect \op__oe__oe_ok$9 \mul3_op__oe__oe_ok$27
-    connect \op__invert_a$10 \mul3_op__invert_a$28
-    connect \op__zero_a$11 \mul3_op__zero_a$29
-    connect \op__invert_out$12 \mul3_op__invert_out$30
-    connect \op__write_cr0$13 \mul3_op__write_cr0$31
-    connect \op__is_32bit$14 \mul3_op__is_32bit$32
-    connect \op__is_signed$15 \mul3_op__is_signed$33
-    connect \op__insn$16 \mul3_op__insn$34
+    connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$20
+    connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$21
+    connect \mul_op__imm_data__imm$4 \mul3_mul_op__imm_data__imm$22
+    connect \mul_op__imm_data__imm_ok$5 \mul3_mul_op__imm_data__imm_ok$23
+    connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$24
+    connect \mul_op__rc__rc_ok$7 \mul3_mul_op__rc__rc_ok$25
+    connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$26
+    connect \mul_op__oe__oe_ok$9 \mul3_mul_op__oe__oe_ok$27
+    connect \mul_op__invert_a$10 \mul3_mul_op__invert_a$28
+    connect \mul_op__zero_a$11 \mul3_mul_op__zero_a$29
+    connect \mul_op__invert_out$12 \mul3_mul_op__invert_out$30
+    connect \mul_op__write_cr0$13 \mul3_mul_op__write_cr0$31
+    connect \mul_op__is_32bit$14 \mul3_mul_op__is_32bit$32
+    connect \mul_op__is_signed$15 \mul3_mul_op__is_signed$33
+    connect \mul_op__insn$16 \mul3_mul_op__insn$34
     connect \o$17 \mul3_o$35
     connect \o_ok \mul3_o_ok
     connect \xer_ov \mul3_xer_ov
     connect \xer_ov_ok \mul3_xer_ov_ok
     connect \xer_so$18 \mul3_xer_so$36
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -94433,8 +94507,8 @@ module \mul_pipe3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94447,45 +94521,45 @@ module \mul_pipe3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_so
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid$37
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -94560,8 +94634,8 @@ module \mul_pipe3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_mul_op__insn_type$38
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94574,88 +94648,88 @@ module \mul_pipe3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_a$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__zero_a$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__invert_out$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__write_cr0$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_mul_op__fn_unit$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_mul_op__imm_data__imm$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__imm_data__imm_ok$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc_ok$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe_ok$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_a$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__zero_a$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_out$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__write_cr0$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_32bit$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_signed$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_mul_op__insn$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ov$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_so$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_so_ok
   cell \output$79 \output
     connect \muxid \output_muxid
-    connect \op__insn_type \output_op__insn_type
-    connect \op__fn_unit \output_op__fn_unit
-    connect \op__imm_data__imm \output_op__imm_data__imm
-    connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
-    connect \op__rc__rc \output_op__rc__rc
-    connect \op__rc__rc_ok \output_op__rc__rc_ok
-    connect \op__oe__oe \output_op__oe__oe
-    connect \op__oe__oe_ok \output_op__oe__oe_ok
-    connect \op__invert_a \output_op__invert_a
-    connect \op__zero_a \output_op__zero_a
-    connect \op__invert_out \output_op__invert_out
-    connect \op__write_cr0 \output_op__write_cr0
-    connect \op__is_32bit \output_op__is_32bit
-    connect \op__is_signed \output_op__is_signed
-    connect \op__insn \output_op__insn
+    connect \mul_op__insn_type \output_mul_op__insn_type
+    connect \mul_op__fn_unit \output_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \output_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \output_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \output_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \output_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \output_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \output_mul_op__invert_a
+    connect \mul_op__zero_a \output_mul_op__zero_a
+    connect \mul_op__invert_out \output_mul_op__invert_out
+    connect \mul_op__write_cr0 \output_mul_op__write_cr0
+    connect \mul_op__is_32bit \output_mul_op__is_32bit
+    connect \mul_op__is_signed \output_mul_op__is_signed
+    connect \mul_op__insn \output_mul_op__insn
     connect \o \output_o
     connect \o_ok \output_o_ok
     connect \cr_a \output_cr_a
     connect \xer_ov \output_xer_ov
     connect \xer_so \output_xer_so
     connect \muxid$1 \output_muxid$37
-    connect \op__insn_type$2 \output_op__insn_type$38
-    connect \op__fn_unit$3 \output_op__fn_unit$39
-    connect \op__imm_data__imm$4 \output_op__imm_data__imm$40
-    connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$41
-    connect \op__rc__rc$6 \output_op__rc__rc$42
-    connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$43
-    connect \op__oe__oe$8 \output_op__oe__oe$44
-    connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$45
-    connect \op__invert_a$10 \output_op__invert_a$46
-    connect \op__zero_a$11 \output_op__zero_a$47
-    connect \op__invert_out$12 \output_op__invert_out$48
-    connect \op__write_cr0$13 \output_op__write_cr0$49
-    connect \op__is_32bit$14 \output_op__is_32bit$50
-    connect \op__is_signed$15 \output_op__is_signed$51
-    connect \op__insn$16 \output_op__insn$52
+    connect \mul_op__insn_type$2 \output_mul_op__insn_type$38
+    connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$39
+    connect \mul_op__imm_data__imm$4 \output_mul_op__imm_data__imm$40
+    connect \mul_op__imm_data__imm_ok$5 \output_mul_op__imm_data__imm_ok$41
+    connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$42
+    connect \mul_op__rc__rc_ok$7 \output_mul_op__rc__rc_ok$43
+    connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$44
+    connect \mul_op__oe__oe_ok$9 \output_mul_op__oe__oe_ok$45
+    connect \mul_op__invert_a$10 \output_mul_op__invert_a$46
+    connect \mul_op__zero_a$11 \output_mul_op__zero_a$47
+    connect \mul_op__invert_out$12 \output_mul_op__invert_out$48
+    connect \mul_op__write_cr0$13 \output_mul_op__write_cr0$49
+    connect \mul_op__is_32bit$14 \output_mul_op__is_32bit$50
+    connect \mul_op__is_signed$15 \output_mul_op__is_signed$51
+    connect \mul_op__insn$16 \output_mul_op__insn$52
     connect \o$17 \output_o$53
     connect \o_ok$18 \output_o_ok$54
     connect \cr_a$19 \output_cr_a$55
@@ -94671,22 +94745,22 @@ module \mul_pipe3
     sync init
   end
   process $group_1
-    assign \mul3_op__insn_type 7'0000000
-    assign \mul3_op__fn_unit 11'00000000000
-    assign \mul3_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul3_op__imm_data__imm_ok 1'0
-    assign \mul3_op__rc__rc 1'0
-    assign \mul3_op__rc__rc_ok 1'0
-    assign \mul3_op__oe__oe 1'0
-    assign \mul3_op__oe__oe_ok 1'0
-    assign \mul3_op__invert_a 1'0
-    assign \mul3_op__zero_a 1'0
-    assign \mul3_op__invert_out 1'0
-    assign \mul3_op__write_cr0 1'0
-    assign \mul3_op__is_32bit 1'0
-    assign \mul3_op__is_signed 1'0
-    assign \mul3_op__insn 32'00000000000000000000000000000000
-    assign { \mul3_op__insn \mul3_op__is_signed \mul3_op__is_32bit \mul3_op__write_cr0 \mul3_op__invert_out \mul3_op__zero_a \mul3_op__invert_a { \mul3_op__oe__oe_ok \mul3_op__oe__oe } { \mul3_op__rc__rc_ok \mul3_op__rc__rc } { \mul3_op__imm_data__imm_ok \mul3_op__imm_data__imm } \mul3_op__fn_unit \mul3_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul3_mul_op__insn_type 7'0000000
+    assign \mul3_mul_op__fn_unit 11'00000000000
+    assign \mul3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul3_mul_op__imm_data__imm_ok 1'0
+    assign \mul3_mul_op__rc__rc 1'0
+    assign \mul3_mul_op__rc__rc_ok 1'0
+    assign \mul3_mul_op__oe__oe 1'0
+    assign \mul3_mul_op__oe__oe_ok 1'0
+    assign \mul3_mul_op__invert_a 1'0
+    assign \mul3_mul_op__zero_a 1'0
+    assign \mul3_mul_op__invert_out 1'0
+    assign \mul3_mul_op__write_cr0 1'0
+    assign \mul3_mul_op__is_32bit 1'0
+    assign \mul3_mul_op__is_signed 1'0
+    assign \mul3_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__invert_out \mul3_mul_op__zero_a \mul3_mul_op__invert_a { \mul3_mul_op__oe__oe_ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__rc_ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
   process $group_16
@@ -94717,22 +94791,22 @@ module \mul_pipe3
     sync init
   end
   process $group_21
-    assign \output_op__insn_type 7'0000000
-    assign \output_op__fn_unit 11'00000000000
-    assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_op__imm_data__imm_ok 1'0
-    assign \output_op__rc__rc 1'0
-    assign \output_op__rc__rc_ok 1'0
-    assign \output_op__oe__oe 1'0
-    assign \output_op__oe__oe_ok 1'0
-    assign \output_op__invert_a 1'0
-    assign \output_op__zero_a 1'0
-    assign \output_op__invert_out 1'0
-    assign \output_op__write_cr0 1'0
-    assign \output_op__is_32bit 1'0
-    assign \output_op__is_signed 1'0
-    assign \output_op__insn 32'00000000000000000000000000000000
-    assign { \output_op__insn \output_op__is_signed \output_op__is_32bit \output_op__write_cr0 \output_op__invert_out \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \mul3_op__insn$34 \mul3_op__is_signed$33 \mul3_op__is_32bit$32 \mul3_op__write_cr0$31 \mul3_op__invert_out$30 \mul3_op__zero_a$29 \mul3_op__invert_a$28 { \mul3_op__oe__oe_ok$27 \mul3_op__oe__oe$26 } { \mul3_op__rc__rc_ok$25 \mul3_op__rc__rc$24 } { \mul3_op__imm_data__imm_ok$23 \mul3_op__imm_data__imm$22 } \mul3_op__fn_unit$21 \mul3_op__insn_type$20 }
+    assign \output_mul_op__insn_type 7'0000000
+    assign \output_mul_op__fn_unit 11'00000000000
+    assign \output_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_mul_op__imm_data__imm_ok 1'0
+    assign \output_mul_op__rc__rc 1'0
+    assign \output_mul_op__rc__rc_ok 1'0
+    assign \output_mul_op__oe__oe 1'0
+    assign \output_mul_op__oe__oe_ok 1'0
+    assign \output_mul_op__invert_a 1'0
+    assign \output_mul_op__zero_a 1'0
+    assign \output_mul_op__invert_out 1'0
+    assign \output_mul_op__write_cr0 1'0
+    assign \output_mul_op__is_32bit 1'0
+    assign \output_mul_op__is_signed 1'0
+    assign \output_mul_op__insn 32'00000000000000000000000000000000
+    assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__invert_out \output_mul_op__zero_a \output_mul_op__invert_a { \output_mul_op__oe__oe_ok \output_mul_op__oe__oe } { \output_mul_op__rc__rc_ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$34 \mul3_mul_op__is_signed$33 \mul3_mul_op__is_32bit$32 \mul3_mul_op__write_cr0$31 \mul3_mul_op__invert_out$30 \mul3_mul_op__zero_a$29 \mul3_mul_op__invert_a$28 { \mul3_mul_op__oe__oe_ok$27 \mul3_mul_op__oe__oe$26 } { \mul3_mul_op__rc__rc_ok$25 \mul3_mul_op__rc__rc$24 } { \mul3_mul_op__imm_data__imm_ok$23 \mul3_mul_op__imm_data__imm$22 } \mul3_mul_op__fn_unit$21 \mul3_mul_op__insn_type$20 }
     sync init
   end
   process $group_36
@@ -94741,11 +94815,11 @@ module \mul_pipe3
     assign { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$35 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$61
   process $group_38
     assign \output_cr_a 4'0000
@@ -94753,7 +94827,7 @@ module \mul_pipe3
     assign { \cr_a_ok$59 \output_cr_a } { \cr_a_ok$61 \cr_a$60 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$62
   process $group_40
     assign \output_xer_ov 2'00
@@ -94761,9 +94835,9 @@ module \mul_pipe3
     assign { \xer_ov_ok$62 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$64
   process $group_42
     assign \output_xer_so 1'0
@@ -94805,7 +94879,7 @@ module \mul_pipe3
     assign \p_valid_i_p_ready_o $66
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$68
   process $group_47
     assign \muxid$68 2'00
@@ -94885,8 +94959,8 @@ module \mul_pipe3
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$69
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94899,56 +94973,56 @@ module \mul_pipe3
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$83
   process $group_48
-    assign \op__insn_type$69 7'0000000
-    assign \op__fn_unit$70 11'00000000000
-    assign \op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$72 1'0
-    assign \op__rc__rc$73 1'0
-    assign \op__rc__rc_ok$74 1'0
-    assign \op__oe__oe$75 1'0
-    assign \op__oe__oe_ok$76 1'0
-    assign \op__invert_a$77 1'0
-    assign \op__zero_a$78 1'0
-    assign \op__invert_out$79 1'0
-    assign \op__write_cr0$80 1'0
-    assign \op__is_32bit$81 1'0
-    assign \op__is_signed$82 1'0
-    assign \op__insn$83 32'00000000000000000000000000000000
-    assign { \op__insn$83 \op__is_signed$82 \op__is_32bit$81 \op__write_cr0$80 \op__invert_out$79 \op__zero_a$78 \op__invert_a$77 { \op__oe__oe_ok$76 \op__oe__oe$75 } { \op__rc__rc_ok$74 \op__rc__rc$73 } { \op__imm_data__imm_ok$72 \op__imm_data__imm$71 } \op__fn_unit$70 \op__insn_type$69 } { \output_op__insn$52 \output_op__is_signed$51 \output_op__is_32bit$50 \output_op__write_cr0$49 \output_op__invert_out$48 \output_op__zero_a$47 \output_op__invert_a$46 { \output_op__oe__oe_ok$45 \output_op__oe__oe$44 } { \output_op__rc__rc_ok$43 \output_op__rc__rc$42 } { \output_op__imm_data__imm_ok$41 \output_op__imm_data__imm$40 } \output_op__fn_unit$39 \output_op__insn_type$38 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+    assign \mul_op__insn_type$69 7'0000000
+    assign \mul_op__fn_unit$70 11'00000000000
+    assign \mul_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$72 1'0
+    assign \mul_op__rc__rc$73 1'0
+    assign \mul_op__rc__rc_ok$74 1'0
+    assign \mul_op__oe__oe$75 1'0
+    assign \mul_op__oe__oe_ok$76 1'0
+    assign \mul_op__invert_a$77 1'0
+    assign \mul_op__zero_a$78 1'0
+    assign \mul_op__invert_out$79 1'0
+    assign \mul_op__write_cr0$80 1'0
+    assign \mul_op__is_32bit$81 1'0
+    assign \mul_op__is_signed$82 1'0
+    assign \mul_op__insn$83 32'00000000000000000000000000000000
+    assign { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 } { \output_mul_op__insn$52 \output_mul_op__is_signed$51 \output_mul_op__is_32bit$50 \output_mul_op__write_cr0$49 \output_mul_op__invert_out$48 \output_mul_op__zero_a$47 \output_mul_op__invert_a$46 { \output_mul_op__oe__oe_ok$45 \output_mul_op__oe__oe$44 } { \output_mul_op__rc__rc_ok$43 \output_mul_op__rc__rc$42 } { \output_mul_op__imm_data__imm_ok$41 \output_mul_op__imm_data__imm$40 } \output_mul_op__fn_unit$39 \output_mul_op__insn_type$38 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$85
   process $group_63
     assign \o$84 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -94956,9 +95030,9 @@ module \mul_pipe3
     assign { \o_ok$85 \o$84 } { \output_o_ok$54 \output_o$53 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$87
   process $group_65
     assign \cr_a$86 4'0000
@@ -94966,9 +95040,9 @@ module \mul_pipe3
     assign { \cr_a_ok$87 \cr_a$86 } { \output_cr_a_ok \output_cr_a$55 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ov$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ov_ok$89
   process $group_67
     assign \xer_ov$88 2'00
@@ -94976,9 +95050,9 @@ module \mul_pipe3
     assign { \xer_ov_ok$89 \xer_ov$88 } { \output_xer_ov_ok \output_xer_ov$56 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_so_ok$91
   process $group_69
     assign \xer_so$90 1'0
@@ -95028,72 +95102,72 @@ module \mul_pipe3
       update \muxid$1 \muxid$1$next
   end
   process $group_73
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__imm_data__imm$4$next \op__imm_data__imm$4
-    assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
-    assign \op__rc__rc$6$next \op__rc__rc$6
-    assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
-    assign \op__oe__oe$8$next \op__oe__oe$8
-    assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
-    assign \op__invert_a$10$next \op__invert_a$10
-    assign \op__zero_a$11$next \op__zero_a$11
-    assign \op__invert_out$12$next \op__invert_out$12
-    assign \op__write_cr0$13$next \op__write_cr0$13
-    assign \op__is_32bit$14$next \op__is_32bit$14
-    assign \op__is_signed$15$next \op__is_signed$15
-    assign \op__insn$16$next \op__insn$16
+    assign \mul_op__insn_type$2$next \mul_op__insn_type$2
+    assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3
+    assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4
+    assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5
+    assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6
+    assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7
+    assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8
+    assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9
+    assign \mul_op__invert_a$10$next \mul_op__invert_a$10
+    assign \mul_op__zero_a$11$next \mul_op__zero_a$11
+    assign \mul_op__invert_out$12$next \mul_op__invert_out$12
+    assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13
+    assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14
+    assign \mul_op__is_signed$15$next \mul_op__is_signed$15
+    assign \mul_op__insn$16$next \mul_op__insn$16
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$83 \op__is_signed$82 \op__is_32bit$81 \op__write_cr0$80 \op__invert_out$79 \op__zero_a$78 \op__invert_a$77 { \op__oe__oe_ok$76 \op__oe__oe$75 } { \op__rc__rc_ok$74 \op__rc__rc$73 } { \op__imm_data__imm_ok$72 \op__imm_data__imm$71 } \op__fn_unit$70 \op__insn_type$69 }
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$83 \op__is_signed$82 \op__is_32bit$81 \op__write_cr0$80 \op__invert_out$79 \op__zero_a$78 \op__invert_a$77 { \op__oe__oe_ok$76 \op__oe__oe$75 } { \op__rc__rc_ok$74 \op__rc__rc$73 } { \op__imm_data__imm_ok$72 \op__imm_data__imm$71 } \op__fn_unit$70 \op__insn_type$69 }
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \op__imm_data__imm_ok$5$next 1'0
-        assign \op__rc__rc$6$next 1'0
-        assign \op__rc__rc_ok$7$next 1'0
-        assign \op__oe__oe$8$next 1'0
-        assign \op__oe__oe_ok$9$next 1'0
-    end
-    sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__imm_data__imm_ok$5 1'0
-      update \op__rc__rc$6 1'0
-      update \op__rc__rc_ok$7 1'0
-      update \op__oe__oe$8 1'0
-      update \op__oe__oe_ok$9 1'0
-      update \op__invert_a$10 1'0
-      update \op__zero_a$11 1'0
-      update \op__invert_out$12 1'0
-      update \op__write_cr0$13 1'0
-      update \op__is_32bit$14 1'0
-      update \op__is_signed$15 1'0
-      update \op__insn$16 32'00000000000000000000000000000000
+        assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \mul_op__imm_data__imm_ok$5$next 1'0
+        assign \mul_op__rc__rc$6$next 1'0
+        assign \mul_op__rc__rc_ok$7$next 1'0
+        assign \mul_op__oe__oe$8$next 1'0
+        assign \mul_op__oe__oe_ok$9$next 1'0
+    end
+    sync init
+      update \mul_op__insn_type$2 7'0000000
+      update \mul_op__fn_unit$3 11'00000000000
+      update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \mul_op__imm_data__imm_ok$5 1'0
+      update \mul_op__rc__rc$6 1'0
+      update \mul_op__rc__rc_ok$7 1'0
+      update \mul_op__oe__oe$8 1'0
+      update \mul_op__oe__oe_ok$9 1'0
+      update \mul_op__invert_a$10 1'0
+      update \mul_op__zero_a$11 1'0
+      update \mul_op__invert_out$12 1'0
+      update \mul_op__write_cr0$13 1'0
+      update \mul_op__is_32bit$14 1'0
+      update \mul_op__is_signed$15 1'0
+      update \mul_op__insn$16 32'00000000000000000000000000000000
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__imm_data__imm$4 \op__imm_data__imm$4$next
-      update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
-      update \op__rc__rc$6 \op__rc__rc$6$next
-      update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
-      update \op__oe__oe$8 \op__oe__oe$8$next
-      update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
-      update \op__invert_a$10 \op__invert_a$10$next
-      update \op__zero_a$11 \op__zero_a$11$next
-      update \op__invert_out$12 \op__invert_out$12$next
-      update \op__write_cr0$13 \op__write_cr0$13$next
-      update \op__is_32bit$14 \op__is_32bit$14$next
-      update \op__is_signed$15 \op__is_signed$15$next
-      update \op__insn$16 \op__insn$16$next
+      update \mul_op__insn_type$2 \mul_op__insn_type$2$next
+      update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next
+      update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next
+      update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next
+      update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next
+      update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next
+      update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next
+      update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next
+      update \mul_op__invert_a$10 \mul_op__invert_a$10$next
+      update \mul_op__zero_a$11 \mul_op__zero_a$11$next
+      update \mul_op__invert_out$12 \mul_op__invert_out$12$next
+      update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next
+      update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next
+      update \mul_op__is_signed$15 \mul_op__is_signed$15$next
+      update \mul_op__insn$16 \mul_op__insn$16$next
   end
   process $group_88
     assign \o$17$next \o$17
@@ -95212,25 +95286,25 @@ module \alu_mul0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 5 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 6 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 7 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 8 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 9 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 10 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 11 \xer_so
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -95305,8 +95379,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 12 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 12 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95319,39 +95393,39 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 13 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 14 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 20 \op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 21 \op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 22 \op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 23 \op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 24 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 25 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 26 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 13 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 14 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 21 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 22 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 23 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 24 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 25 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 26 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 27 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 28 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 input 29 \xer_so$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 30 \p_valid_i
@@ -95369,7 +95443,7 @@ module \alu_mul0
   wire width 1 \mul_pipe1_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \mul_pipe1_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul_pipe1_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -95444,8 +95518,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul_pipe1_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe1_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95458,39 +95532,39 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul_pipe1_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul_pipe1_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul_pipe1_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe1_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe1_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe1_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul_pipe1_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul_pipe1_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul_pipe1_xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 \mul_pipe1_neg_res
@@ -95500,7 +95574,7 @@ module \alu_mul0
   wire width 1 \mul_pipe1_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \mul_pipe1_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul_pipe1_muxid$2
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -95575,8 +95649,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul_pipe1_op__insn_type$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe1_mul_op__insn_type$3
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95589,39 +95663,39 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul_pipe1_op__fn_unit$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul_pipe1_op__imm_data__imm$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__imm_data__imm_ok$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__rc__rc$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__rc__rc_ok$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__oe__oe$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__oe__oe_ok$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__invert_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__zero_a$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__invert_out$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__write_cr0$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__is_32bit$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe1_op__is_signed$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul_pipe1_op__insn$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe1_mul_op__fn_unit$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe1_mul_op__imm_data__imm$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc_ok$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe_ok$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__zero_a$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_32bit$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_signed$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe1_mul_op__insn$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul_pipe1_ra$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul_pipe1_rb$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul_pipe1_xer_so$20
   cell \mul_pipe1 \mul_pipe1
     connect \rst \rst
@@ -95629,21 +95703,21 @@ module \alu_mul0
     connect \n_valid_o \mul_pipe1_n_valid_o
     connect \n_ready_i \mul_pipe1_n_ready_i
     connect \muxid \mul_pipe1_muxid
-    connect \op__insn_type \mul_pipe1_op__insn_type
-    connect \op__fn_unit \mul_pipe1_op__fn_unit
-    connect \op__imm_data__imm \mul_pipe1_op__imm_data__imm
-    connect \op__imm_data__imm_ok \mul_pipe1_op__imm_data__imm_ok
-    connect \op__rc__rc \mul_pipe1_op__rc__rc
-    connect \op__rc__rc_ok \mul_pipe1_op__rc__rc_ok
-    connect \op__oe__oe \mul_pipe1_op__oe__oe
-    connect \op__oe__oe_ok \mul_pipe1_op__oe__oe_ok
-    connect \op__invert_a \mul_pipe1_op__invert_a
-    connect \op__zero_a \mul_pipe1_op__zero_a
-    connect \op__invert_out \mul_pipe1_op__invert_out
-    connect \op__write_cr0 \mul_pipe1_op__write_cr0
-    connect \op__is_32bit \mul_pipe1_op__is_32bit
-    connect \op__is_signed \mul_pipe1_op__is_signed
-    connect \op__insn \mul_pipe1_op__insn
+    connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type
+    connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul_pipe1_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul_pipe1_mul_op__invert_a
+    connect \mul_op__zero_a \mul_pipe1_mul_op__zero_a
+    connect \mul_op__invert_out \mul_pipe1_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit
+    connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed
+    connect \mul_op__insn \mul_pipe1_mul_op__insn
     connect \ra \mul_pipe1_ra
     connect \rb \mul_pipe1_rb
     connect \xer_so \mul_pipe1_xer_so
@@ -95652,21 +95726,21 @@ module \alu_mul0
     connect \p_valid_i \mul_pipe1_p_valid_i
     connect \p_ready_o \mul_pipe1_p_ready_o
     connect \muxid$1 \mul_pipe1_muxid$2
-    connect \op__insn_type$2 \mul_pipe1_op__insn_type$3
-    connect \op__fn_unit$3 \mul_pipe1_op__fn_unit$4
-    connect \op__imm_data__imm$4 \mul_pipe1_op__imm_data__imm$5
-    connect \op__imm_data__imm_ok$5 \mul_pipe1_op__imm_data__imm_ok$6
-    connect \op__rc__rc$6 \mul_pipe1_op__rc__rc$7
-    connect \op__rc__rc_ok$7 \mul_pipe1_op__rc__rc_ok$8
-    connect \op__oe__oe$8 \mul_pipe1_op__oe__oe$9
-    connect \op__oe__oe_ok$9 \mul_pipe1_op__oe__oe_ok$10
-    connect \op__invert_a$10 \mul_pipe1_op__invert_a$11
-    connect \op__zero_a$11 \mul_pipe1_op__zero_a$12
-    connect \op__invert_out$12 \mul_pipe1_op__invert_out$13
-    connect \op__write_cr0$13 \mul_pipe1_op__write_cr0$14
-    connect \op__is_32bit$14 \mul_pipe1_op__is_32bit$15
-    connect \op__is_signed$15 \mul_pipe1_op__is_signed$16
-    connect \op__insn$16 \mul_pipe1_op__insn$17
+    connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3
+    connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4
+    connect \mul_op__imm_data__imm$4 \mul_pipe1_mul_op__imm_data__imm$5
+    connect \mul_op__imm_data__imm_ok$5 \mul_pipe1_mul_op__imm_data__imm_ok$6
+    connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7
+    connect \mul_op__rc__rc_ok$7 \mul_pipe1_mul_op__rc__rc_ok$8
+    connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9
+    connect \mul_op__oe__oe_ok$9 \mul_pipe1_mul_op__oe__oe_ok$10
+    connect \mul_op__invert_a$10 \mul_pipe1_mul_op__invert_a$11
+    connect \mul_op__zero_a$11 \mul_pipe1_mul_op__zero_a$12
+    connect \mul_op__invert_out$12 \mul_pipe1_mul_op__invert_out$13
+    connect \mul_op__write_cr0$13 \mul_pipe1_mul_op__write_cr0$14
+    connect \mul_op__is_32bit$14 \mul_pipe1_mul_op__is_32bit$15
+    connect \mul_op__is_signed$15 \mul_pipe1_mul_op__is_signed$16
+    connect \mul_op__insn$16 \mul_pipe1_mul_op__insn$17
     connect \ra$17 \mul_pipe1_ra$18
     connect \rb$18 \mul_pipe1_rb$19
     connect \xer_so$19 \mul_pipe1_xer_so$20
@@ -95675,7 +95749,7 @@ module \alu_mul0
   wire width 1 \mul_pipe2_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \mul_pipe2_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul_pipe2_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -95750,8 +95824,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul_pipe2_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe2_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95764,39 +95838,39 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul_pipe2_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul_pipe2_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul_pipe2_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe2_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe2_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe2_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul_pipe2_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \mul_pipe2_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul_pipe2_xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
   wire width 1 \mul_pipe2_neg_res
@@ -95806,7 +95880,7 @@ module \alu_mul0
   wire width 1 \mul_pipe2_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \mul_pipe2_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul_pipe2_muxid$21
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -95881,8 +95955,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul_pipe2_op__insn_type$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe2_mul_op__insn_type$22
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95895,37 +95969,37 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul_pipe2_op__fn_unit$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul_pipe2_op__imm_data__imm$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__imm_data__imm_ok$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__rc__rc$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__rc__rc_ok$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__oe__oe$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__oe__oe_ok$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__invert_a$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__zero_a$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__invert_out$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__write_cr0$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__is_32bit$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe2_op__is_signed$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul_pipe2_op__insn$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe2_mul_op__fn_unit$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe2_mul_op__imm_data__imm$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc_ok$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe_ok$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_a$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__zero_a$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_out$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__write_cr0$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_32bit$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_signed$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe2_mul_op__insn$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 \mul_pipe2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul_pipe2_xer_so$37
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 \mul_pipe2_neg_res$38
@@ -95937,21 +96011,21 @@ module \alu_mul0
     connect \p_valid_i \mul_pipe2_p_valid_i
     connect \p_ready_o \mul_pipe2_p_ready_o
     connect \muxid \mul_pipe2_muxid
-    connect \op__insn_type \mul_pipe2_op__insn_type
-    connect \op__fn_unit \mul_pipe2_op__fn_unit
-    connect \op__imm_data__imm \mul_pipe2_op__imm_data__imm
-    connect \op__imm_data__imm_ok \mul_pipe2_op__imm_data__imm_ok
-    connect \op__rc__rc \mul_pipe2_op__rc__rc
-    connect \op__rc__rc_ok \mul_pipe2_op__rc__rc_ok
-    connect \op__oe__oe \mul_pipe2_op__oe__oe
-    connect \op__oe__oe_ok \mul_pipe2_op__oe__oe_ok
-    connect \op__invert_a \mul_pipe2_op__invert_a
-    connect \op__zero_a \mul_pipe2_op__zero_a
-    connect \op__invert_out \mul_pipe2_op__invert_out
-    connect \op__write_cr0 \mul_pipe2_op__write_cr0
-    connect \op__is_32bit \mul_pipe2_op__is_32bit
-    connect \op__is_signed \mul_pipe2_op__is_signed
-    connect \op__insn \mul_pipe2_op__insn
+    connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type
+    connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul_pipe2_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul_pipe2_mul_op__invert_a
+    connect \mul_op__zero_a \mul_pipe2_mul_op__zero_a
+    connect \mul_op__invert_out \mul_pipe2_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit
+    connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed
+    connect \mul_op__insn \mul_pipe2_mul_op__insn
     connect \ra \mul_pipe2_ra
     connect \rb \mul_pipe2_rb
     connect \xer_so \mul_pipe2_xer_so
@@ -95960,21 +96034,21 @@ module \alu_mul0
     connect \n_valid_o \mul_pipe2_n_valid_o
     connect \n_ready_i \mul_pipe2_n_ready_i
     connect \muxid$1 \mul_pipe2_muxid$21
-    connect \op__insn_type$2 \mul_pipe2_op__insn_type$22
-    connect \op__fn_unit$3 \mul_pipe2_op__fn_unit$23
-    connect \op__imm_data__imm$4 \mul_pipe2_op__imm_data__imm$24
-    connect \op__imm_data__imm_ok$5 \mul_pipe2_op__imm_data__imm_ok$25
-    connect \op__rc__rc$6 \mul_pipe2_op__rc__rc$26
-    connect \op__rc__rc_ok$7 \mul_pipe2_op__rc__rc_ok$27
-    connect \op__oe__oe$8 \mul_pipe2_op__oe__oe$28
-    connect \op__oe__oe_ok$9 \mul_pipe2_op__oe__oe_ok$29
-    connect \op__invert_a$10 \mul_pipe2_op__invert_a$30
-    connect \op__zero_a$11 \mul_pipe2_op__zero_a$31
-    connect \op__invert_out$12 \mul_pipe2_op__invert_out$32
-    connect \op__write_cr0$13 \mul_pipe2_op__write_cr0$33
-    connect \op__is_32bit$14 \mul_pipe2_op__is_32bit$34
-    connect \op__is_signed$15 \mul_pipe2_op__is_signed$35
-    connect \op__insn$16 \mul_pipe2_op__insn$36
+    connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$22
+    connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$23
+    connect \mul_op__imm_data__imm$4 \mul_pipe2_mul_op__imm_data__imm$24
+    connect \mul_op__imm_data__imm_ok$5 \mul_pipe2_mul_op__imm_data__imm_ok$25
+    connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$26
+    connect \mul_op__rc__rc_ok$7 \mul_pipe2_mul_op__rc__rc_ok$27
+    connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$28
+    connect \mul_op__oe__oe_ok$9 \mul_pipe2_mul_op__oe__oe_ok$29
+    connect \mul_op__invert_a$10 \mul_pipe2_mul_op__invert_a$30
+    connect \mul_op__zero_a$11 \mul_pipe2_mul_op__zero_a$31
+    connect \mul_op__invert_out$12 \mul_pipe2_mul_op__invert_out$32
+    connect \mul_op__write_cr0$13 \mul_pipe2_mul_op__write_cr0$33
+    connect \mul_op__is_32bit$14 \mul_pipe2_mul_op__is_32bit$34
+    connect \mul_op__is_signed$15 \mul_pipe2_mul_op__is_signed$35
+    connect \mul_op__insn$16 \mul_pipe2_mul_op__insn$36
     connect \o \mul_pipe2_o
     connect \xer_so$17 \mul_pipe2_xer_so$37
     connect \neg_res$18 \mul_pipe2_neg_res$38
@@ -95984,7 +96058,7 @@ module \alu_mul0
   wire width 1 \mul_pipe3_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \mul_pipe3_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul_pipe3_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -96059,8 +96133,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul_pipe3_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe3_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -96073,37 +96147,37 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul_pipe3_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul_pipe3_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul_pipe3_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe3_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe3_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe3_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 129 \mul_pipe3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \mul_pipe3_xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
   wire width 1 \mul_pipe3_neg_res
@@ -96113,7 +96187,7 @@ module \alu_mul0
   wire width 1 \mul_pipe3_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \mul_pipe3_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \mul_pipe3_muxid$40
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -96188,8 +96262,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \mul_pipe3_op__insn_type$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe3_mul_op__insn_type$41
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -96202,49 +96276,49 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \mul_pipe3_op__fn_unit$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \mul_pipe3_op__imm_data__imm$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__imm_data__imm_ok$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__rc__rc$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__rc__rc_ok$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__oe__oe$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__oe__oe_ok$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__invert_a$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__zero_a$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__invert_out$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__write_cr0$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__is_32bit$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \mul_pipe3_op__is_signed$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \mul_pipe3_op__insn$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe3_mul_op__fn_unit$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe3_mul_op__imm_data__imm$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc_ok$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe_ok$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_a$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__zero_a$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_out$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__write_cr0$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_32bit$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_signed$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe3_mul_op__insn$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \mul_pipe3_o$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul_pipe3_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \mul_pipe3_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul_pipe3_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \mul_pipe3_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul_pipe3_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul_pipe3_xer_so$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \mul_pipe3_xer_so_ok
   cell \mul_pipe3 \mul_pipe3
     connect \rst \rst
@@ -96252,21 +96326,21 @@ module \alu_mul0
     connect \p_valid_i \mul_pipe3_p_valid_i
     connect \p_ready_o \mul_pipe3_p_ready_o
     connect \muxid \mul_pipe3_muxid
-    connect \op__insn_type \mul_pipe3_op__insn_type
-    connect \op__fn_unit \mul_pipe3_op__fn_unit
-    connect \op__imm_data__imm \mul_pipe3_op__imm_data__imm
-    connect \op__imm_data__imm_ok \mul_pipe3_op__imm_data__imm_ok
-    connect \op__rc__rc \mul_pipe3_op__rc__rc
-    connect \op__rc__rc_ok \mul_pipe3_op__rc__rc_ok
-    connect \op__oe__oe \mul_pipe3_op__oe__oe
-    connect \op__oe__oe_ok \mul_pipe3_op__oe__oe_ok
-    connect \op__invert_a \mul_pipe3_op__invert_a
-    connect \op__zero_a \mul_pipe3_op__zero_a
-    connect \op__invert_out \mul_pipe3_op__invert_out
-    connect \op__write_cr0 \mul_pipe3_op__write_cr0
-    connect \op__is_32bit \mul_pipe3_op__is_32bit
-    connect \op__is_signed \mul_pipe3_op__is_signed
-    connect \op__insn \mul_pipe3_op__insn
+    connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type
+    connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul_pipe3_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul_pipe3_mul_op__invert_a
+    connect \mul_op__zero_a \mul_pipe3_mul_op__zero_a
+    connect \mul_op__invert_out \mul_pipe3_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit
+    connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed
+    connect \mul_op__insn \mul_pipe3_mul_op__insn
     connect \o \mul_pipe3_o
     connect \xer_so \mul_pipe3_xer_so
     connect \neg_res \mul_pipe3_neg_res
@@ -96274,21 +96348,21 @@ module \alu_mul0
     connect \n_valid_o \mul_pipe3_n_valid_o
     connect \n_ready_i \mul_pipe3_n_ready_i
     connect \muxid$1 \mul_pipe3_muxid$40
-    connect \op__insn_type$2 \mul_pipe3_op__insn_type$41
-    connect \op__fn_unit$3 \mul_pipe3_op__fn_unit$42
-    connect \op__imm_data__imm$4 \mul_pipe3_op__imm_data__imm$43
-    connect \op__imm_data__imm_ok$5 \mul_pipe3_op__imm_data__imm_ok$44
-    connect \op__rc__rc$6 \mul_pipe3_op__rc__rc$45
-    connect \op__rc__rc_ok$7 \mul_pipe3_op__rc__rc_ok$46
-    connect \op__oe__oe$8 \mul_pipe3_op__oe__oe$47
-    connect \op__oe__oe_ok$9 \mul_pipe3_op__oe__oe_ok$48
-    connect \op__invert_a$10 \mul_pipe3_op__invert_a$49
-    connect \op__zero_a$11 \mul_pipe3_op__zero_a$50
-    connect \op__invert_out$12 \mul_pipe3_op__invert_out$51
-    connect \op__write_cr0$13 \mul_pipe3_op__write_cr0$52
-    connect \op__is_32bit$14 \mul_pipe3_op__is_32bit$53
-    connect \op__is_signed$15 \mul_pipe3_op__is_signed$54
-    connect \op__insn$16 \mul_pipe3_op__insn$55
+    connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$41
+    connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$42
+    connect \mul_op__imm_data__imm$4 \mul_pipe3_mul_op__imm_data__imm$43
+    connect \mul_op__imm_data__imm_ok$5 \mul_pipe3_mul_op__imm_data__imm_ok$44
+    connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$45
+    connect \mul_op__rc__rc_ok$7 \mul_pipe3_mul_op__rc__rc_ok$46
+    connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$47
+    connect \mul_op__oe__oe_ok$9 \mul_pipe3_mul_op__oe__oe_ok$48
+    connect \mul_op__invert_a$10 \mul_pipe3_mul_op__invert_a$49
+    connect \mul_op__zero_a$11 \mul_pipe3_mul_op__zero_a$50
+    connect \mul_op__invert_out$12 \mul_pipe3_mul_op__invert_out$51
+    connect \mul_op__write_cr0$13 \mul_pipe3_mul_op__write_cr0$52
+    connect \mul_op__is_32bit$14 \mul_pipe3_mul_op__is_32bit$53
+    connect \mul_op__is_signed$15 \mul_pipe3_mul_op__is_signed$54
+    connect \mul_op__insn$16 \mul_pipe3_mul_op__insn$55
     connect \o$17 \mul_pipe3_o$56
     connect \o_ok \mul_pipe3_o_ok
     connect \cr_a \mul_pipe3_cr_a
@@ -96314,22 +96388,22 @@ module \alu_mul0
     sync init
   end
   process $group_3
-    assign \mul_pipe2_op__insn_type 7'0000000
-    assign \mul_pipe2_op__fn_unit 11'00000000000
-    assign \mul_pipe2_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe2_op__imm_data__imm_ok 1'0
-    assign \mul_pipe2_op__rc__rc 1'0
-    assign \mul_pipe2_op__rc__rc_ok 1'0
-    assign \mul_pipe2_op__oe__oe 1'0
-    assign \mul_pipe2_op__oe__oe_ok 1'0
-    assign \mul_pipe2_op__invert_a 1'0
-    assign \mul_pipe2_op__zero_a 1'0
-    assign \mul_pipe2_op__invert_out 1'0
-    assign \mul_pipe2_op__write_cr0 1'0
-    assign \mul_pipe2_op__is_32bit 1'0
-    assign \mul_pipe2_op__is_signed 1'0
-    assign \mul_pipe2_op__insn 32'00000000000000000000000000000000
-    assign { \mul_pipe2_op__insn \mul_pipe2_op__is_signed \mul_pipe2_op__is_32bit \mul_pipe2_op__write_cr0 \mul_pipe2_op__invert_out \mul_pipe2_op__zero_a \mul_pipe2_op__invert_a { \mul_pipe2_op__oe__oe_ok \mul_pipe2_op__oe__oe } { \mul_pipe2_op__rc__rc_ok \mul_pipe2_op__rc__rc } { \mul_pipe2_op__imm_data__imm_ok \mul_pipe2_op__imm_data__imm } \mul_pipe2_op__fn_unit \mul_pipe2_op__insn_type } { \mul_pipe1_op__insn \mul_pipe1_op__is_signed \mul_pipe1_op__is_32bit \mul_pipe1_op__write_cr0 \mul_pipe1_op__invert_out \mul_pipe1_op__zero_a \mul_pipe1_op__invert_a { \mul_pipe1_op__oe__oe_ok \mul_pipe1_op__oe__oe } { \mul_pipe1_op__rc__rc_ok \mul_pipe1_op__rc__rc } { \mul_pipe1_op__imm_data__imm_ok \mul_pipe1_op__imm_data__imm } \mul_pipe1_op__fn_unit \mul_pipe1_op__insn_type }
+    assign \mul_pipe2_mul_op__insn_type 7'0000000
+    assign \mul_pipe2_mul_op__fn_unit 11'00000000000
+    assign \mul_pipe2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe2_mul_op__imm_data__imm_ok 1'0
+    assign \mul_pipe2_mul_op__rc__rc 1'0
+    assign \mul_pipe2_mul_op__rc__rc_ok 1'0
+    assign \mul_pipe2_mul_op__oe__oe 1'0
+    assign \mul_pipe2_mul_op__oe__oe_ok 1'0
+    assign \mul_pipe2_mul_op__invert_a 1'0
+    assign \mul_pipe2_mul_op__zero_a 1'0
+    assign \mul_pipe2_mul_op__invert_out 1'0
+    assign \mul_pipe2_mul_op__write_cr0 1'0
+    assign \mul_pipe2_mul_op__is_32bit 1'0
+    assign \mul_pipe2_mul_op__is_signed 1'0
+    assign \mul_pipe2_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__invert_out \mul_pipe2_mul_op__zero_a \mul_pipe2_mul_op__invert_a { \mul_pipe2_mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__invert_out \mul_pipe1_mul_op__zero_a \mul_pipe1_mul_op__invert_a { \mul_pipe1_mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type }
     sync init
   end
   process $group_18
@@ -96373,22 +96447,22 @@ module \alu_mul0
     sync init
   end
   process $group_26
-    assign \mul_pipe3_op__insn_type 7'0000000
-    assign \mul_pipe3_op__fn_unit 11'00000000000
-    assign \mul_pipe3_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe3_op__imm_data__imm_ok 1'0
-    assign \mul_pipe3_op__rc__rc 1'0
-    assign \mul_pipe3_op__rc__rc_ok 1'0
-    assign \mul_pipe3_op__oe__oe 1'0
-    assign \mul_pipe3_op__oe__oe_ok 1'0
-    assign \mul_pipe3_op__invert_a 1'0
-    assign \mul_pipe3_op__zero_a 1'0
-    assign \mul_pipe3_op__invert_out 1'0
-    assign \mul_pipe3_op__write_cr0 1'0
-    assign \mul_pipe3_op__is_32bit 1'0
-    assign \mul_pipe3_op__is_signed 1'0
-    assign \mul_pipe3_op__insn 32'00000000000000000000000000000000
-    assign { \mul_pipe3_op__insn \mul_pipe3_op__is_signed \mul_pipe3_op__is_32bit \mul_pipe3_op__write_cr0 \mul_pipe3_op__invert_out \mul_pipe3_op__zero_a \mul_pipe3_op__invert_a { \mul_pipe3_op__oe__oe_ok \mul_pipe3_op__oe__oe } { \mul_pipe3_op__rc__rc_ok \mul_pipe3_op__rc__rc } { \mul_pipe3_op__imm_data__imm_ok \mul_pipe3_op__imm_data__imm } \mul_pipe3_op__fn_unit \mul_pipe3_op__insn_type } { \mul_pipe2_op__insn$36 \mul_pipe2_op__is_signed$35 \mul_pipe2_op__is_32bit$34 \mul_pipe2_op__write_cr0$33 \mul_pipe2_op__invert_out$32 \mul_pipe2_op__zero_a$31 \mul_pipe2_op__invert_a$30 { \mul_pipe2_op__oe__oe_ok$29 \mul_pipe2_op__oe__oe$28 } { \mul_pipe2_op__rc__rc_ok$27 \mul_pipe2_op__rc__rc$26 } { \mul_pipe2_op__imm_data__imm_ok$25 \mul_pipe2_op__imm_data__imm$24 } \mul_pipe2_op__fn_unit$23 \mul_pipe2_op__insn_type$22 }
+    assign \mul_pipe3_mul_op__insn_type 7'0000000
+    assign \mul_pipe3_mul_op__fn_unit 11'00000000000
+    assign \mul_pipe3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe3_mul_op__imm_data__imm_ok 1'0
+    assign \mul_pipe3_mul_op__rc__rc 1'0
+    assign \mul_pipe3_mul_op__rc__rc_ok 1'0
+    assign \mul_pipe3_mul_op__oe__oe 1'0
+    assign \mul_pipe3_mul_op__oe__oe_ok 1'0
+    assign \mul_pipe3_mul_op__invert_a 1'0
+    assign \mul_pipe3_mul_op__zero_a 1'0
+    assign \mul_pipe3_mul_op__invert_out 1'0
+    assign \mul_pipe3_mul_op__write_cr0 1'0
+    assign \mul_pipe3_mul_op__is_32bit 1'0
+    assign \mul_pipe3_mul_op__is_signed 1'0
+    assign \mul_pipe3_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__invert_out \mul_pipe3_mul_op__zero_a \mul_pipe3_mul_op__invert_a { \mul_pipe3_mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$36 \mul_pipe2_mul_op__is_signed$35 \mul_pipe2_mul_op__is_32bit$34 \mul_pipe2_mul_op__write_cr0$33 \mul_pipe2_mul_op__invert_out$32 \mul_pipe2_mul_op__zero_a$31 \mul_pipe2_mul_op__invert_a$30 { \mul_pipe2_mul_op__oe__oe_ok$29 \mul_pipe2_mul_op__oe__oe$28 } { \mul_pipe2_mul_op__rc__rc_ok$27 \mul_pipe2_mul_op__rc__rc$26 } { \mul_pipe2_mul_op__imm_data__imm_ok$25 \mul_pipe2_mul_op__imm_data__imm$24 } \mul_pipe2_mul_op__fn_unit$23 \mul_pipe2_mul_op__insn_type$22 }
     sync init
   end
   process $group_41
@@ -96421,7 +96495,7 @@ module \alu_mul0
     assign \p_ready_o \mul_pipe1_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_47
     assign \mul_pipe1_muxid$2 2'00
@@ -96429,22 +96503,22 @@ module \alu_mul0
     sync init
   end
   process $group_48
-    assign \mul_pipe1_op__insn_type$3 7'0000000
-    assign \mul_pipe1_op__fn_unit$4 11'00000000000
-    assign \mul_pipe1_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe1_op__imm_data__imm_ok$6 1'0
-    assign \mul_pipe1_op__rc__rc$7 1'0
-    assign \mul_pipe1_op__rc__rc_ok$8 1'0
-    assign \mul_pipe1_op__oe__oe$9 1'0
-    assign \mul_pipe1_op__oe__oe_ok$10 1'0
-    assign \mul_pipe1_op__invert_a$11 1'0
-    assign \mul_pipe1_op__zero_a$12 1'0
-    assign \mul_pipe1_op__invert_out$13 1'0
-    assign \mul_pipe1_op__write_cr0$14 1'0
-    assign \mul_pipe1_op__is_32bit$15 1'0
-    assign \mul_pipe1_op__is_signed$16 1'0
-    assign \mul_pipe1_op__insn$17 32'00000000000000000000000000000000
-    assign { \mul_pipe1_op__insn$17 \mul_pipe1_op__is_signed$16 \mul_pipe1_op__is_32bit$15 \mul_pipe1_op__write_cr0$14 \mul_pipe1_op__invert_out$13 \mul_pipe1_op__zero_a$12 \mul_pipe1_op__invert_a$11 { \mul_pipe1_op__oe__oe_ok$10 \mul_pipe1_op__oe__oe$9 } { \mul_pipe1_op__rc__rc_ok$8 \mul_pipe1_op__rc__rc$7 } { \mul_pipe1_op__imm_data__imm_ok$6 \mul_pipe1_op__imm_data__imm$5 } \mul_pipe1_op__fn_unit$4 \mul_pipe1_op__insn_type$3 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \mul_pipe1_mul_op__insn_type$3 7'0000000
+    assign \mul_pipe1_mul_op__fn_unit$4 11'00000000000
+    assign \mul_pipe1_mul_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe1_mul_op__imm_data__imm_ok$6 1'0
+    assign \mul_pipe1_mul_op__rc__rc$7 1'0
+    assign \mul_pipe1_mul_op__rc__rc_ok$8 1'0
+    assign \mul_pipe1_mul_op__oe__oe$9 1'0
+    assign \mul_pipe1_mul_op__oe__oe_ok$10 1'0
+    assign \mul_pipe1_mul_op__invert_a$11 1'0
+    assign \mul_pipe1_mul_op__zero_a$12 1'0
+    assign \mul_pipe1_mul_op__invert_out$13 1'0
+    assign \mul_pipe1_mul_op__write_cr0$14 1'0
+    assign \mul_pipe1_mul_op__is_32bit$15 1'0
+    assign \mul_pipe1_mul_op__is_signed$16 1'0
+    assign \mul_pipe1_mul_op__insn$17 32'00000000000000000000000000000000
+    assign { \mul_pipe1_mul_op__insn$17 \mul_pipe1_mul_op__is_signed$16 \mul_pipe1_mul_op__is_32bit$15 \mul_pipe1_mul_op__write_cr0$14 \mul_pipe1_mul_op__invert_out$13 \mul_pipe1_mul_op__zero_a$12 \mul_pipe1_mul_op__invert_a$11 { \mul_pipe1_mul_op__oe__oe_ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__rc_ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__imm_ok$6 \mul_pipe1_mul_op__imm_data__imm$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
   process $group_63
@@ -96472,7 +96546,7 @@ module \alu_mul0
     assign \mul_pipe3_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$58
   process $group_68
     assign \muxid$58 2'00
@@ -96552,8 +96626,8 @@ module \alu_mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$59
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -96566,51 +96640,51 @@ module \alu_mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_a$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__zero_a$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__invert_out$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__write_cr0$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$73
   process $group_69
-    assign \op__insn_type$59 7'0000000
-    assign \op__fn_unit$60 11'00000000000
-    assign \op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$62 1'0
-    assign \op__rc__rc$63 1'0
-    assign \op__rc__rc_ok$64 1'0
-    assign \op__oe__oe$65 1'0
-    assign \op__oe__oe_ok$66 1'0
-    assign \op__invert_a$67 1'0
-    assign \op__zero_a$68 1'0
-    assign \op__invert_out$69 1'0
-    assign \op__write_cr0$70 1'0
-    assign \op__is_32bit$71 1'0
-    assign \op__is_signed$72 1'0
-    assign \op__insn$73 32'00000000000000000000000000000000
-    assign { \op__insn$73 \op__is_signed$72 \op__is_32bit$71 \op__write_cr0$70 \op__invert_out$69 \op__zero_a$68 \op__invert_a$67 { \op__oe__oe_ok$66 \op__oe__oe$65 } { \op__rc__rc_ok$64 \op__rc__rc$63 } { \op__imm_data__imm_ok$62 \op__imm_data__imm$61 } \op__fn_unit$60 \op__insn_type$59 } { \mul_pipe3_op__insn$55 \mul_pipe3_op__is_signed$54 \mul_pipe3_op__is_32bit$53 \mul_pipe3_op__write_cr0$52 \mul_pipe3_op__invert_out$51 \mul_pipe3_op__zero_a$50 \mul_pipe3_op__invert_a$49 { \mul_pipe3_op__oe__oe_ok$48 \mul_pipe3_op__oe__oe$47 } { \mul_pipe3_op__rc__rc_ok$46 \mul_pipe3_op__rc__rc$45 } { \mul_pipe3_op__imm_data__imm_ok$44 \mul_pipe3_op__imm_data__imm$43 } \mul_pipe3_op__fn_unit$42 \mul_pipe3_op__insn_type$41 }
+    assign \mul_op__insn_type$59 7'0000000
+    assign \mul_op__fn_unit$60 11'00000000000
+    assign \mul_op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$62 1'0
+    assign \mul_op__rc__rc$63 1'0
+    assign \mul_op__rc__rc_ok$64 1'0
+    assign \mul_op__oe__oe$65 1'0
+    assign \mul_op__oe__oe_ok$66 1'0
+    assign \mul_op__invert_a$67 1'0
+    assign \mul_op__zero_a$68 1'0
+    assign \mul_op__invert_out$69 1'0
+    assign \mul_op__write_cr0$70 1'0
+    assign \mul_op__is_32bit$71 1'0
+    assign \mul_op__is_signed$72 1'0
+    assign \mul_op__insn$73 32'00000000000000000000000000000000
+    assign { \mul_op__insn$73 \mul_op__is_signed$72 \mul_op__is_32bit$71 \mul_op__write_cr0$70 \mul_op__invert_out$69 \mul_op__zero_a$68 \mul_op__invert_a$67 { \mul_op__oe__oe_ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__rc_ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__imm_ok$62 \mul_op__imm_data__imm$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \mul_pipe3_mul_op__insn$55 \mul_pipe3_mul_op__is_signed$54 \mul_pipe3_mul_op__is_32bit$53 \mul_pipe3_mul_op__write_cr0$52 \mul_pipe3_mul_op__invert_out$51 \mul_pipe3_mul_op__zero_a$50 \mul_pipe3_mul_op__invert_a$49 { \mul_pipe3_mul_op__oe__oe_ok$48 \mul_pipe3_mul_op__oe__oe$47 } { \mul_pipe3_mul_op__rc__rc_ok$46 \mul_pipe3_mul_op__rc__rc$45 } { \mul_pipe3_mul_op__imm_data__imm_ok$44 \mul_pipe3_mul_op__imm_data__imm$43 } \mul_pipe3_mul_op__fn_unit$42 \mul_pipe3_mul_op__insn_type$41 }
     sync init
   end
   process $group_84
@@ -97734,8 +97808,8 @@ module \mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \oper_i_alu_mul0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -97748,85 +97822,85 @@ module \mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 4 \oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \oper_i__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \oper_i__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \oper_i__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \oper_i__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \oper_i__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \oper_i__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \oper_i__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \oper_i__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \oper_i__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 16 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 17 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \oper_i_alu_mul0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 4 \oper_i_alu_mul0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \oper_i_alu_mul0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \oper_i_alu_mul0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_alu_mul0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_alu_mul0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_alu_mul0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \oper_i_alu_mul0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_alu_mul0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_alu_mul0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_alu_mul0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_alu_mul0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_alu_mul0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \oper_i_alu_mul0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 18 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 input 19 \rdmaskn
+  wire width 1 input 17 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 18 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 19 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 20 \rd__rel
+  wire width 3 output 20 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 21 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 3 input 21 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 22 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 23 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 1 input 24 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 25 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 26 \wr__rel
+  wire width 4 output 26 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 27 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 4 input 27 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 28 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 output 30 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 31 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 32 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 34 \dest4_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 35 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 36 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 35 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 36 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_mul0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_mul0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_mul0_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \alu_mul0_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \alu_mul0_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \alu_mul0_xer_so
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -97901,8 +97975,8 @@ module \mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_mul0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_mul0_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -97915,39 +97989,39 @@ module \mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_mul0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_mul0_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_mul0_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_mul0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_mul0_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_mul0_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_mul0_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_mul0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_mul0_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \alu_mul0_xer_so$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_mul0_p_valid_i
@@ -97966,21 +98040,21 @@ module \mul0
     connect \cr_a \alu_mul0_cr_a
     connect \xer_ov \alu_mul0_xer_ov
     connect \xer_so \alu_mul0_xer_so
-    connect \op__insn_type \alu_mul0_op__insn_type
-    connect \op__fn_unit \alu_mul0_op__fn_unit
-    connect \op__imm_data__imm \alu_mul0_op__imm_data__imm
-    connect \op__imm_data__imm_ok \alu_mul0_op__imm_data__imm_ok
-    connect \op__rc__rc \alu_mul0_op__rc__rc
-    connect \op__rc__rc_ok \alu_mul0_op__rc__rc_ok
-    connect \op__oe__oe \alu_mul0_op__oe__oe
-    connect \op__oe__oe_ok \alu_mul0_op__oe__oe_ok
-    connect \op__invert_a \alu_mul0_op__invert_a
-    connect \op__zero_a \alu_mul0_op__zero_a
-    connect \op__invert_out \alu_mul0_op__invert_out
-    connect \op__write_cr0 \alu_mul0_op__write_cr0
-    connect \op__is_32bit \alu_mul0_op__is_32bit
-    connect \op__is_signed \alu_mul0_op__is_signed
-    connect \op__insn \alu_mul0_op__insn
+    connect \mul_op__insn_type \alu_mul0_mul_op__insn_type
+    connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \alu_mul0_mul_op__invert_a
+    connect \mul_op__zero_a \alu_mul0_mul_op__zero_a
+    connect \mul_op__invert_out \alu_mul0_mul_op__invert_out
+    connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0
+    connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit
+    connect \mul_op__is_signed \alu_mul0_mul_op__is_signed
+    connect \mul_op__insn \alu_mul0_mul_op__insn
     connect \ra \alu_mul0_ra
     connect \rb \alu_mul0_rb
     connect \xer_so$1 \alu_mul0_xer_so$1
@@ -98089,36 +98163,36 @@ module \mul0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $3
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $2
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 3 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 3 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -98126,10 +98200,10 @@ module \mul0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A $5
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -98137,9 +98211,9 @@ module \mul0
     connect \A $7
     connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $11
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98155,9 +98229,9 @@ module \mul0
     assign \all_rd $10
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -98167,11 +98241,11 @@ module \mul0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98179,9 +98253,9 @@ module \mul0
     connect \A \all_rd_dly
     connect \Y $12
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98197,16 +98271,16 @@ module \mul0
     assign \all_rd_pulse $14
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_mul0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -98216,11 +98290,11 @@ module \mul0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98228,9 +98302,9 @@ module \mul0
     connect \A \alu_done_dly
     connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98246,28 +98320,28 @@ module \mul0
     assign \alu_pulse $18
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 4 \alu_pulsem
   process $group_6
     assign \alu_pulsem 4'0000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 4 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 4 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 4 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $20
   end
   process $group_7
@@ -98283,38 +98357,38 @@ module \mul0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 4 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 4 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 4 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 4 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $24
     connect \Y $26
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -98322,7 +98396,7 @@ module \mul0
     connect \A $26
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98330,39 +98404,39 @@ module \mul0
     connect \A $23
     connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $22
     connect \Y $30
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $30
+    assign \cu_done_o 1'0
+    assign \cu_done_o $30
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $32
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -98370,9 +98444,9 @@ module \mul0
     connect \A \prev_wr_go
     connect \Y $34
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98388,11 +98462,11 @@ module \mul0
     assign \wr_any $36
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98400,9 +98474,9 @@ module \mul0
     connect \A \alu_mul0_n_ready_i
     connect \Y $38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98413,9 +98487,9 @@ module \mul0
     connect \B $38
     connect \Y $40
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 4 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -98423,12 +98497,12 @@ module \mul0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -98439,9 +98513,9 @@ module \mul0
     connect \B 1'0
     connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98452,22 +98526,22 @@ module \mul0
     connect \B $44
     connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $48
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98478,9 +98552,9 @@ module \mul0
     connect \B \alu_mul0_n_ready_i
     connect \Y $50
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98491,9 +98565,9 @@ module \mul0
     connect \B \alu_mul0_n_valid_o
     connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98501,25 +98575,25 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $52
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $54
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $46
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $54 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98527,7 +98601,7 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $56
   end
   process $group_11
@@ -98535,19 +98609,19 @@ module \mul0
     assign \reset $56
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $58
   end
   process $group_12
@@ -98555,19 +98629,19 @@ module \mul0
     assign \rst_r $58
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 4 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 4 $60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $60
   end
   process $group_13
@@ -98575,19 +98649,19 @@ module \mul0
     assign \reset_w $60
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 3 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 3 $62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $63
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $62
   end
   process $group_14
@@ -98597,12 +98671,12 @@ module \mul0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -98610,7 +98684,7 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_mul0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $64
   end
   process $group_16
@@ -98638,7 +98712,7 @@ module \mul0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -98664,7 +98738,7 @@ module \mul0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -98688,9 +98762,9 @@ module \mul0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 4 $66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -98698,7 +98772,7 @@ module \mul0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $66
   end
   process $group_23
@@ -98706,9 +98780,9 @@ module \mul0
     assign \req_l_s_req $66
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 4 $68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $69
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -98797,7 +98871,7 @@ module \mul0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -98811,33 +98885,33 @@ module \mul0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -98905,8 +98979,8 @@ module \mul0
   cell $mux $71
     parameter \WIDTH 125
     connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
+    connect \S \cu_issue_i
     connect \Y $70
   end
   process $group_25
@@ -98945,10 +99019,10 @@ module \mul0
     assign \oper_l__is_signed$next \oper_l__is_signed
     assign \oper_l__insn$next \oper_l__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -98993,9 +99067,9 @@ module \mul0
       update \oper_l__is_signed \oper_l__is_signed$next
       update \oper_l__insn \oper_l__insn$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__o_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__o
@@ -99062,9 +99136,9 @@ module \mul0
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 4 \data_r1__cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 4 \data_r1_l__cr_a
@@ -99131,9 +99205,9 @@ module \mul0
       update \data_r1_l__cr_a \data_r1_l__cr_a$next
       update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 2 \data_r2__xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \data_r2_l__xer_ov
@@ -99200,9 +99274,9 @@ module \mul0
       update \data_r2_l__xer_ov \data_r2_l__xer_ov$next
       update \data_r2_l__xer_ov_ok \data_r2_l__xer_ov_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r3__xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r3__xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \data_r3_l__xer_so
@@ -99269,9 +99343,9 @@ module \mul0
       update \data_r3_l__xer_so \data_r3_l__xer_so$next
       update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $97
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99279,12 +99353,12 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__o_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $96
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $99
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99292,12 +99366,12 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__cr_a_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $98
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $101
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99305,12 +99379,12 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__xer_ov_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $100
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $103
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99318,38 +99392,38 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r3__xer_so_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $102
   end
   process $group_71
-    assign \wrmask 4'0000
-    assign \wrmask { $102 $100 $98 $96 }
+    assign \cu_wrmask_o 4'0000
+    assign \cu_wrmask_o { $102 $100 $98 $96 }
     sync init
   end
   process $group_72
-    assign \alu_mul0_op__insn_type 7'0000000
-    assign \alu_mul0_op__fn_unit 11'00000000000
-    assign \alu_mul0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_mul0_op__imm_data__imm_ok 1'0
-    assign \alu_mul0_op__rc__rc 1'0
-    assign \alu_mul0_op__rc__rc_ok 1'0
-    assign \alu_mul0_op__oe__oe 1'0
-    assign \alu_mul0_op__oe__oe_ok 1'0
-    assign \alu_mul0_op__invert_a 1'0
-    assign \alu_mul0_op__zero_a 1'0
-    assign \alu_mul0_op__invert_out 1'0
-    assign \alu_mul0_op__write_cr0 1'0
-    assign \alu_mul0_op__is_32bit 1'0
-    assign \alu_mul0_op__is_signed 1'0
-    assign \alu_mul0_op__insn 32'00000000000000000000000000000000
-    assign { \alu_mul0_op__insn \alu_mul0_op__is_signed \alu_mul0_op__is_32bit \alu_mul0_op__write_cr0 \alu_mul0_op__invert_out \alu_mul0_op__zero_a \alu_mul0_op__invert_a { \alu_mul0_op__oe__oe_ok \alu_mul0_op__oe__oe } { \alu_mul0_op__rc__rc_ok \alu_mul0_op__rc__rc } { \alu_mul0_op__imm_data__imm_ok \alu_mul0_op__imm_data__imm } \alu_mul0_op__fn_unit \alu_mul0_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+    assign \alu_mul0_mul_op__insn_type 7'0000000
+    assign \alu_mul0_mul_op__fn_unit 11'00000000000
+    assign \alu_mul0_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_mul0_mul_op__imm_data__imm_ok 1'0
+    assign \alu_mul0_mul_op__rc__rc 1'0
+    assign \alu_mul0_mul_op__rc__rc_ok 1'0
+    assign \alu_mul0_mul_op__oe__oe 1'0
+    assign \alu_mul0_mul_op__oe__oe_ok 1'0
+    assign \alu_mul0_mul_op__invert_a 1'0
+    assign \alu_mul0_mul_op__zero_a 1'0
+    assign \alu_mul0_mul_op__invert_out 1'0
+    assign \alu_mul0_mul_op__write_cr0 1'0
+    assign \alu_mul0_mul_op__is_32bit 1'0
+    assign \alu_mul0_mul_op__is_signed 1'0
+    assign \alu_mul0_mul_op__insn 32'00000000000000000000000000000000
+    assign { \alu_mul0_mul_op__insn \alu_mul0_mul_op__is_signed \alu_mul0_mul_op__is_32bit \alu_mul0_mul_op__write_cr0 \alu_mul0_mul_op__invert_out \alu_mul0_mul_op__zero_a \alu_mul0_mul_op__invert_a { \alu_mul0_mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe } { \alu_mul0_mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc } { \alu_mul0_mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm } \alu_mul0_mul_op__fn_unit \alu_mul0_mul_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $105
     parameter \WIDTH 1
     connect \A \src_l_q_src [0]
@@ -99362,11 +99436,11 @@ module \mul0
     assign \src_sel $104
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $107
     parameter \WIDTH 64
     connect \A \src1_i
@@ -99379,11 +99453,11 @@ module \mul0
     assign \src_or_imm $106
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel$108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $110
     parameter \WIDTH 1
     connect \A \src_l_q_src [1]
@@ -99396,11 +99470,11 @@ module \mul0
     assign \src_sel$108 $109
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $113
     parameter \WIDTH 64
     connect \A \src2_i
@@ -99514,9 +99588,9 @@ module \mul0
     assign \alu_mul0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99550,9 +99624,9 @@ module \mul0
     assign \alu_mul0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99582,13 +99656,13 @@ module \mul0
     sync init
   end
   process $group_103
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -99596,12 +99670,12 @@ module \mul0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $124
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99609,9 +99683,9 @@ module \mul0
     connect \A \oper_r__zero_a
     connect \Y $126
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99619,9 +99693,9 @@ module \mul0
     connect \A \oper_r__imm_data__imm_ok
     connect \Y $128
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -99632,19 +99706,19 @@ module \mul0
     connect \B { 1'1 $128 $126 }
     connect \Y $130
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $132
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 3 $134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -99656,65 +99730,65 @@ module \mul0
     connect \Y $134
   end
   process $group_104
-    assign \rd__rel 3'000
-    assign \rd__rel $134
+    assign \cu_rd__rel_o 3'000
+    assign \cu_rd__rel_o $134
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $136
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $138
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $138
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $140
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $140
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $142
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 4 $144
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $145
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -99725,9 +99799,9 @@ module \mul0
     connect \B { $136 $138 $140 $142 }
     connect \Y $144
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 4 $146
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -99735,101 +99809,101 @@ module \mul0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A $144
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $146
   end
   process $group_105
-    assign \wr__rel 4'0000
-    assign \wr__rel $146
+    assign \cu_wr__rel_o 4'0000
+    assign \cu_wr__rel_o $146
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $148
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $148
   end
   process $group_106
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $148 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $150
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $150
   end
   process $group_107
     assign \dest2_o 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $150 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $152
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $152
   end
   process $group_108
     assign \dest3_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $152 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__xer_ov_ok \data_r2__xer_ov } [1:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $154
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [3]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [3]
+    connect \B \cu_busy_o
     connect \Y $154
   end
   process $group_109
     assign \dest4_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $154 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0]
     end
@@ -99873,9 +99947,9 @@ module \n$88
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99929,9 +100003,9 @@ module \n$91
   wire width 1 input 1 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
   wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -99951,7 +100025,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input"
 module \input$92
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -100026,8 +100100,8 @@ module \input$92
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -100040,47 +100114,47 @@ module \input$92
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 10 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 16 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 10 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 17 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 18 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 19 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 20 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -100155,8 +100229,8 @@ module \input$92
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 22 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \sr_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -100169,45 +100243,45 @@ module \input$92
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 23 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 24 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \sr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \sr_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \sr_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \sr_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \sr_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \sr_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \sr_op__oe__oe_ok$9
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 31 \op__input_carry$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__output_carry$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__input_cr$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__output_cr$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 37 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 31 \sr_op__input_carry$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \sr_op__output_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \sr_op__input_cr$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \sr_op__output_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \sr_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \sr_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 37 \sr_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 38 \ra$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 39 \rb$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 output 40 \rc$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 output 41 \xer_ca$20
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
   wire width 64 \a
@@ -100224,7 +100298,7 @@ module \input$92
   process $group_2
     assign \xer_ca$20 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
-    switch \op__input_carry
+    switch \sr_op__input_carry
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
       attribute \nmigen.decoding "ZERO/0"
       case 2'00
@@ -100246,23 +100320,23 @@ module \input$92
     sync init
   end
   process $group_4
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
+    assign \sr_op__insn_type$2 7'0000000
+    assign \sr_op__fn_unit$3 11'00000000000
+    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$5 1'0
+    assign \sr_op__rc__rc$6 1'0
+    assign \sr_op__rc__rc_ok$7 1'0
+    assign \sr_op__oe__oe$8 1'0
+    assign \sr_op__oe__oe_ok$9 1'0
     assign { } 0'0
-    assign \op__input_carry$10 2'00
-    assign \op__output_carry$11 1'0
-    assign \op__input_cr$12 1'0
-    assign \op__output_cr$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__output_cr$13 \op__input_cr$12 \op__output_carry$11 \op__input_carry$10 { } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \sr_op__input_carry$10 2'00
+    assign \sr_op__output_carry$11 1'0
+    assign \sr_op__input_cr$12 1'0
+    assign \sr_op__output_cr$13 1'0
+    assign \sr_op__is_32bit$14 1'0
+    assign \sr_op__is_signed$15 1'0
+    assign \sr_op__insn$16 32'00000000000000000000000000000000
+    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
     sync init
   end
   process $group_20
@@ -100320,33 +100394,33 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator"
 module \rotator
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
   wire width 5 input 0 \me
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
   wire width 5 input 1 \mb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
   wire width 1 input 2 \mb_extra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
   wire width 64 input 3 \rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
   wire width 64 input 4 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
   wire width 7 input 5 \shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
   wire width 1 input 6 \is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
   wire width 1 input 7 \arith
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
   wire width 1 input 8 \right_shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
   wire width 1 input 9 \clear_left
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
   wire width 1 input 10 \clear_right
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
   wire width 1 input 11 \sign_ext_rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61"
   wire width 64 output 12 \result_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
   wire width 1 output 13 \carry_out_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
   wire width 64 \rotl_a
@@ -100359,45 +100433,45 @@ module \rotator
     connect \b \rotl_b
     connect \o \rotl_o
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78"
   wire width 32 \hi32
   process $group_0
     assign \hi32 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
     switch { \sign_ext_rs \is_32bit }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
       case 2'-1
         assign \hi32 \rs [31:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:84"
       case 2'1-
         assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:84"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:87"
       case
         assign \hi32 \rs [63:32]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
   wire width 64 \repl32
   process $group_1
     assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \repl32 { \hi32 \rs [31:0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:88"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
   wire width 6 \shift_signed
   process $group_2
     assign \shift_signed 6'000000
     assign \shift_signed \shift [5:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70"
   wire width 6 \rot_count
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
   wire width 7 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
   wire width 7 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
   cell $neg $3
     parameter \A_SIGNED 1
     parameter \A_WIDTH 6
@@ -100408,12 +100482,12 @@ module \rotator
   connect $1 $2
   process $group_3
     assign \rot_count 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:92"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95"
     switch { \right_shift }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:92"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95"
       case 1'1
         assign \rot_count $1 [5:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:97"
       case
         assign \rot_count \shift [5:0]
     end
@@ -100429,18 +100503,18 @@ module \rotator
     assign \rotl_b \rot_count
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:68"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71"
   wire width 64 \rot
   process $group_6
     assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \rot \rotl_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72"
   wire width 7 \sh
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
   wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
   cell $not $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100448,9 +100522,9 @@ module \rotator
     connect \A \is_32bit
     connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
   wire width 1 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
   cell $and $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100466,11 +100540,11 @@ module \rotator
     assign \sh { $6 \shift [5:0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73"
   wire width 7 \mb$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
   wire width 7 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
   cell $pos $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -100478,9 +100552,9 @@ module \rotator
     connect \A \mb
     connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
   cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100490,40 +100564,40 @@ module \rotator
   end
   process $group_8
     assign \mb$8 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113"
     switch { \right_shift \clear_left }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113"
       case 2'-1
         assign \mb$8 $9
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:112"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115"
         switch { \is_32bit }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:112"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115"
           case 1'1
             assign \mb$8 [6:5] 2'01
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:114"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117"
           case
             assign \mb$8 [6:5] { 1'0 \mb_extra }
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
       case 2'1-
         assign \mb$8 \sh
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122"
         switch { \is_32bit }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122"
           case 1'1
             assign \mb$8 [6:5] { \sh [5] $11 }
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:121"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:124"
       case
         assign \mb$8 { 1'0 \is_32bit 5'00000 }
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74"
   wire width 7 \me$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
   wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
   cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100534,9 +100608,9 @@ module \rotator
     connect \B \is_32bit
     connect \Y $14
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
   wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
   cell $not $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100544,9 +100618,9 @@ module \rotator
     connect \A \clear_left
     connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
   wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
   cell $and $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100557,9 +100631,9 @@ module \rotator
     connect \B $16
     connect \Y $18
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136"
   wire width 6 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136"
   cell $not $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -100569,15 +100643,15 @@ module \rotator
   end
   process $group_9
     assign \me$13 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
     switch { $18 $14 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
       case 2'-1
         assign \me$13 { 2'01 \me }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
       case 2'1-
         assign \me$13 { 1'0 \mb_extra \mb }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134"
       case
         assign \me$13 { \sh [6] $20 }
     end
@@ -100650,22 +100724,22 @@ module \rotator
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75"
   wire width 64 \mr
   process $group_11
     assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \mr \right_mask
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:20"
-  wire width 64 \left_mask
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  wire width 64 \left_mask
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   wire width 257 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   wire width 257 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   wire width 8 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   cell $sub $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -100676,9 +100750,9 @@ module \rotator
     connect \B \me$13
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   wire width 256 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   cell $sshl $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100689,9 +100763,9 @@ module \rotator
     connect \B $33
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   wire width 257 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   cell $sub $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 256
@@ -100702,7 +100776,7 @@ module \rotator
     connect \B 1'1
     connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
   cell $not $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 257
@@ -100716,18 +100790,18 @@ module \rotator
     assign \left_mask $31 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76"
   wire width 64 \ml
   process $group_13
     assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \ml \left_mask
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77"
   wire width 2 \output_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
   cell $not $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100735,9 +100809,9 @@ module \rotator
     connect \A \clear_right
     connect \Y $40
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
   wire width 1 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
   cell $and $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100748,9 +100822,9 @@ module \rotator
     connect \B $40
     connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
   wire width 1 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
   cell $or $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100761,9 +100835,9 @@ module \rotator
     connect \B \right_shift
     connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148"
   wire width 1 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148"
   cell $and $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100774,9 +100848,9 @@ module \rotator
     connect \B \repl32 [63]
     connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
   wire width 1 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
   cell $gt $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -100787,9 +100861,9 @@ module \rotator
     connect \B \me$13 [5:0]
     connect \Y $48
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
   wire width 1 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
   cell $and $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -100802,20 +100876,20 @@ module \rotator
   end
   process $group_14
     assign \output_mode 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
     switch { $44 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
       case 1'1
         assign \output_mode { 1'1 $46 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:146"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149"
       case
         assign \output_mode { 1'0 $50 }
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   wire width 64 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   cell $and $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100826,9 +100900,9 @@ module \rotator
     connect \B \ml
     connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   wire width 64 $54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   cell $and $55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100839,11 +100913,11 @@ module \rotator
     connect \B $52
     connect \Y $54
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   wire width 64 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   wire width 64 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   cell $and $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100854,7 +100928,7 @@ module \rotator
     connect \B \ml
     connect \Y $57
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   cell $not $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100862,9 +100936,9 @@ module \rotator
     connect \A $57
     connect \Y $56
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   wire width 64 $60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   cell $and $61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100875,9 +100949,9 @@ module \rotator
     connect \B $56
     connect \Y $60
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   wire width 64 $62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
   cell $or $63
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100888,9 +100962,9 @@ module \rotator
     connect \B $60
     connect \Y $62
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   wire width 64 $64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   cell $or $65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100901,9 +100975,9 @@ module \rotator
     connect \B \ml
     connect \Y $64
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   wire width 64 $66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   cell $and $67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100914,11 +100988,11 @@ module \rotator
     connect \B $64
     connect \Y $66
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   wire width 64 $68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   wire width 64 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   cell $or $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100929,7 +101003,7 @@ module \rotator
     connect \B \ml
     connect \Y $69
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   cell $not $71
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100937,9 +101011,9 @@ module \rotator
     connect \A $69
     connect \Y $68
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   wire width 64 $72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   cell $and $73
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100950,9 +101024,9 @@ module \rotator
     connect \B $68
     connect \Y $72
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   wire width 64 $74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
   cell $or $75
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100963,9 +101037,9 @@ module \rotator
     connect \B $72
     connect \Y $74
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160"
   wire width 64 $76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160"
   cell $and $77
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100976,9 +101050,9 @@ module \rotator
     connect \B \mr
     connect \Y $76
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
   wire width 64 $78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
   cell $not $79
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -100986,9 +101060,9 @@ module \rotator
     connect \A \mr
     connect \Y $78
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
   wire width 64 $80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
   cell $or $81
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -101001,28 +101075,28 @@ module \rotator
   end
   process $group_15
     assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
     switch \output_mode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
       case 2'00
         assign \result_o $62
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
       case 2'01
         assign \result_o $74
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
       case 2'10
         assign \result_o $76
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
       case 2'11
         assign \result_o $80
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
   wire width 1 $82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
   wire width 64 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
   cell $not $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -101030,9 +101104,9 @@ module \rotator
     connect \A \ml
     connect \Y $83
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
   wire width 64 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
   cell $and $86
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -101043,7 +101117,7 @@ module \rotator
     connect \B $83
     connect \Y $85
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
   cell $reduce_bool $87
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -101053,15 +101127,15 @@ module \rotator
   end
   process $group_16
     assign \carry_out_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
     switch \output_mode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
       case 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
       case 2'11
         assign \carry_out_o $82
     end
@@ -101071,7 +101145,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main"
 module \main$93
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -101146,8 +101220,8 @@ module \main$93
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101160,45 +101234,45 @@ module \main$93
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 10 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 16 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 10 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 17 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 18 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 19 \rc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 20 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -101273,8 +101347,8 @@ module \main$93
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 21 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 21 \sr_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101287,71 +101361,71 @@ module \main$93
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 22 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 23 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 24 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 22 \sr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 23 \sr_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 24 \sr_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \sr_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \sr_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \sr_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \sr_op__oe__oe_ok$9
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 30 \op__input_carry$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__output_carry$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__input_cr$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__output_cr$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 36 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 30 \sr_op__input_carry$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \sr_op__output_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \sr_op__input_cr$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \sr_op__output_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \sr_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \sr_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 36 \sr_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 37 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 38 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 39 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
   wire width 5 \rotator_me
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
   wire width 5 \rotator_mb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
   wire width 1 \rotator_mb_extra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
   wire width 64 \rotator_rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
   wire width 64 \rotator_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
   wire width 7 \rotator_shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
   wire width 1 \rotator_is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
   wire width 1 \rotator_arith
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
   wire width 1 \rotator_right_shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
   wire width 1 \rotator_clear_left
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
   wire width 1 \rotator_clear_right
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
   wire width 1 \rotator_sign_ext_rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61"
   wire width 64 \rotator_result_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
   wire width 1 \rotator_carry_out_o
   cell \rotator \rotator
     connect \me \rotator_me
@@ -101373,21 +101447,21 @@ module \main$93
   wire width 5 \mb
   process $group_0
     assign \mb 5'00000
-    assign \mb { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] }
+    assign \mb { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:43"
   wire width 5 \me
   process $group_1
     assign \me 5'00000
-    assign \me { \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] }
+    assign \me { \sr_op__insn [5] \sr_op__insn [4] \sr_op__insn [3] \sr_op__insn [2] \sr_op__insn [1] }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:44"
   wire width 1 \mb_extra
   process $group_2
     assign \mb_extra 1'0
-    assign \mb_extra { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] } [0]
+    assign \mb_extra { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] \sr_op__insn [5] } [0]
     sync init
   end
   process $group_3
@@ -101422,19 +101496,19 @@ module \main$93
   end
   process $group_9
     assign \rotator_is_32bit 1'0
-    assign \rotator_is_32bit \op__is_32bit
+    assign \rotator_is_32bit \sr_op__is_32bit
     sync init
   end
   process $group_10
     assign \rotator_arith 1'0
-    assign \rotator_arith \op__is_signed
+    assign \rotator_arith \sr_op__is_signed
     sync init
   end
   process $group_11
     assign \o_ok 1'0
     assign \o_ok 1'1
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
-    switch \op__insn_type
+    switch \sr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
       attribute \nmigen.decoding "OP_SHL/60"
       case 7'0111100
@@ -101465,7 +101539,7 @@ module \main$93
   process $group_12
     assign \mode 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
-    switch \op__insn_type
+    switch \sr_op__insn_type
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
       attribute \nmigen.decoding "OP_SHL/60"
       case 7'0111100
@@ -101520,30 +101594,30 @@ module \main$93
     sync init
   end
   process $group_20
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
+    assign \sr_op__insn_type$2 7'0000000
+    assign \sr_op__fn_unit$3 11'00000000000
+    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$5 1'0
+    assign \sr_op__rc__rc$6 1'0
+    assign \sr_op__rc__rc_ok$7 1'0
+    assign \sr_op__oe__oe$8 1'0
+    assign \sr_op__oe__oe_ok$9 1'0
     assign { } 0'0
-    assign \op__input_carry$10 2'00
-    assign \op__output_carry$11 1'0
-    assign \op__input_cr$12 1'0
-    assign \op__output_cr$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__output_cr$13 \op__input_cr$12 \op__output_carry$11 \op__input_carry$10 { } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \sr_op__input_carry$10 2'00
+    assign \sr_op__output_carry$11 1'0
+    assign \sr_op__input_cr$12 1'0
+    assign \sr_op__output_cr$13 1'0
+    assign \sr_op__is_32bit$14 1'0
+    assign \sr_op__is_signed$15 1'0
+    assign \sr_op__insn$16 32'00000000000000000000000000000000
+    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
     sync init
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output"
 module \output$94
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -101618,8 +101692,8 @@ module \output$94
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 1 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101632,47 +101706,47 @@ module \output$94
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 2 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 3 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 4 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 10 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 16 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 10 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 17 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 18 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 input 19 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 input 20 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -101747,8 +101821,8 @@ module \output$94
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 22 \op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \sr_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101761,55 +101835,55 @@ module \output$94
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 23 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 24 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 25 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 26 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 27 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 28 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 29 \op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \sr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \sr_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \sr_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \sr_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \sr_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \sr_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \sr_op__oe__oe_ok$9
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 31 \op__input_carry$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__output_carry$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__input_cr$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__output_cr$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 37 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 31 \sr_op__input_carry$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \sr_op__output_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \sr_op__input_cr$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \sr_op__output_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \sr_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \sr_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 37 \sr_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 38 \o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 39 \o_ok$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 40 \cr_a$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 41 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 42 \xer_ca$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 43 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
   wire width 65 \o$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 65 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   cell $pos $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -101836,7 +101910,7 @@ module \output$94
   end
   process $group_3
     assign \xer_ca_ok 1'0
-    assign \xer_ca_ok \op__output_carry
+    assign \xer_ca_ok \sr_op__output_carry
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
@@ -101850,7 +101924,7 @@ module \output$94
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \sr_op__insn_type
     connect \B 7'0001010
     connect \Y $24
   end
@@ -101870,7 +101944,7 @@ module \output$94
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \op__insn_type
+    connect \A \sr_op__insn_type
     connect \B 7'0001100
     connect \Y $26
   end
@@ -102019,9 +102093,9 @@ module \output$94
     assign \cr_a$19 \cr0
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   cell $pos $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 0
@@ -102040,23 +102114,23 @@ module \output$94
     sync init
   end
   process $group_16
-    assign \op__insn_type$2 7'0000000
-    assign \op__fn_unit$3 11'00000000000
-    assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$5 1'0
-    assign \op__rc__rc$6 1'0
-    assign \op__rc__rc_ok$7 1'0
-    assign \op__oe__oe$8 1'0
-    assign \op__oe__oe_ok$9 1'0
+    assign \sr_op__insn_type$2 7'0000000
+    assign \sr_op__fn_unit$3 11'00000000000
+    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$5 1'0
+    assign \sr_op__rc__rc$6 1'0
+    assign \sr_op__rc__rc_ok$7 1'0
+    assign \sr_op__oe__oe$8 1'0
+    assign \sr_op__oe__oe_ok$9 1'0
     assign { } 0'0
-    assign \op__input_carry$10 2'00
-    assign \op__output_carry$11 1'0
-    assign \op__input_cr$12 1'0
-    assign \op__output_cr$13 1'0
-    assign \op__is_32bit$14 1'0
-    assign \op__is_signed$15 1'0
-    assign \op__insn$16 32'00000000000000000000000000000000
-    assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__output_cr$13 \op__input_cr$12 \op__output_carry$11 \op__input_carry$10 { } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \sr_op__input_carry$10 2'00
+    assign \sr_op__output_carry$11 1'0
+    assign \sr_op__input_cr$12 1'0
+    assign \sr_op__output_cr$13 1'0
+    assign \sr_op__is_32bit$14 1'0
+    assign \sr_op__is_signed$15 1'0
+    assign \sr_op__insn$16 32'00000000000000000000000000000000
+    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
     sync init
   end
 end
@@ -102071,7 +102145,7 @@ module \pipe$89
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -102146,8 +102220,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 5 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102160,53 +102234,53 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 6 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 7 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 14 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 20 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 14 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 20 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 21 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 22 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 23 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 24 \xer_ca
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 25 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 26 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 output 27 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -102281,10 +102355,10 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 28 \op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$2$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 28 \sr_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \sr_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102297,89 +102371,89 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 29 \op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 30 \op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 31 \op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 32 \op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 34 \op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 29 \sr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \sr_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 30 \sr_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \sr_op__imm_data__imm$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \sr_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__imm_data__imm_ok$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \sr_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \sr_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \sr_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \sr_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe_ok$9$next
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 37 \op__input_carry$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 38 \op__output_carry$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \op__input_cr$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__input_cr$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 40 \op__output_cr$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_cr$13$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 41 \op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 42 \op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 43 \op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 37 \sr_op__input_carry$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \sr_op__input_carry$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \sr_op__output_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_carry$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \sr_op__input_cr$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__input_cr$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \sr_op__output_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_cr$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 41 \sr_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_32bit$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 42 \sr_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_signed$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 43 \sr_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \sr_op__insn$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 44 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 45 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 46 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 47 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 48 \xer_ca$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 49 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$next
   cell \p$90 \p
     connect \p_valid_i \p_valid_i
@@ -102389,7 +102463,7 @@ module \pipe$89
     connect \n_valid_o \n_valid_o
     connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -102464,8 +102538,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102478,47 +102552,47 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \input_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \input_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \input_muxid$18
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -102593,8 +102667,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \input_op__insn_type$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_sr_op__insn_type$19
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102607,89 +102681,89 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \input_op__fn_unit$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \input_op__imm_data__imm$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__imm_data__imm_ok$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__rc__rc_ok$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__oe__oe_ok$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_sr_op__fn_unit$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_sr_op__imm_data__imm$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__imm_data__imm_ok$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc_ok$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe_ok$26
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \input_op__input_carry$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_carry$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__input_cr$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__output_cr$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_32bit$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \input_op__is_signed$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \input_op__insn$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_sr_op__input_carry$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_carry$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__input_cr$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_cr$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_32bit$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_signed$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_sr_op__insn$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rb$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_rc$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \input_xer_ca$37
   cell \input$92 \input
     connect \muxid \input_muxid
-    connect \op__insn_type \input_op__insn_type
-    connect \op__fn_unit \input_op__fn_unit
-    connect \op__imm_data__imm \input_op__imm_data__imm
-    connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
-    connect \op__rc__rc \input_op__rc__rc
-    connect \op__rc__rc_ok \input_op__rc__rc_ok
-    connect \op__oe__oe \input_op__oe__oe
-    connect \op__oe__oe_ok \input_op__oe__oe_ok
-    connect \op__input_carry \input_op__input_carry
-    connect \op__output_carry \input_op__output_carry
-    connect \op__input_cr \input_op__input_cr
-    connect \op__output_cr \input_op__output_cr
-    connect \op__is_32bit \input_op__is_32bit
-    connect \op__is_signed \input_op__is_signed
-    connect \op__insn \input_op__insn
+    connect \sr_op__insn_type \input_sr_op__insn_type
+    connect \sr_op__fn_unit \input_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \input_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \input_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \input_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \input_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \input_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \input_sr_op__input_carry
+    connect \sr_op__output_carry \input_sr_op__output_carry
+    connect \sr_op__input_cr \input_sr_op__input_cr
+    connect \sr_op__output_cr \input_sr_op__output_cr
+    connect \sr_op__is_32bit \input_sr_op__is_32bit
+    connect \sr_op__is_signed \input_sr_op__is_signed
+    connect \sr_op__insn \input_sr_op__insn
     connect \ra \input_ra
     connect \rb \input_rb
     connect \rc \input_rc
     connect \xer_ca \input_xer_ca
     connect \muxid$1 \input_muxid$18
-    connect \op__insn_type$2 \input_op__insn_type$19
-    connect \op__fn_unit$3 \input_op__fn_unit$20
-    connect \op__imm_data__imm$4 \input_op__imm_data__imm$21
-    connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$22
-    connect \op__rc__rc$6 \input_op__rc__rc$23
-    connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$24
-    connect \op__oe__oe$8 \input_op__oe__oe$25
-    connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$26
-    connect \op__input_carry$10 \input_op__input_carry$27
-    connect \op__output_carry$11 \input_op__output_carry$28
-    connect \op__input_cr$12 \input_op__input_cr$29
-    connect \op__output_cr$13 \input_op__output_cr$30
-    connect \op__is_32bit$14 \input_op__is_32bit$31
-    connect \op__is_signed$15 \input_op__is_signed$32
-    connect \op__insn$16 \input_op__insn$33
+    connect \sr_op__insn_type$2 \input_sr_op__insn_type$19
+    connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$20
+    connect \sr_op__imm_data__imm$4 \input_sr_op__imm_data__imm$21
+    connect \sr_op__imm_data__imm_ok$5 \input_sr_op__imm_data__imm_ok$22
+    connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$23
+    connect \sr_op__rc__rc_ok$7 \input_sr_op__rc__rc_ok$24
+    connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$25
+    connect \sr_op__oe__oe_ok$9 \input_sr_op__oe__oe_ok$26
+    connect \sr_op__input_carry$10 \input_sr_op__input_carry$27
+    connect \sr_op__output_carry$11 \input_sr_op__output_carry$28
+    connect \sr_op__input_cr$12 \input_sr_op__input_cr$29
+    connect \sr_op__output_cr$13 \input_sr_op__output_cr$30
+    connect \sr_op__is_32bit$14 \input_sr_op__is_32bit$31
+    connect \sr_op__is_signed$15 \input_sr_op__is_signed$32
+    connect \sr_op__insn$16 \input_sr_op__insn$33
     connect \ra$17 \input_ra$34
     connect \rb$18 \input_rb$35
     connect \rc$19 \input_rc$36
     connect \xer_ca$20 \input_xer_ca$37
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -102764,8 +102838,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102778,45 +102852,45 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \main_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \main_rc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \main_muxid$38
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -102891,8 +102965,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \main_op__insn_type$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_sr_op__insn_type$39
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102905,85 +102979,85 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \main_op__fn_unit$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \main_op__imm_data__imm$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__imm_data__imm_ok$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__rc__rc_ok$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__oe__oe_ok$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_sr_op__fn_unit$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_sr_op__imm_data__imm$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__imm_data__imm_ok$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc_ok$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe_ok$46
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \main_op__input_carry$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_carry$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__input_cr$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__output_cr$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_32bit$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \main_op__is_signed$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \main_op__insn$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_sr_op__input_carry$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_carry$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__input_cr$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_cr$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_32bit$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_signed$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_sr_op__insn$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \main_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \main_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \main_xer_ca
   cell \main$93 \main
     connect \muxid \main_muxid
-    connect \op__insn_type \main_op__insn_type
-    connect \op__fn_unit \main_op__fn_unit
-    connect \op__imm_data__imm \main_op__imm_data__imm
-    connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
-    connect \op__rc__rc \main_op__rc__rc
-    connect \op__rc__rc_ok \main_op__rc__rc_ok
-    connect \op__oe__oe \main_op__oe__oe
-    connect \op__oe__oe_ok \main_op__oe__oe_ok
-    connect \op__input_carry \main_op__input_carry
-    connect \op__output_carry \main_op__output_carry
-    connect \op__input_cr \main_op__input_cr
-    connect \op__output_cr \main_op__output_cr
-    connect \op__is_32bit \main_op__is_32bit
-    connect \op__is_signed \main_op__is_signed
-    connect \op__insn \main_op__insn
+    connect \sr_op__insn_type \main_sr_op__insn_type
+    connect \sr_op__fn_unit \main_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \main_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \main_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \main_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \main_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \main_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \main_sr_op__input_carry
+    connect \sr_op__output_carry \main_sr_op__output_carry
+    connect \sr_op__input_cr \main_sr_op__input_cr
+    connect \sr_op__output_cr \main_sr_op__output_cr
+    connect \sr_op__is_32bit \main_sr_op__is_32bit
+    connect \sr_op__is_signed \main_sr_op__is_signed
+    connect \sr_op__insn \main_sr_op__insn
     connect \ra \main_ra
     connect \rb \main_rb
     connect \rc \main_rc
     connect \muxid$1 \main_muxid$38
-    connect \op__insn_type$2 \main_op__insn_type$39
-    connect \op__fn_unit$3 \main_op__fn_unit$40
-    connect \op__imm_data__imm$4 \main_op__imm_data__imm$41
-    connect \op__imm_data__imm_ok$5 \main_op__imm_data__imm_ok$42
-    connect \op__rc__rc$6 \main_op__rc__rc$43
-    connect \op__rc__rc_ok$7 \main_op__rc__rc_ok$44
-    connect \op__oe__oe$8 \main_op__oe__oe$45
-    connect \op__oe__oe_ok$9 \main_op__oe__oe_ok$46
-    connect \op__input_carry$10 \main_op__input_carry$47
-    connect \op__output_carry$11 \main_op__output_carry$48
-    connect \op__input_cr$12 \main_op__input_cr$49
-    connect \op__output_cr$13 \main_op__output_cr$50
-    connect \op__is_32bit$14 \main_op__is_32bit$51
-    connect \op__is_signed$15 \main_op__is_signed$52
-    connect \op__insn$16 \main_op__insn$53
+    connect \sr_op__insn_type$2 \main_sr_op__insn_type$39
+    connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$40
+    connect \sr_op__imm_data__imm$4 \main_sr_op__imm_data__imm$41
+    connect \sr_op__imm_data__imm_ok$5 \main_sr_op__imm_data__imm_ok$42
+    connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$43
+    connect \sr_op__rc__rc_ok$7 \main_sr_op__rc__rc_ok$44
+    connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$45
+    connect \sr_op__oe__oe_ok$9 \main_sr_op__oe__oe_ok$46
+    connect \sr_op__input_carry$10 \main_sr_op__input_carry$47
+    connect \sr_op__output_carry$11 \main_sr_op__output_carry$48
+    connect \sr_op__input_cr$12 \main_sr_op__input_cr$49
+    connect \sr_op__output_cr$13 \main_sr_op__output_cr$50
+    connect \sr_op__is_32bit$14 \main_sr_op__is_32bit$51
+    connect \sr_op__is_signed$15 \main_sr_op__is_signed$52
+    connect \sr_op__insn$16 \main_sr_op__insn$53
     connect \o \main_o
     connect \o_ok \main_o_ok
     connect \xer_ca \main_xer_ca
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -103058,8 +103132,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103072,47 +103146,47 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \output_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \output_muxid$54
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -103187,8 +103261,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \output_op__insn_type$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_sr_op__insn_type$55
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103201,87 +103275,87 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \output_op__fn_unit$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \output_op__imm_data__imm$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__imm_data__imm_ok$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__rc__rc_ok$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__oe__oe_ok$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_sr_op__fn_unit$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_sr_op__imm_data__imm$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__imm_data__imm_ok$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc_ok$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe_ok$62
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \output_op__input_carry$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_carry$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__input_cr$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__output_cr$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_32bit$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \output_op__is_signed$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \output_op__insn$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_sr_op__input_carry$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_carry$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__input_cr$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_cr$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_32bit$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_signed$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_sr_op__insn$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \output_o$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_o_ok$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \output_cr_a$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \output_xer_ca$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \output_xer_ca_ok
   cell \output$94 \output
     connect \muxid \output_muxid
-    connect \op__insn_type \output_op__insn_type
-    connect \op__fn_unit \output_op__fn_unit
-    connect \op__imm_data__imm \output_op__imm_data__imm
-    connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
-    connect \op__rc__rc \output_op__rc__rc
-    connect \op__rc__rc_ok \output_op__rc__rc_ok
-    connect \op__oe__oe \output_op__oe__oe
-    connect \op__oe__oe_ok \output_op__oe__oe_ok
-    connect \op__input_carry \output_op__input_carry
-    connect \op__output_carry \output_op__output_carry
-    connect \op__input_cr \output_op__input_cr
-    connect \op__output_cr \output_op__output_cr
-    connect \op__is_32bit \output_op__is_32bit
-    connect \op__is_signed \output_op__is_signed
-    connect \op__insn \output_op__insn
+    connect \sr_op__insn_type \output_sr_op__insn_type
+    connect \sr_op__fn_unit \output_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \output_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \output_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \output_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \output_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \output_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \output_sr_op__input_carry
+    connect \sr_op__output_carry \output_sr_op__output_carry
+    connect \sr_op__input_cr \output_sr_op__input_cr
+    connect \sr_op__output_cr \output_sr_op__output_cr
+    connect \sr_op__is_32bit \output_sr_op__is_32bit
+    connect \sr_op__is_signed \output_sr_op__is_signed
+    connect \sr_op__insn \output_sr_op__insn
     connect \o \output_o
     connect \o_ok \output_o_ok
     connect \cr_a \output_cr_a
     connect \xer_ca \output_xer_ca
     connect \muxid$1 \output_muxid$54
-    connect \op__insn_type$2 \output_op__insn_type$55
-    connect \op__fn_unit$3 \output_op__fn_unit$56
-    connect \op__imm_data__imm$4 \output_op__imm_data__imm$57
-    connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$58
-    connect \op__rc__rc$6 \output_op__rc__rc$59
-    connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$60
-    connect \op__oe__oe$8 \output_op__oe__oe$61
-    connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$62
-    connect \op__input_carry$10 \output_op__input_carry$63
-    connect \op__output_carry$11 \output_op__output_carry$64
-    connect \op__input_cr$12 \output_op__input_cr$65
-    connect \op__output_cr$13 \output_op__output_cr$66
-    connect \op__is_32bit$14 \output_op__is_32bit$67
-    connect \op__is_signed$15 \output_op__is_signed$68
-    connect \op__insn$16 \output_op__insn$69
+    connect \sr_op__insn_type$2 \output_sr_op__insn_type$55
+    connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$56
+    connect \sr_op__imm_data__imm$4 \output_sr_op__imm_data__imm$57
+    connect \sr_op__imm_data__imm_ok$5 \output_sr_op__imm_data__imm_ok$58
+    connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$59
+    connect \sr_op__rc__rc_ok$7 \output_sr_op__rc__rc_ok$60
+    connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$61
+    connect \sr_op__oe__oe_ok$9 \output_sr_op__oe__oe_ok$62
+    connect \sr_op__input_carry$10 \output_sr_op__input_carry$63
+    connect \sr_op__output_carry$11 \output_sr_op__output_carry$64
+    connect \sr_op__input_cr$12 \output_sr_op__input_cr$65
+    connect \sr_op__output_cr$13 \output_sr_op__output_cr$66
+    connect \sr_op__is_32bit$14 \output_sr_op__is_32bit$67
+    connect \sr_op__is_signed$15 \output_sr_op__is_signed$68
+    connect \sr_op__insn$16 \output_sr_op__insn$69
     connect \o$17 \output_o$70
     connect \o_ok$18 \output_o_ok$71
     connect \cr_a$19 \output_cr_a$72
@@ -103295,23 +103369,23 @@ module \pipe$89
     sync init
   end
   process $group_1
-    assign \input_op__insn_type 7'0000000
-    assign \input_op__fn_unit 11'00000000000
-    assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_op__imm_data__imm_ok 1'0
-    assign \input_op__rc__rc 1'0
-    assign \input_op__rc__rc_ok 1'0
-    assign \input_op__oe__oe 1'0
-    assign \input_op__oe__oe_ok 1'0
+    assign \input_sr_op__insn_type 7'0000000
+    assign \input_sr_op__fn_unit 11'00000000000
+    assign \input_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_sr_op__imm_data__imm_ok 1'0
+    assign \input_sr_op__rc__rc 1'0
+    assign \input_sr_op__rc__rc_ok 1'0
+    assign \input_sr_op__oe__oe 1'0
+    assign \input_sr_op__oe__oe_ok 1'0
     assign { } 0'0
-    assign \input_op__input_carry 2'00
-    assign \input_op__output_carry 1'0
-    assign \input_op__input_cr 1'0
-    assign \input_op__output_cr 1'0
-    assign \input_op__is_32bit 1'0
-    assign \input_op__is_signed 1'0
-    assign \input_op__insn 32'00000000000000000000000000000000
-    assign { \input_op__insn \input_op__is_signed \input_op__is_32bit \input_op__output_cr \input_op__input_cr \input_op__output_carry \input_op__input_carry { } { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \input_sr_op__input_carry 2'00
+    assign \input_sr_op__output_carry 1'0
+    assign \input_sr_op__input_cr 1'0
+    assign \input_sr_op__output_cr 1'0
+    assign \input_sr_op__is_32bit 1'0
+    assign \input_sr_op__is_signed 1'0
+    assign \input_sr_op__insn 32'00000000000000000000000000000000
+    assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry { } { \input_sr_op__oe__oe_ok \input_sr_op__oe__oe } { \input_sr_op__rc__rc_ok \input_sr_op__rc__rc } { \input_sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm } \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
     sync init
   end
   process $group_17
@@ -103340,23 +103414,23 @@ module \pipe$89
     sync init
   end
   process $group_22
-    assign \main_op__insn_type 7'0000000
-    assign \main_op__fn_unit 11'00000000000
-    assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_op__imm_data__imm_ok 1'0
-    assign \main_op__rc__rc 1'0
-    assign \main_op__rc__rc_ok 1'0
-    assign \main_op__oe__oe 1'0
-    assign \main_op__oe__oe_ok 1'0
+    assign \main_sr_op__insn_type 7'0000000
+    assign \main_sr_op__fn_unit 11'00000000000
+    assign \main_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_sr_op__imm_data__imm_ok 1'0
+    assign \main_sr_op__rc__rc 1'0
+    assign \main_sr_op__rc__rc_ok 1'0
+    assign \main_sr_op__oe__oe 1'0
+    assign \main_sr_op__oe__oe_ok 1'0
     assign { } 0'0
-    assign \main_op__input_carry 2'00
-    assign \main_op__output_carry 1'0
-    assign \main_op__input_cr 1'0
-    assign \main_op__output_cr 1'0
-    assign \main_op__is_32bit 1'0
-    assign \main_op__is_signed 1'0
-    assign \main_op__insn 32'00000000000000000000000000000000
-    assign { \main_op__insn \main_op__is_signed \main_op__is_32bit \main_op__output_cr \main_op__input_cr \main_op__output_carry \main_op__input_carry { } { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$33 \input_op__is_signed$32 \input_op__is_32bit$31 \input_op__output_cr$30 \input_op__input_cr$29 \input_op__output_carry$28 \input_op__input_carry$27 { } { \input_op__oe__oe_ok$26 \input_op__oe__oe$25 } { \input_op__rc__rc_ok$24 \input_op__rc__rc$23 } { \input_op__imm_data__imm_ok$22 \input_op__imm_data__imm$21 } \input_op__fn_unit$20 \input_op__insn_type$19 }
+    assign \main_sr_op__input_carry 2'00
+    assign \main_sr_op__output_carry 1'0
+    assign \main_sr_op__input_cr 1'0
+    assign \main_sr_op__output_cr 1'0
+    assign \main_sr_op__is_32bit 1'0
+    assign \main_sr_op__is_signed 1'0
+    assign \main_sr_op__insn 32'00000000000000000000000000000000
+    assign { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry { } { \main_sr_op__oe__oe_ok \main_sr_op__oe__oe } { \main_sr_op__rc__rc_ok \main_sr_op__rc__rc } { \main_sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm } \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$33 \input_sr_op__is_signed$32 \input_sr_op__is_32bit$31 \input_sr_op__output_cr$30 \input_sr_op__input_cr$29 \input_sr_op__output_carry$28 \input_sr_op__input_carry$27 { } { \input_sr_op__oe__oe_ok$26 \input_sr_op__oe__oe$25 } { \input_sr_op__rc__rc_ok$24 \input_sr_op__rc__rc$23 } { \input_sr_op__imm_data__imm_ok$22 \input_sr_op__imm_data__imm$21 } \input_sr_op__fn_unit$20 \input_sr_op__insn_type$19 }
     sync init
   end
   process $group_38
@@ -103374,7 +103448,7 @@ module \pipe$89
     assign \main_rc \input_rc$36
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \xer_ca$74
   process $group_41
     assign \xer_ca$74 2'00
@@ -103387,23 +103461,23 @@ module \pipe$89
     sync init
   end
   process $group_43
-    assign \output_op__insn_type 7'0000000
-    assign \output_op__fn_unit 11'00000000000
-    assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_op__imm_data__imm_ok 1'0
-    assign \output_op__rc__rc 1'0
-    assign \output_op__rc__rc_ok 1'0
-    assign \output_op__oe__oe 1'0
-    assign \output_op__oe__oe_ok 1'0
+    assign \output_sr_op__insn_type 7'0000000
+    assign \output_sr_op__fn_unit 11'00000000000
+    assign \output_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_sr_op__imm_data__imm_ok 1'0
+    assign \output_sr_op__rc__rc 1'0
+    assign \output_sr_op__rc__rc_ok 1'0
+    assign \output_sr_op__oe__oe 1'0
+    assign \output_sr_op__oe__oe_ok 1'0
     assign { } 0'0
-    assign \output_op__input_carry 2'00
-    assign \output_op__output_carry 1'0
-    assign \output_op__input_cr 1'0
-    assign \output_op__output_cr 1'0
-    assign \output_op__is_32bit 1'0
-    assign \output_op__is_signed 1'0
-    assign \output_op__insn 32'00000000000000000000000000000000
-    assign { \output_op__insn \output_op__is_signed \output_op__is_32bit \output_op__output_cr \output_op__input_cr \output_op__output_carry \output_op__input_carry { } { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$53 \main_op__is_signed$52 \main_op__is_32bit$51 \main_op__output_cr$50 \main_op__input_cr$49 \main_op__output_carry$48 \main_op__input_carry$47 { } { \main_op__oe__oe_ok$46 \main_op__oe__oe$45 } { \main_op__rc__rc_ok$44 \main_op__rc__rc$43 } { \main_op__imm_data__imm_ok$42 \main_op__imm_data__imm$41 } \main_op__fn_unit$40 \main_op__insn_type$39 }
+    assign \output_sr_op__input_carry 2'00
+    assign \output_sr_op__output_carry 1'0
+    assign \output_sr_op__input_cr 1'0
+    assign \output_sr_op__output_cr 1'0
+    assign \output_sr_op__is_32bit 1'0
+    assign \output_sr_op__is_signed 1'0
+    assign \output_sr_op__insn 32'00000000000000000000000000000000
+    assign { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry { } { \output_sr_op__oe__oe_ok \output_sr_op__oe__oe } { \output_sr_op__rc__rc_ok \output_sr_op__rc__rc } { \output_sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm } \output_sr_op__fn_unit \output_sr_op__insn_type } { \main_sr_op__insn$53 \main_sr_op__is_signed$52 \main_sr_op__is_32bit$51 \main_sr_op__output_cr$50 \main_sr_op__input_cr$49 \main_sr_op__output_carry$48 \main_sr_op__input_carry$47 { } { \main_sr_op__oe__oe_ok$46 \main_sr_op__oe__oe$45 } { \main_sr_op__rc__rc_ok$44 \main_sr_op__rc__rc$43 } { \main_sr_op__imm_data__imm_ok$42 \main_sr_op__imm_data__imm$41 } \main_sr_op__fn_unit$40 \main_sr_op__insn_type$39 }
     sync init
   end
   process $group_59
@@ -103412,11 +103486,11 @@ module \pipe$89
     assign { \output_o_ok \output_o } { \main_o_ok \main_o }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$77
   process $group_61
     assign \output_cr_a 4'0000
@@ -103424,9 +103498,9 @@ module \pipe$89
     assign { \cr_a_ok$75 \output_cr_a } { \cr_a_ok$77 \cr_a$76 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$79
   process $group_63
     assign \output_xer_ca 2'00
@@ -103468,7 +103542,7 @@ module \pipe$89
     assign \p_valid_i_p_ready_o $81
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$83
   process $group_68
     assign \muxid$83 2'00
@@ -103548,8 +103622,8 @@ module \pipe$89
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \sr_op__insn_type$84
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103562,61 +103636,61 @@ module \pipe$89
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$91
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \sr_op__fn_unit$85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \sr_op__imm_data__imm$86
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__imm_data__imm_ok$87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc$88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc_ok$89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe$90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe_ok$91
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__input_cr$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_cr$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$98
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \sr_op__input_carry$92
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_carry$93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__input_cr$94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_cr$95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_32bit$96
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_signed$97
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \sr_op__insn$98
   process $group_69
-    assign \op__insn_type$84 7'0000000
-    assign \op__fn_unit$85 11'00000000000
-    assign \op__imm_data__imm$86 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$87 1'0
-    assign \op__rc__rc$88 1'0
-    assign \op__rc__rc_ok$89 1'0
-    assign \op__oe__oe$90 1'0
-    assign \op__oe__oe_ok$91 1'0
+    assign \sr_op__insn_type$84 7'0000000
+    assign \sr_op__fn_unit$85 11'00000000000
+    assign \sr_op__imm_data__imm$86 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$87 1'0
+    assign \sr_op__rc__rc$88 1'0
+    assign \sr_op__rc__rc_ok$89 1'0
+    assign \sr_op__oe__oe$90 1'0
+    assign \sr_op__oe__oe_ok$91 1'0
     assign { } 0'0
-    assign \op__input_carry$92 2'00
-    assign \op__output_carry$93 1'0
-    assign \op__input_cr$94 1'0
-    assign \op__output_cr$95 1'0
-    assign \op__is_32bit$96 1'0
-    assign \op__is_signed$97 1'0
-    assign \op__insn$98 32'00000000000000000000000000000000
-    assign { \op__insn$98 \op__is_signed$97 \op__is_32bit$96 \op__output_cr$95 \op__input_cr$94 \op__output_carry$93 \op__input_carry$92 { } { \op__oe__oe_ok$91 \op__oe__oe$90 } { \op__rc__rc_ok$89 \op__rc__rc$88 } { \op__imm_data__imm_ok$87 \op__imm_data__imm$86 } \op__fn_unit$85 \op__insn_type$84 } { \output_op__insn$69 \output_op__is_signed$68 \output_op__is_32bit$67 \output_op__output_cr$66 \output_op__input_cr$65 \output_op__output_carry$64 \output_op__input_carry$63 { } { \output_op__oe__oe_ok$62 \output_op__oe__oe$61 } { \output_op__rc__rc_ok$60 \output_op__rc__rc$59 } { \output_op__imm_data__imm_ok$58 \output_op__imm_data__imm$57 } \output_op__fn_unit$56 \output_op__insn_type$55 }
+    assign \sr_op__input_carry$92 2'00
+    assign \sr_op__output_carry$93 1'0
+    assign \sr_op__input_cr$94 1'0
+    assign \sr_op__output_cr$95 1'0
+    assign \sr_op__is_32bit$96 1'0
+    assign \sr_op__is_signed$97 1'0
+    assign \sr_op__insn$98 32'00000000000000000000000000000000
+    assign { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 } { \output_sr_op__insn$69 \output_sr_op__is_signed$68 \output_sr_op__is_32bit$67 \output_sr_op__output_cr$66 \output_sr_op__input_cr$65 \output_sr_op__output_carry$64 \output_sr_op__input_carry$63 { } { \output_sr_op__oe__oe_ok$62 \output_sr_op__oe__oe$61 } { \output_sr_op__rc__rc_ok$60 \output_sr_op__rc__rc$59 } { \output_sr_op__imm_data__imm_ok$58 \output_sr_op__imm_data__imm$57 } \output_sr_op__fn_unit$56 \output_sr_op__insn_type$55 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \o$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \o_ok$100
   process $group_85
     assign \o$99 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -103624,9 +103698,9 @@ module \pipe$89
     assign { \o_ok$100 \o$99 } { \output_o_ok$71 \output_o$70 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \cr_a$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \cr_a_ok$102
   process $group_87
     assign \cr_a$101 4'0000
@@ -103634,9 +103708,9 @@ module \pipe$89
     assign { \cr_a_ok$102 \cr_a$101 } { \output_cr_a_ok \output_cr_a$72 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \xer_ca$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \xer_ca_ok$104
   process $group_89
     assign \xer_ca$103 2'00
@@ -103686,75 +103760,75 @@ module \pipe$89
       update \muxid$1 \muxid$1$next
   end
   process $group_93
-    assign \op__insn_type$2$next \op__insn_type$2
-    assign \op__fn_unit$3$next \op__fn_unit$3
-    assign \op__imm_data__imm$4$next \op__imm_data__imm$4
-    assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
-    assign \op__rc__rc$6$next \op__rc__rc$6
-    assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
-    assign \op__oe__oe$8$next \op__oe__oe$8
-    assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
+    assign \sr_op__insn_type$2$next \sr_op__insn_type$2
+    assign \sr_op__fn_unit$3$next \sr_op__fn_unit$3
+    assign \sr_op__imm_data__imm$4$next \sr_op__imm_data__imm$4
+    assign \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm_ok$5
+    assign \sr_op__rc__rc$6$next \sr_op__rc__rc$6
+    assign \sr_op__rc__rc_ok$7$next \sr_op__rc__rc_ok$7
+    assign \sr_op__oe__oe$8$next \sr_op__oe__oe$8
+    assign \sr_op__oe__oe_ok$9$next \sr_op__oe__oe_ok$9
     assign { } { }
-    assign \op__input_carry$10$next \op__input_carry$10
-    assign \op__output_carry$11$next \op__output_carry$11
-    assign \op__input_cr$12$next \op__input_cr$12
-    assign \op__output_cr$13$next \op__output_cr$13
-    assign \op__is_32bit$14$next \op__is_32bit$14
-    assign \op__is_signed$15$next \op__is_signed$15
-    assign \op__insn$16$next \op__insn$16
+    assign \sr_op__input_carry$10$next \sr_op__input_carry$10
+    assign \sr_op__output_carry$11$next \sr_op__output_carry$11
+    assign \sr_op__input_cr$12$next \sr_op__input_cr$12
+    assign \sr_op__output_cr$13$next \sr_op__output_cr$13
+    assign \sr_op__is_32bit$14$next \sr_op__is_32bit$14
+    assign \sr_op__is_signed$15$next \sr_op__is_signed$15
+    assign \sr_op__insn$16$next \sr_op__insn$16
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__output_cr$13$next \op__input_cr$12$next \op__output_carry$11$next \op__input_carry$10$next { } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$98 \op__is_signed$97 \op__is_32bit$96 \op__output_cr$95 \op__input_cr$94 \op__output_carry$93 \op__input_carry$92 { } { \op__oe__oe_ok$91 \op__oe__oe$90 } { \op__rc__rc_ok$89 \op__rc__rc$88 } { \op__imm_data__imm_ok$87 \op__imm_data__imm$86 } \op__fn_unit$85 \op__insn_type$84 }
+        assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__output_cr$13$next \op__input_cr$12$next \op__output_carry$11$next \op__input_carry$10$next { } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$98 \op__is_signed$97 \op__is_32bit$96 \op__output_cr$95 \op__input_cr$94 \op__output_carry$93 \op__input_carry$92 { } { \op__oe__oe_ok$91 \op__oe__oe$90 } { \op__rc__rc_ok$89 \op__rc__rc$88 } { \op__imm_data__imm_ok$87 \op__imm_data__imm$86 } \op__fn_unit$85 \op__insn_type$84 }
+        assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \op__imm_data__imm_ok$5$next 1'0
-        assign \op__rc__rc$6$next 1'0
-        assign \op__rc__rc_ok$7$next 1'0
-        assign \op__oe__oe$8$next 1'0
-        assign \op__oe__oe_ok$9$next 1'0
-    end
-    sync init
-      update \op__insn_type$2 7'0000000
-      update \op__fn_unit$3 11'00000000000
-      update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \op__imm_data__imm_ok$5 1'0
-      update \op__rc__rc$6 1'0
-      update \op__rc__rc_ok$7 1'0
-      update \op__oe__oe$8 1'0
-      update \op__oe__oe_ok$9 1'0
+        assign \sr_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \sr_op__imm_data__imm_ok$5$next 1'0
+        assign \sr_op__rc__rc$6$next 1'0
+        assign \sr_op__rc__rc_ok$7$next 1'0
+        assign \sr_op__oe__oe$8$next 1'0
+        assign \sr_op__oe__oe_ok$9$next 1'0
+    end
+    sync init
+      update \sr_op__insn_type$2 7'0000000
+      update \sr_op__fn_unit$3 11'00000000000
+      update \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \sr_op__imm_data__imm_ok$5 1'0
+      update \sr_op__rc__rc$6 1'0
+      update \sr_op__rc__rc_ok$7 1'0
+      update \sr_op__oe__oe$8 1'0
+      update \sr_op__oe__oe_ok$9 1'0
       update { } 0'0
-      update \op__input_carry$10 2'00
-      update \op__output_carry$11 1'0
-      update \op__input_cr$12 1'0
-      update \op__output_cr$13 1'0
-      update \op__is_32bit$14 1'0
-      update \op__is_signed$15 1'0
-      update \op__insn$16 32'00000000000000000000000000000000
+      update \sr_op__input_carry$10 2'00
+      update \sr_op__output_carry$11 1'0
+      update \sr_op__input_cr$12 1'0
+      update \sr_op__output_cr$13 1'0
+      update \sr_op__is_32bit$14 1'0
+      update \sr_op__is_signed$15 1'0
+      update \sr_op__insn$16 32'00000000000000000000000000000000
     sync posedge \clk
-      update \op__insn_type$2 \op__insn_type$2$next
-      update \op__fn_unit$3 \op__fn_unit$3$next
-      update \op__imm_data__imm$4 \op__imm_data__imm$4$next
-      update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
-      update \op__rc__rc$6 \op__rc__rc$6$next
-      update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
-      update \op__oe__oe$8 \op__oe__oe$8$next
-      update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
+      update \sr_op__insn_type$2 \sr_op__insn_type$2$next
+      update \sr_op__fn_unit$3 \sr_op__fn_unit$3$next
+      update \sr_op__imm_data__imm$4 \sr_op__imm_data__imm$4$next
+      update \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm_ok$5$next
+      update \sr_op__rc__rc$6 \sr_op__rc__rc$6$next
+      update \sr_op__rc__rc_ok$7 \sr_op__rc__rc_ok$7$next
+      update \sr_op__oe__oe$8 \sr_op__oe__oe$8$next
+      update \sr_op__oe__oe_ok$9 \sr_op__oe__oe_ok$9$next
       update { } { }
-      update \op__input_carry$10 \op__input_carry$10$next
-      update \op__output_carry$11 \op__output_carry$11$next
-      update \op__input_cr$12 \op__input_cr$12$next
-      update \op__output_cr$13 \op__output_cr$13$next
-      update \op__is_32bit$14 \op__is_32bit$14$next
-      update \op__is_signed$15 \op__is_signed$15$next
-      update \op__insn$16 \op__insn$16$next
+      update \sr_op__input_carry$10 \sr_op__input_carry$10$next
+      update \sr_op__output_carry$11 \sr_op__output_carry$11$next
+      update \sr_op__input_cr$12 \sr_op__input_cr$12$next
+      update \sr_op__output_cr$13 \sr_op__output_cr$13$next
+      update \sr_op__is_32bit$14 \sr_op__is_32bit$14$next
+      update \sr_op__is_signed$15 \sr_op__is_signed$15$next
+      update \sr_op__insn$16 \sr_op__insn$16$next
   end
   process $group_109
     assign \o$next \o
@@ -103849,21 +103923,21 @@ module \alu_shift_rot0
   wire width 1 input 0 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 4 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 6 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 7 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 output 8 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 output 9 \xer_ca
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -103938,8 +104012,8 @@ module \alu_shift_rot0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 10 \op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 10 \sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103952,45 +104026,45 @@ module \alu_shift_rot0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 11 \op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 12 \op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 11 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 12 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 19 \op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 20 \op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 21 \op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 22 \op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 23 \op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 24 \op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 25 \op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 19 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 21 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 22 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 23 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 24 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 25 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 26 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 27 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 input 28 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 input 29 \xer_ca$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 30 \p_valid_i
@@ -104008,7 +104082,7 @@ module \alu_shift_rot0
   wire width 1 \pipe_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -104083,8 +104157,8 @@ module \alu_shift_rot0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -104097,51 +104171,51 @@ module \alu_shift_rot0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \pipe_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \pipe_rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \pipe_xer_ca
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \pipe_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \pipe_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \pipe_muxid$2
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -104216,8 +104290,8 @@ module \alu_shift_rot0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \pipe_op__insn_type$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_sr_op__insn_type$3
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -104230,49 +104304,49 @@ module \alu_shift_rot0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \pipe_op__fn_unit$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \pipe_op__imm_data__imm$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__imm_data__imm_ok$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__rc__rc_ok$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__oe__oe_ok$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_sr_op__fn_unit$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_sr_op__imm_data__imm$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__imm_data__imm_ok$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc_ok$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe_ok$10
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \pipe_op__input_carry$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_carry$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__input_cr$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__output_cr$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_32bit$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \pipe_op__is_signed$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \pipe_op__insn$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_sr_op__input_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__input_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_cr$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_32bit$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_signed$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_sr_op__insn$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \pipe_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \pipe_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \pipe_xer_ca$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ca_ok
   cell \pipe$89 \pipe
     connect \rst \rst
@@ -104280,21 +104354,21 @@ module \alu_shift_rot0
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
-    connect \op__insn_type \pipe_op__insn_type
-    connect \op__fn_unit \pipe_op__fn_unit
-    connect \op__imm_data__imm \pipe_op__imm_data__imm
-    connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
-    connect \op__rc__rc \pipe_op__rc__rc
-    connect \op__rc__rc_ok \pipe_op__rc__rc_ok
-    connect \op__oe__oe \pipe_op__oe__oe
-    connect \op__oe__oe_ok \pipe_op__oe__oe_ok
-    connect \op__input_carry \pipe_op__input_carry
-    connect \op__output_carry \pipe_op__output_carry
-    connect \op__input_cr \pipe_op__input_cr
-    connect \op__output_cr \pipe_op__output_cr
-    connect \op__is_32bit \pipe_op__is_32bit
-    connect \op__is_signed \pipe_op__is_signed
-    connect \op__insn \pipe_op__insn
+    connect \sr_op__insn_type \pipe_sr_op__insn_type
+    connect \sr_op__fn_unit \pipe_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \pipe_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \pipe_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \pipe_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \pipe_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \pipe_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \pipe_sr_op__input_carry
+    connect \sr_op__output_carry \pipe_sr_op__output_carry
+    connect \sr_op__input_cr \pipe_sr_op__input_cr
+    connect \sr_op__output_cr \pipe_sr_op__output_cr
+    connect \sr_op__is_32bit \pipe_sr_op__is_32bit
+    connect \sr_op__is_signed \pipe_sr_op__is_signed
+    connect \sr_op__insn \pipe_sr_op__insn
     connect \ra \pipe_ra
     connect \rb \pipe_rb
     connect \rc \pipe_rc
@@ -104302,21 +104376,21 @@ module \alu_shift_rot0
     connect \n_valid_o \pipe_n_valid_o
     connect \n_ready_i \pipe_n_ready_i
     connect \muxid$1 \pipe_muxid$2
-    connect \op__insn_type$2 \pipe_op__insn_type$3
-    connect \op__fn_unit$3 \pipe_op__fn_unit$4
-    connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$5
-    connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$6
-    connect \op__rc__rc$6 \pipe_op__rc__rc$7
-    connect \op__rc__rc_ok$7 \pipe_op__rc__rc_ok$8
-    connect \op__oe__oe$8 \pipe_op__oe__oe$9
-    connect \op__oe__oe_ok$9 \pipe_op__oe__oe_ok$10
-    connect \op__input_carry$10 \pipe_op__input_carry$11
-    connect \op__output_carry$11 \pipe_op__output_carry$12
-    connect \op__input_cr$12 \pipe_op__input_cr$13
-    connect \op__output_cr$13 \pipe_op__output_cr$14
-    connect \op__is_32bit$14 \pipe_op__is_32bit$15
-    connect \op__is_signed$15 \pipe_op__is_signed$16
-    connect \op__insn$16 \pipe_op__insn$17
+    connect \sr_op__insn_type$2 \pipe_sr_op__insn_type$3
+    connect \sr_op__fn_unit$3 \pipe_sr_op__fn_unit$4
+    connect \sr_op__imm_data__imm$4 \pipe_sr_op__imm_data__imm$5
+    connect \sr_op__imm_data__imm_ok$5 \pipe_sr_op__imm_data__imm_ok$6
+    connect \sr_op__rc__rc$6 \pipe_sr_op__rc__rc$7
+    connect \sr_op__rc__rc_ok$7 \pipe_sr_op__rc__rc_ok$8
+    connect \sr_op__oe__oe$8 \pipe_sr_op__oe__oe$9
+    connect \sr_op__oe__oe_ok$9 \pipe_sr_op__oe__oe_ok$10
+    connect \sr_op__input_carry$10 \pipe_sr_op__input_carry$11
+    connect \sr_op__output_carry$11 \pipe_sr_op__output_carry$12
+    connect \sr_op__input_cr$12 \pipe_sr_op__input_cr$13
+    connect \sr_op__output_cr$13 \pipe_sr_op__output_cr$14
+    connect \sr_op__is_32bit$14 \pipe_sr_op__is_32bit$15
+    connect \sr_op__is_signed$15 \pipe_sr_op__is_signed$16
+    connect \sr_op__insn$16 \pipe_sr_op__insn$17
     connect \o \pipe_o
     connect \o_ok \pipe_o_ok
     connect \cr_a \pipe_cr_a
@@ -104334,7 +104408,7 @@ module \alu_shift_rot0
     assign \p_ready_o \pipe_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid
   process $group_2
     assign \pipe_muxid 2'00
@@ -104342,23 +104416,23 @@ module \alu_shift_rot0
     sync init
   end
   process $group_3
-    assign \pipe_op__insn_type 7'0000000
-    assign \pipe_op__fn_unit 11'00000000000
-    assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_op__imm_data__imm_ok 1'0
-    assign \pipe_op__rc__rc 1'0
-    assign \pipe_op__rc__rc_ok 1'0
-    assign \pipe_op__oe__oe 1'0
-    assign \pipe_op__oe__oe_ok 1'0
+    assign \pipe_sr_op__insn_type 7'0000000
+    assign \pipe_sr_op__fn_unit 11'00000000000
+    assign \pipe_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_sr_op__imm_data__imm_ok 1'0
+    assign \pipe_sr_op__rc__rc 1'0
+    assign \pipe_sr_op__rc__rc_ok 1'0
+    assign \pipe_sr_op__oe__oe 1'0
+    assign \pipe_sr_op__oe__oe_ok 1'0
     assign { } 0'0
-    assign \pipe_op__input_carry 2'00
-    assign \pipe_op__output_carry 1'0
-    assign \pipe_op__input_cr 1'0
-    assign \pipe_op__output_cr 1'0
-    assign \pipe_op__is_32bit 1'0
-    assign \pipe_op__is_signed 1'0
-    assign \pipe_op__insn 32'00000000000000000000000000000000
-    assign { \pipe_op__insn \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_cr \pipe_op__input_cr \pipe_op__output_carry \pipe_op__input_carry { } { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+    assign \pipe_sr_op__input_carry 2'00
+    assign \pipe_sr_op__output_carry 1'0
+    assign \pipe_sr_op__input_cr 1'0
+    assign \pipe_sr_op__output_cr 1'0
+    assign \pipe_sr_op__is_32bit 1'0
+    assign \pipe_sr_op__is_signed 1'0
+    assign \pipe_sr_op__insn 32'00000000000000000000000000000000
+    assign { \pipe_sr_op__insn \pipe_sr_op__is_signed \pipe_sr_op__is_32bit \pipe_sr_op__output_cr \pipe_sr_op__input_cr \pipe_sr_op__output_carry \pipe_sr_op__input_carry { } { \pipe_sr_op__oe__oe_ok \pipe_sr_op__oe__oe } { \pipe_sr_op__rc__rc_ok \pipe_sr_op__rc__rc } { \pipe_sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm } \pipe_sr_op__fn_unit \pipe_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
     sync init
   end
   process $group_19
@@ -104391,7 +104465,7 @@ module \alu_shift_rot0
     assign \pipe_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 \muxid$19
   process $group_25
     assign \muxid$19 2'00
@@ -104471,8 +104545,8 @@ module \alu_shift_rot0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \op__insn_type$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \sr_op__insn_type$20
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -104485,56 +104559,56 @@ module \alu_shift_rot0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \op__fn_unit$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \op__imm_data__imm$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__imm_data__imm_ok$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__rc__rc_ok$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__oe__oe_ok$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \sr_op__fn_unit$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \sr_op__imm_data__imm$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__imm_data__imm_ok$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc_ok$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe_ok$27
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \op__input_carry$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_carry$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__input_cr$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__output_cr$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_32bit$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \op__is_signed$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \op__insn$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \sr_op__input_carry$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_carry$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__input_cr$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_cr$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_32bit$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_signed$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \sr_op__insn$34
   process $group_26
-    assign \op__insn_type$20 7'0000000
-    assign \op__fn_unit$21 11'00000000000
-    assign \op__imm_data__imm$22 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \op__imm_data__imm_ok$23 1'0
-    assign \op__rc__rc$24 1'0
-    assign \op__rc__rc_ok$25 1'0
-    assign \op__oe__oe$26 1'0
-    assign \op__oe__oe_ok$27 1'0
+    assign \sr_op__insn_type$20 7'0000000
+    assign \sr_op__fn_unit$21 11'00000000000
+    assign \sr_op__imm_data__imm$22 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$23 1'0
+    assign \sr_op__rc__rc$24 1'0
+    assign \sr_op__rc__rc_ok$25 1'0
+    assign \sr_op__oe__oe$26 1'0
+    assign \sr_op__oe__oe_ok$27 1'0
     assign { } 0'0
-    assign \op__input_carry$28 2'00
-    assign \op__output_carry$29 1'0
-    assign \op__input_cr$30 1'0
-    assign \op__output_cr$31 1'0
-    assign \op__is_32bit$32 1'0
-    assign \op__is_signed$33 1'0
-    assign \op__insn$34 32'00000000000000000000000000000000
-    assign { \op__insn$34 \op__is_signed$33 \op__is_32bit$32 \op__output_cr$31 \op__input_cr$30 \op__output_carry$29 \op__input_carry$28 { } { \op__oe__oe_ok$27 \op__oe__oe$26 } { \op__rc__rc_ok$25 \op__rc__rc$24 } { \op__imm_data__imm_ok$23 \op__imm_data__imm$22 } \op__fn_unit$21 \op__insn_type$20 } { \pipe_op__insn$17 \pipe_op__is_signed$16 \pipe_op__is_32bit$15 \pipe_op__output_cr$14 \pipe_op__input_cr$13 \pipe_op__output_carry$12 \pipe_op__input_carry$11 { } { \pipe_op__oe__oe_ok$10 \pipe_op__oe__oe$9 } { \pipe_op__rc__rc_ok$8 \pipe_op__rc__rc$7 } { \pipe_op__imm_data__imm_ok$6 \pipe_op__imm_data__imm$5 } \pipe_op__fn_unit$4 \pipe_op__insn_type$3 }
+    assign \sr_op__input_carry$28 2'00
+    assign \sr_op__output_carry$29 1'0
+    assign \sr_op__input_cr$30 1'0
+    assign \sr_op__output_cr$31 1'0
+    assign \sr_op__is_32bit$32 1'0
+    assign \sr_op__is_signed$33 1'0
+    assign \sr_op__insn$34 32'00000000000000000000000000000000
+    assign { \sr_op__insn$34 \sr_op__is_signed$33 \sr_op__is_32bit$32 \sr_op__output_cr$31 \sr_op__input_cr$30 \sr_op__output_carry$29 \sr_op__input_carry$28 { } { \sr_op__oe__oe_ok$27 \sr_op__oe__oe$26 } { \sr_op__rc__rc_ok$25 \sr_op__rc__rc$24 } { \sr_op__imm_data__imm_ok$23 \sr_op__imm_data__imm$22 } \sr_op__fn_unit$21 \sr_op__insn_type$20 } { \pipe_sr_op__insn$17 \pipe_sr_op__is_signed$16 \pipe_sr_op__is_32bit$15 \pipe_sr_op__output_cr$14 \pipe_sr_op__input_cr$13 \pipe_sr_op__output_carry$12 \pipe_sr_op__input_carry$11 { } { \pipe_sr_op__oe__oe_ok$10 \pipe_sr_op__oe__oe$9 } { \pipe_sr_op__rc__rc_ok$8 \pipe_sr_op__rc__rc$7 } { \pipe_sr_op__imm_data__imm_ok$6 \pipe_sr_op__imm_data__imm$5 } \pipe_sr_op__fn_unit$4 \pipe_sr_op__insn_type$3 }
     sync init
   end
   process $group_42
@@ -105652,8 +105726,8 @@ module \shiftrot0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 2 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 2 \oper_i_alu_shift_rot0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -105666,85 +105740,85 @@ module \shiftrot0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 3 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 4 \oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 5 \oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 6 \oper_i__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 7 \oper_i__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \oper_i__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \oper_i__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 3 \oper_i_alu_shift_rot0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \oper_i_alu_shift_rot0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \oper_i_alu_shift_rot0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_alu_shift_rot0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_alu_shift_rot0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_alu_shift_rot0__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 11 \oper_i__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \oper_i__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \oper_i__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \oper_i__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \oper_i__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 17 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 18 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 11 \oper_i_alu_shift_rot0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_alu_shift_rot0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_alu_shift_rot0__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_alu_shift_rot0__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_alu_shift_rot0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \oper_i_alu_shift_rot0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 17 \oper_i_alu_shift_rot0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 19 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 input 20 \rdmaskn
+  wire width 1 input 18 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 19 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 20 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 21 \rd__rel
+  wire width 4 output 21 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 22 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 4 input 22 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 23 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 24 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 25 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 input 26 \src4_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 27 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 28 \wr__rel
+  wire width 3 output 28 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 29 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 3 input 29 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 30 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 31 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 output 32 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 34 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 35 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 36 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 35 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 36 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_shift_rot0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 \alu_shift_rot0_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \alu_shift_rot0_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 4 \alu_shift_rot0_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 2 \alu_shift_rot0_xer_ca
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -105819,8 +105893,8 @@ module \shiftrot0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 \alu_shift_rot0_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_shift_rot0_sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -105833,45 +105907,45 @@ module \shiftrot0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 \alu_shift_rot0_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \alu_shift_rot0_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_shift_rot0_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_shift_rot0_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 \alu_shift_rot0_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \alu_shift_rot0_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 \alu_shift_rot0_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \alu_shift_rot0_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_shift_rot0_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_shift_rot0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_shift_rot0_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \alu_shift_rot0_rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 2 \alu_shift_rot0_xer_ca$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 \alu_shift_rot0_p_valid_i
@@ -105888,21 +105962,21 @@ module \shiftrot0
     connect \o \alu_shift_rot0_o
     connect \cr_a \alu_shift_rot0_cr_a
     connect \xer_ca \alu_shift_rot0_xer_ca
-    connect \op__insn_type \alu_shift_rot0_op__insn_type
-    connect \op__fn_unit \alu_shift_rot0_op__fn_unit
-    connect \op__imm_data__imm \alu_shift_rot0_op__imm_data__imm
-    connect \op__imm_data__imm_ok \alu_shift_rot0_op__imm_data__imm_ok
-    connect \op__rc__rc \alu_shift_rot0_op__rc__rc
-    connect \op__rc__rc_ok \alu_shift_rot0_op__rc__rc_ok
-    connect \op__oe__oe \alu_shift_rot0_op__oe__oe
-    connect \op__oe__oe_ok \alu_shift_rot0_op__oe__oe_ok
-    connect \op__input_carry \alu_shift_rot0_op__input_carry
-    connect \op__output_carry \alu_shift_rot0_op__output_carry
-    connect \op__input_cr \alu_shift_rot0_op__input_cr
-    connect \op__output_cr \alu_shift_rot0_op__output_cr
-    connect \op__is_32bit \alu_shift_rot0_op__is_32bit
-    connect \op__is_signed \alu_shift_rot0_op__is_signed
-    connect \op__insn \alu_shift_rot0_op__insn
+    connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type
+    connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry
+    connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry
+    connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr
+    connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr
+    connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit
+    connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed
+    connect \sr_op__insn \alu_shift_rot0_sr_op__insn
     connect \ra \alu_shift_rot0_ra
     connect \rb \alu_shift_rot0_rb
     connect \rc \alu_shift_rot0_rc
@@ -106012,36 +106086,36 @@ module \shiftrot0
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
   wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   wire width 1 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
   cell $and $3
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B \rok_l_q_rdok
     connect \Y $2
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 4 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rd__rel
+    connect \A \cu_rd__rel_o
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 4 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $or $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -106049,10 +106123,10 @@ module \shiftrot0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A $5
-    connect \B \rd__go
+    connect \B \cu_rd__go_i
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $reduce_and $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -106060,9 +106134,9 @@ module \shiftrot0
     connect \A $7
     connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
   cell $and $11
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106078,9 +106152,9 @@ module \shiftrot0
     assign \all_rd $10
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
   wire width 1 \all_rd_dly$next
   process $group_1
     assign \all_rd_dly$next \all_rd_dly
@@ -106090,11 +106164,11 @@ module \shiftrot0
     sync posedge \clk
       update \all_rd_dly \all_rd_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
   wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $not $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106102,9 +106176,9 @@ module \shiftrot0
     connect \A \all_rd_dly
     connect \Y $12
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
   cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106120,16 +106194,16 @@ module \shiftrot0
     assign \all_rd_pulse $14
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
     assign \alu_done \alu_shift_rot0_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
   wire width 1 \alu_done_dly$next
   process $group_4
     assign \alu_done_dly$next \alu_done_dly
@@ -106139,11 +106213,11 @@ module \shiftrot0
     sync posedge \clk
       update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
   wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $not $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106151,9 +106225,9 @@ module \shiftrot0
     connect \A \alu_done_dly
     connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
   cell $and $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106169,28 +106243,28 @@ module \shiftrot0
     assign \alu_pulse $18
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
   wire width 3 \alu_pulsem
   process $group_6
     assign \alu_pulsem 3'000
     assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
   wire width 3 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   wire width 3 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
   cell $and $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \busy_o \busy_o \busy_o }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $20
   end
   process $group_7
@@ -106206,38 +106280,38 @@ module \shiftrot0
     sync posedge \clk
       update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 3 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 3 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 3 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__rel
+    connect \A \cu_wr__rel_o
     connect \B $24
     connect \Y $26
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $reduce_bool $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -106245,7 +106319,7 @@ module \shiftrot0
     connect \A $26
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $not $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106253,39 +106327,39 @@ module \shiftrot0
     connect \A $23
     connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
   cell $and $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
+    connect \A \cu_busy_o
     connect \B $22
     connect \Y $30
   end
   process $group_8
-    assign \done_o 1'0
-    assign \done_o $30
+    assign \cu_done_o 1'0
+    assign \cu_done_o $30
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
   wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \wr__go
+    connect \A \cu_wr__go_i
     connect \Y $32
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $reduce_bool $35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -106293,9 +106367,9 @@ module \shiftrot0
     connect \A \prev_wr_go
     connect \Y $34
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
   cell $or $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106311,11 +106385,11 @@ module \shiftrot0
     assign \wr_any $36
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
   wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $not $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106323,9 +106397,9 @@ module \shiftrot0
     connect \A \alu_shift_rot0_n_ready_i
     connect \Y $38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
   cell $and $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106336,9 +106410,9 @@ module \shiftrot0
     connect \B $38
     connect \Y $40
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 3 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -106346,12 +106420,12 @@ module \shiftrot0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \req_l_q_req
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $eq $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -106362,9 +106436,9 @@ module \shiftrot0
     connect \B 1'0
     connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   wire width 1 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
   cell $and $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106375,22 +106449,22 @@ module \shiftrot0
     connect \B $44
     connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $eq $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrmask
+    connect \A \cu_wrmask_o
     connect \B 1'0
     connect \Y $48
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106401,9 +106475,9 @@ module \shiftrot0
     connect \B \alu_shift_rot0_n_ready_i
     connect \Y $50
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106414,9 +106488,9 @@ module \shiftrot0
     connect \B \alu_shift_rot0_n_valid_o
     connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   wire width 1 $54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
   cell $and $55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106424,25 +106498,25 @@ module \shiftrot0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $52
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $54
   end
   process $group_10
     assign \req_done 1'0
     assign \req_done $46
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
     switch { $54 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
         assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   cell $or $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106450,7 +106524,7 @@ module \shiftrot0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \req_done
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $56
   end
   process $group_11
@@ -106458,19 +106532,19 @@ module \shiftrot0
     assign \reset $56
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
   wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   wire width 1 $58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
   cell $or $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $58
   end
   process $group_12
@@ -106478,19 +106552,19 @@ module \shiftrot0
     assign \rst_r $58
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
   wire width 3 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   wire width 3 $60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
   cell $or $61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \wr__go
-    connect \B { \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $60
   end
   process $group_13
@@ -106498,19 +106572,19 @@ module \shiftrot0
     assign \reset_w $60
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
   wire width 4 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   wire width 4 $62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
   cell $or $63
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $62
   end
   process $group_14
@@ -106520,12 +106594,12 @@ module \shiftrot0
   end
   process $group_15
     assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \issue_i
+    assign \rok_l_s_rdok \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   wire width 1 $64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
   cell $and $65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -106533,7 +106607,7 @@ module \shiftrot0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_shift_rot0_n_valid_o
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $64
   end
   process $group_16
@@ -106561,7 +106635,7 @@ module \shiftrot0
   end
   process $group_19
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -106587,7 +106661,7 @@ module \shiftrot0
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -106611,9 +106685,9 @@ module \shiftrot0
     sync posedge \clk
       update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   wire width 3 $66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
   cell $and $67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -106621,7 +106695,7 @@ module \shiftrot0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \alu_pulsem
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $66
   end
   process $group_23
@@ -106629,9 +106703,9 @@ module \shiftrot0
     assign \req_l_s_req $66
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   wire width 3 $68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
   cell $or $69
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -106720,7 +106794,7 @@ module \shiftrot0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -106734,37 +106808,37 @@ module \shiftrot0
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 11 \oper_r__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 2 \oper_r__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -106832,8 +106906,8 @@ module \shiftrot0
   cell $mux $71
     parameter \WIDTH 126
     connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
-    connect \S \issue_i
+    connect \B { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
+    connect \S \cu_issue_i
     connect \Y $70
   end
   process $group_25
@@ -106874,10 +106948,10 @@ module \shiftrot0
     assign \oper_l__is_signed$next \oper_l__is_signed
     assign \oper_l__insn$next \oper_l__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -106924,9 +106998,9 @@ module \shiftrot0
       update \oper_l__is_signed \oper_l__is_signed$next
       update \oper_l__insn \oper_l__insn$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r0__o_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \data_r0_l__o
@@ -106993,9 +107067,9 @@ module \shiftrot0
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 4 \data_r1__cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r1__cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 4 \data_r1_l__cr_a
@@ -107062,9 +107136,9 @@ module \shiftrot0
       update \data_r1_l__cr_a \data_r1_l__cr_a$next
       update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 2 \data_r2__xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
   wire width 1 \data_r2__xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \data_r2_l__xer_ca
@@ -107131,9 +107205,9 @@ module \shiftrot0
       update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
       update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $91
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -107141,12 +107215,12 @@ module \shiftrot0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r0__o_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $90
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $93
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -107154,12 +107228,12 @@ module \shiftrot0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r1__cr_a_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $92
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   wire width 1 $94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
   cell $and $95
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -107167,39 +107241,39 @@ module \shiftrot0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \data_r2__xer_ca_ok
-    connect \B \busy_o
+    connect \B \cu_busy_o
     connect \Y $94
   end
   process $group_69
-    assign \wrmask 3'000
-    assign \wrmask { $94 $92 $90 }
+    assign \cu_wrmask_o 3'000
+    assign \cu_wrmask_o { $94 $92 $90 }
     sync init
   end
   process $group_70
-    assign \alu_shift_rot0_op__insn_type 7'0000000
-    assign \alu_shift_rot0_op__fn_unit 11'00000000000
-    assign \alu_shift_rot0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_shift_rot0_op__imm_data__imm_ok 1'0
-    assign \alu_shift_rot0_op__rc__rc 1'0
-    assign \alu_shift_rot0_op__rc__rc_ok 1'0
-    assign \alu_shift_rot0_op__oe__oe 1'0
-    assign \alu_shift_rot0_op__oe__oe_ok 1'0
+    assign \alu_shift_rot0_sr_op__insn_type 7'0000000
+    assign \alu_shift_rot0_sr_op__fn_unit 11'00000000000
+    assign \alu_shift_rot0_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_shift_rot0_sr_op__imm_data__imm_ok 1'0
+    assign \alu_shift_rot0_sr_op__rc__rc 1'0
+    assign \alu_shift_rot0_sr_op__rc__rc_ok 1'0
+    assign \alu_shift_rot0_sr_op__oe__oe 1'0
+    assign \alu_shift_rot0_sr_op__oe__oe_ok 1'0
     assign { } 0'0
-    assign \alu_shift_rot0_op__input_carry 2'00
-    assign \alu_shift_rot0_op__output_carry 1'0
-    assign \alu_shift_rot0_op__input_cr 1'0
-    assign \alu_shift_rot0_op__output_cr 1'0
-    assign \alu_shift_rot0_op__is_32bit 1'0
-    assign \alu_shift_rot0_op__is_signed 1'0
-    assign \alu_shift_rot0_op__insn 32'00000000000000000000000000000000
-    assign { \alu_shift_rot0_op__insn \alu_shift_rot0_op__is_signed \alu_shift_rot0_op__is_32bit \alu_shift_rot0_op__output_cr \alu_shift_rot0_op__input_cr \alu_shift_rot0_op__output_carry \alu_shift_rot0_op__input_carry { } { \alu_shift_rot0_op__oe__oe_ok \alu_shift_rot0_op__oe__oe } { \alu_shift_rot0_op__rc__rc_ok \alu_shift_rot0_op__rc__rc } { \alu_shift_rot0_op__imm_data__imm_ok \alu_shift_rot0_op__imm_data__imm } \alu_shift_rot0_op__fn_unit \alu_shift_rot0_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+    assign \alu_shift_rot0_sr_op__input_carry 2'00
+    assign \alu_shift_rot0_sr_op__output_carry 1'0
+    assign \alu_shift_rot0_sr_op__input_cr 1'0
+    assign \alu_shift_rot0_sr_op__output_cr 1'0
+    assign \alu_shift_rot0_sr_op__is_32bit 1'0
+    assign \alu_shift_rot0_sr_op__is_signed 1'0
+    assign \alu_shift_rot0_sr_op__insn 32'00000000000000000000000000000000
+    assign { \alu_shift_rot0_sr_op__insn \alu_shift_rot0_sr_op__is_signed \alu_shift_rot0_sr_op__is_32bit \alu_shift_rot0_sr_op__output_cr \alu_shift_rot0_sr_op__input_cr \alu_shift_rot0_sr_op__output_carry \alu_shift_rot0_sr_op__input_carry { } { \alu_shift_rot0_sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe } { \alu_shift_rot0_sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc } { \alu_shift_rot0_sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm } \alu_shift_rot0_sr_op__fn_unit \alu_shift_rot0_sr_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
   wire width 1 \src_sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   wire width 1 $96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
   cell $mux $97
     parameter \WIDTH 1
     connect \A \src_l_q_src [1]
@@ -107212,11 +107286,11 @@ module \shiftrot0
     assign \src_sel $96
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
   wire width 64 \src_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   wire width 64 $98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
   cell $mux $99
     parameter \WIDTH 64
     connect \A \src2_i
@@ -107362,9 +107436,9 @@ module \shiftrot0
     assign \alu_shift_rot0_p_valid_i \alui_l_q_alui
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   wire width 1 $108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
   cell $and $109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -107398,9 +107472,9 @@ module \shiftrot0
     assign \alu_shift_rot0_n_ready_i \alu_l_q_alu
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   wire width 1 $110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
   cell $and $111
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -107430,13 +107504,13 @@ module \shiftrot0
     sync init
   end
   process $group_102
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $113
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -107444,12 +107518,12 @@ module \shiftrot0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o \busy_o }
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
     connect \Y $112
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   wire width 1 $114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
   cell $not $115
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -107457,9 +107531,9 @@ module \shiftrot0
     connect \A \oper_r__imm_data__imm_ok
     connect \Y $114
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $117
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -107470,19 +107544,19 @@ module \shiftrot0
     connect \B { 1'1 1'1 $114 1'1 }
     connect \Y $116
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $not $119
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \rdmaskn
+    connect \A \cu_rdmaskn_i
     connect \Y $118
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   wire width 4 $120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
   cell $and $121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
@@ -107494,52 +107568,52 @@ module \shiftrot0
     connect \Y $120
   end
   process $group_103
-    assign \rd__rel 4'0000
-    assign \rd__rel $120
+    assign \cu_rd__rel_o 4'0000
+    assign \cu_rd__rel_o $120
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $122
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $124
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   cell $and $127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B \shadown_i
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
     connect \Y $126
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -107550,9 +107624,9 @@ module \shiftrot0
     connect \B { $122 $124 $126 }
     connect \Y $128
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   wire width 3 $130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
   cell $and $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -107560,78 +107634,78 @@ module \shiftrot0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A $128
-    connect \B \wrmask
+    connect \B \cu_wrmask_o
     connect \Y $130
   end
   process $group_104
-    assign \wr__rel 3'000
-    assign \wr__rel $130
+    assign \cu_wr__rel_o 3'000
+    assign \cu_wr__rel_o $130
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
     connect \Y $132
   end
   process $group_105
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $132 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
     connect \Y $134
   end
   process $group_106
     assign \dest2_o 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $134 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   wire width 1 $136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
   cell $and $137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [2]
-    connect \B \busy_o
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
     connect \Y $136
   end
   process $group_107
     assign \dest3_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $136 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
         assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
     end
@@ -108231,8 +108305,6 @@ module \lod_l
   wire width 1 input 3 \r_lod
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
   wire width 1 output 4 \qn_lod
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 5 \q_lod
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -108286,6 +108358,8 @@ module \lod_l
     sync posedge \clk
       update \q_int \q_int$next
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \q_lod
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   wire width 1 $7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108944,16 +109018,161 @@ module \rst_l$105
   end
 end
 attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l"
+module \lsd_l
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_lsd
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_lsd
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_lsd
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_lsd
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_lsd 1'0
+    assign \q_lsd $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_lsd
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_lsd 1'0
+    assign \qn_lsd $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_lsd
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_lsd 1'0
+    assign \qlq_lsd $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0"
 module \ldst0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 0 \ad__go
+  wire width 1 input 0 \ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 1 \ad__rel
+  wire width 1 output 1 \ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 2 \st__go
+  wire width 1 input 2 \st__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 3 \st__rel
+  wire width 1 output 3 \st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 4 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
@@ -109031,92 +109250,92 @@ module \ldst0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 6 \oper_i__insn_type
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 7 \oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 8 \oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \oper_i__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \oper_i__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \oper_i__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \oper_i__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \oper_i__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \oper_i__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 16 \oper_i__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \oper_i__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 18 \oper_i__sign_extend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 6 \oper_i_ldst_ldst0__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_ldst_ldst0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_ldst_ldst0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_ldst_ldst0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_ldst_ldst0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_ldst_ldst0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_ldst_ldst0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 16 \oper_i_ldst_ldst0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \oper_i_ldst_ldst0__byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \oper_i_ldst_ldst0__sign_extend
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 19 \oper_i__ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 20 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 21 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 input 22 \rdmaskn
+  wire width 1 input 20 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 21 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 22 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 23 \rd__rel
+  wire width 3 output 23 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 24 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 3 input 24 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 25 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 26 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 27 \src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 28 \wr__rel
+  wire width 2 output 28 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 input 29 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 2 input 29 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 30 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 31 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 32 \go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 32 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
   wire width 1 output 33 \load_mem_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
   wire width 1 output 34 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 35 \shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 35 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 36 \ldst_port0_is_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
   wire width 1 output 37 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 output 38 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 96 output 39 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 40 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 input 41 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 input 42 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 43 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 44 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 45 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 46 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \opc_l_s_opc
@@ -109186,15 +109405,12 @@ module \ldst0
   wire width 1 \lod_l_r_lod
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
   wire width 1 \lod_l_qn_lod
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \lod_l_q_lod
   cell \lod_l \lod_l
     connect \rst \rst
     connect \clk \clk
     connect \s_lod \lod_l_s_lod
     connect \r_lod \lod_l_r_lod
     connect \qn_lod \lod_l_qn_lod
-    connect \q_lod \lod_l_q_lod
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \sto_l_s_sto
@@ -109254,19 +109470,34 @@ module \ldst0
     connect \r_rst \rst_l_r_rst
     connect \q_rst \rst_l_q_rst
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \lsd_l_s_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \lsd_l_r_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \lsd_l_r_lsd$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \lsd_l_q_lsd
+  cell \lsd_l \lsd_l
+    connect \rst \rst
+    connect \clk \clk
+    connect \s_lsd \lsd_l_s_lsd
+    connect \r_lsd \lsd_l_r_lsd
+    connect \q_lsd \lsd_l_q_lsd
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289"
   wire width 1 \reset_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
   cell $or $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \issue_i
-    connect \B \go_die_i
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
     connect \Y $1
   end
   process $group_0
@@ -109274,13 +109505,13 @@ module \ldst0
     assign \reset_i $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:284"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:285"
   wire width 1 \reset_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275"
   wire width 1 \wr_reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
   cell $or $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109288,7 +109519,7 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \wr_reset
-    connect \B \go_die_i
+    connect \B \cu_go_die_i
     connect \Y $3
   end
   process $group_1
@@ -109296,19 +109527,19 @@ module \ldst0
     assign \reset_o $3
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:285"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286"
   wire width 1 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
   cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [0]
-    connect \B \go_die_i
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_go_die_i
     connect \Y $5
   end
   process $group_2
@@ -109316,19 +109547,19 @@ module \ldst0
     assign \reset_w $5
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287"
   wire width 1 \reset_u
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
   cell $or $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__go [1]
-    connect \B \go_die_i
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_go_die_i
     connect \Y $7
   end
   process $group_3
@@ -109336,19 +109567,19 @@ module \ldst0
     assign \reset_u $7
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291"
   wire width 1 \reset_s
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
   cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \st__go
-    connect \B \go_die_i
+    connect \A \st__go_i
+    connect \B \cu_go_die_i
     connect \Y $9
   end
   process $group_4
@@ -109356,19 +109587,19 @@ module \ldst0
     assign \reset_s $9
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290"
   wire width 3 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
   wire width 3 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
   cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rd__go
-    connect \B { \go_die_i \go_die_i \go_die_i }
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
     connect \Y $11
   end
   process $group_5
@@ -109376,19 +109607,19 @@ module \ldst0
     assign \reset_r $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288"
   wire width 1 \reset_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
   cell $or $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ad__go
-    connect \B \go_die_i
+    connect \A \ad__go_i
+    connect \B \cu_go_die_i
     connect \Y $13
   end
   process $group_6
@@ -109396,13 +109627,13 @@ module \ldst0
     assign \reset_a $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
   wire width 1 \p_st_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
   wire width 1 \p_st_go$next
   process $group_7
     assign \p_st_go$next \p_st_go
-    assign \p_st_go$next \st__go
+    assign \p_st_go$next \st__go_i
     sync init
       update \p_st_go 1'0
     sync posedge \clk
@@ -109410,7 +109641,7 @@ module \ldst0
   end
   process $group_8
     assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \issue_i
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -109436,7 +109667,7 @@ module \ldst0
   end
   process $group_10
     assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \issue_i \issue_i \issue_i }
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
@@ -109465,15 +109696,15 @@ module \ldst0
     assign \alu_l_s_alu \reset_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
   wire width 1 \alu_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
   wire width 1 \alu_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268"
   wire width 1 \alu_valid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   cell $not $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109481,9 +109712,9 @@ module \ldst0
     connect \A \alu_valid
     connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   cell $and $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109494,11 +109725,11 @@ module \ldst0
     connect \B $15
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273"
   wire width 1 \rda_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   cell $not $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109506,9 +109737,9 @@ module \ldst0
     connect \A \rda_any
     connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:330"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
   cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109547,7 +109778,7 @@ module \ldst0
     assign \lod_l_s_lod \reset_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271"
   wire width 1 \ld_ok
   process $group_17
     assign \lod_l_r_lod 1'1
@@ -109556,16 +109787,16 @@ module \ldst0
   end
   process $group_18
     assign \wri_l_s_wri 1'0
-    assign \wri_l_s_wri \issue_i
+    assign \wri_l_s_wri \cu_issue_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:342"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
   wire width 2 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
-  wire width 1 \done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:342"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
   wire width 2 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:342"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
   cell $or $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109573,7 +109804,7 @@ module \ldst0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \reset_w
-    connect \B { \done_o \done_o }
+    connect \B { \cu_done_o \cu_done_o }
     connect \Y $24
   end
   connect $23 $24
@@ -109616,13 +109847,13 @@ module \ldst0
     sync posedge \clk
       update \upd_l_r_upd \upd_l_r_upd$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
   wire width 1 \addr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:264"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265"
   wire width 1 \op_is_st
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
   wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:349"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
   cell $and $27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109638,9 +109869,9 @@ module \ldst0
     assign \sto_l_s_sto $26
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351"
   wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351"
   cell $or $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -109657,13 +109888,57 @@ module \ldst0
     sync init
   end
   process $group_24
+    assign \lsd_l_s_lsd 1'0
+    assign \lsd_l_s_lsd \cu_issue_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  wire width 1 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  cell $or $31
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \reset_s
+    connect \B \p_st_go
+    connect \Y $30
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  cell $or $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $30
+    connect \B \ld_ok
+    connect \Y $32
+  end
+  process $group_25
+    assign \lsd_l_r_lsd$next \lsd_l_r_lsd
+    assign \lsd_l_r_lsd$next $32
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \lsd_l_r_lsd$next 1'1
+    end
+    sync init
+      update \lsd_l_r_lsd 1'1
+    sync posedge \clk
+      update \lsd_l_r_lsd \lsd_l_r_lsd$next
+  end
+  process $group_26
     assign \rst_l_s_rst 1'0
     assign \rst_l_s_rst \addr_ok
     sync init
   end
-  process $group_25
+  process $group_27
     assign \rst_l_r_rst 1'1
-    assign \rst_l_r_rst \issue_i
+    assign \rst_l_r_rst \cu_issue_i
     sync init
   end
   attribute \enum_base_type "MicrOp"
@@ -109739,38 +110014,38 @@ module \ldst0
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 4 \oper_r__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__sign_extend
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 2 \oper_r__ldst_mode
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -109829,16 +110104,16 @@ module \ldst0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 2 \oper_l__ldst_mode$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 87 $30
+  wire width 87 $34
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $31
+  cell $mux $35
     parameter \WIDTH 87
     connect \A { \oper_l__ldst_mode \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type }
-    connect \B { \oper_i__ldst_mode \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
-    connect \S \issue_i
-    connect \Y $30
+    connect \B { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type }
+    connect \S \cu_issue_i
+    connect \Y $34
   end
-  process $group_26
+  process $group_28
     assign \oper_r__insn_type 7'0000000
     assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \oper_r__imm_data__imm_ok 1'0
@@ -109853,10 +110128,10 @@ module \ldst0
     assign \oper_r__byte_reverse 1'0
     assign \oper_r__sign_extend 1'0
     assign \oper_r__ldst_mode 2'00
-    assign { \oper_r__ldst_mode \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $30
+    assign { \oper_r__ldst_mode \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $34
     sync init
   end
-  process $group_40
+  process $group_42
     assign \oper_l__insn_type$next \oper_l__insn_type
     assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
     assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
@@ -109872,10 +110147,10 @@ module \ldst0
     assign \oper_l__sign_extend$next \oper_l__sign_extend
     assign \oper_l__ldst_mode$next \oper_l__ldst_mode
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \issue_i }
+    switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__ldst_mode$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i__ldst_mode \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
+        assign { \oper_l__ldst_mode$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -109918,30 +110193,30 @@ module \ldst0
       update \oper_l__sign_extend \oper_l__sign_extend$next
       update \oper_l__ldst_mode \oper_l__ldst_mode$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:361"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366"
   wire width 64 \ldd_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279"
   wire width 64 \ldd_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \ldo_r
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \ldo_r$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $32
+  wire width 64 $36
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $33
+  cell $mux $37
     parameter \WIDTH 64
     connect \A \ldo_r
     connect \B \ldd_o
     connect \S \ld_ok
-    connect \Y $32
+    connect \Y $36
   end
-  process $group_54
+  process $group_56
     assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ldd_r $32
+    assign \ldd_r $36
     sync init
   end
-  process $group_55
+  process $group_57
     assign \ldo_r$next \ldo_r
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \ld_ok }
@@ -109954,28 +110229,28 @@ module \ldst0
     sync posedge \clk
       update \ldo_r \ldo_r$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
   wire width 64 \src_r0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \src_r0_l
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \src_r0_l$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $34
+  wire width 64 $38
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $35
+  cell $mux $39
     parameter \WIDTH 64
     connect \A \src_r0_l
     connect \B \src1_i
     connect \S \src_l_q_src [0]
-    connect \Y $34
+    connect \Y $38
   end
-  process $group_56
+  process $group_58
     assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src_r0 $34
+    assign \src_r0 $38
     sync init
   end
-  process $group_57
+  process $group_59
     assign \src_r0_l$next \src_r0_l
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \src_l_q_src [0] }
@@ -109988,28 +110263,28 @@ module \ldst0
     sync posedge \clk
       update \src_r0_l \src_r0_l$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
   wire width 64 \src_r1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \src_r1_l
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \src_r1_l$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $36
+  wire width 64 $40
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $37
+  cell $mux $41
     parameter \WIDTH 64
     connect \A \src_r1_l
     connect \B \src2_i
     connect \S \src_l_q_src [1]
-    connect \Y $36
+    connect \Y $40
   end
-  process $group_58
+  process $group_60
     assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src_r1 $36
+    assign \src_r1 $40
     sync init
   end
-  process $group_59
+  process $group_61
     assign \src_r1_l$next \src_r1_l
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \src_l_q_src [1] }
@@ -110022,28 +110297,28 @@ module \ldst0
     sync posedge \clk
       update \src_r1_l \src_r1_l$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
   wire width 64 \src_r2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \src_r2_l
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \src_r2_l$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $38
+  wire width 64 $42
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $39
+  cell $mux $43
     parameter \WIDTH 64
     connect \A \src_r2_l
     connect \B \src3_i
     connect \S \src_l_q_src [2]
-    connect \Y $38
+    connect \Y $42
   end
-  process $group_60
+  process $group_62
     assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src_r2 $38
+    assign \src_r2 $42
     sync init
   end
-  process $group_61
+  process $group_63
     assign \src_r2_l$next \src_r2_l
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \src_l_q_src [2] }
@@ -110056,32 +110331,32 @@ module \ldst0
     sync posedge \clk
       update \src_r2_l \src_r2_l$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
   wire width 64 \addr_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
   wire width 64 \alu_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
   wire width 64 \alu_o$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \ea_r
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
   wire width 64 \ea_r$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $40
+  wire width 64 $44
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $41
+  cell $mux $45
     parameter \WIDTH 64
     connect \A \ea_r
     connect \B \alu_o
     connect \S \alu_l_q_alu
-    connect \Y $40
+    connect \Y $44
   end
-  process $group_62
+  process $group_64
     assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \addr_r $40
+    assign \addr_r $44
     sync init
   end
-  process $group_63
+  process $group_65
     assign \ea_r$next \ea_r
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \alu_l_q_alu }
@@ -110094,46 +110369,46 @@ module \ldst0
     sync posedge \clk
       update \ea_r \ea_r$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:383"
   wire width 64 \src1_or_z
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379"
-  wire width 64 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379"
-  cell $mux $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
+  wire width 64 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
+  cell $mux $47
     parameter \WIDTH 64
     connect \A \src_r0
     connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
     connect \S \oper_r__zero_a
-    connect \Y $42
+    connect \Y $46
   end
-  process $group_64
+  process $group_66
     assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_or_z $42
+    assign \src1_or_z $46
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:383"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:388"
   wire width 64 \src2_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
-  wire width 64 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
-  cell $mux $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389"
+  wire width 64 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389"
+  cell $mux $49
     parameter \WIDTH 64
     connect \A \src_r1
     connect \B \oper_r__imm_data__imm
     connect \S \oper_r__imm_data__imm_ok
-    connect \Y $44
+    connect \Y $48
   end
-  process $group_65
+  process $group_67
     assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_or_imm $44
+    assign \src2_or_imm $48
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387"
-  wire width 65 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387"
-  wire width 65 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:387"
-  cell $add $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
+  wire width 65 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
+  wire width 65 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
+  cell $add $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -110141,18 +110416,18 @@ module \ldst0
     parameter \Y_WIDTH 65
     connect \A \src1_or_z
     connect \B \src2_or_imm
-    connect \Y $47
+    connect \Y $51
   end
-  connect $46 $47
-  process $group_66
+  connect $50 $51
+  process $group_68
     assign \alu_o$next \alu_o
-    assign \alu_o$next $46 [63:0]
+    assign \alu_o$next $50 [63:0]
     sync init
       update \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000
     sync posedge \clk
       update \alu_o \alu_o$next
   end
-  process $group_67
+  process $group_69
     assign \alu_ok$next \alu_ok
     assign \alu_ok$next \alu_valid
     sync init
@@ -110160,10 +110435,10 @@ module \ldst0
     sync posedge \clk
       update \alu_ok \alu_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391"
-  wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391"
-  cell $eq $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
+  wire width 1 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
+  cell $eq $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -110171,19 +110446,19 @@ module \ldst0
     parameter \Y_WIDTH 1
     connect \A \oper_r__insn_type
     connect \B 7'0100110
-    connect \Y $49
+    connect \Y $53
   end
-  process $group_68
+  process $group_70
     assign \op_is_st 1'0
-    assign \op_is_st $49
+    assign \op_is_st $53
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:263"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:264"
   wire width 1 \op_is_ld
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
-  wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
-  cell $eq $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397"
+  wire width 1 $55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397"
+  cell $eq $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -110191,295 +110466,264 @@ module \ldst0
     parameter \Y_WIDTH 1
     connect \A \oper_r__insn_type
     connect \B 7'0100101
-    connect \Y $51
+    connect \Y $55
   end
-  process $group_69
+  process $group_71
     assign \op_is_ld 1'0
-    assign \op_is_ld $51
+    assign \op_is_ld $55
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
-  wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
-  cell $and $54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
+  cell $and $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \op_is_ld
-    connect \B \ad__go
-    connect \Y $53
+    connect \B \ad__go_i
+    connect \Y $57
   end
-  process $group_70
+  process $group_72
     assign \load_mem_o 1'0
-    assign \load_mem_o $53
+    assign \load_mem_o $57
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
-  wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
-  cell $and $56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
+  cell $and $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \op_is_st
-    connect \B \st__go
-    connect \Y $55
+    connect \B \st__go_i
+    connect \Y $59
   end
-  process $group_71
+  process $group_73
     assign \stwd_mem_o 1'0
-    assign \stwd_mem_o $55
+    assign \stwd_mem_o $59
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:108"
   wire width 1 \ld_o
-  process $group_72
+  process $group_74
     assign \ld_o 1'0
     assign \ld_o \op_is_ld
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109"
   wire width 1 \st_o
-  process $group_73
+  process $group_75
     assign \st_o 1'0
     assign \st_o \op_is_st
     sync init
   end
-  process $group_74
-    assign \busy_o 1'0
-    assign \busy_o \opc_l_q_opc
+  process $group_76
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  wire width 3 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  cell $and $58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $and $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A \src_l_q_src
-    connect \B { \busy_o \busy_o \busy_o }
-    connect \Y $57
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
+    connect \Y $61
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  wire width 2 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  cell $not $60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 2 $63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $not $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a }
-    connect \Y $59
+    connect \Y $63
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  wire width 3 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  cell $and $62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $and $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 3
-    connect \A $57
-    connect \B $59
-    connect \Y $61
+    connect \A $61
+    connect \B $63
+    connect \Y $65
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  wire width 3 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  cell $not $64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $not $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \rdmaskn
-    connect \Y $63
+    connect \A \cu_rdmaskn_i
+    connect \Y $67
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  wire width 3 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
-  cell $and $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $and $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A $61
-    connect \B $63
-    connect \Y $65
+    connect \A $65
+    connect \B $67
+    connect \Y $69
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
-  wire width 1 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
-  cell $and $68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  wire width 1 $71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  cell $and $72
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \src_l_q_src [2]
-    connect \B \busy_o
-    connect \Y $67
+    connect \B \cu_busy_o
+    connect \Y $71
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
-  wire width 1 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
-  cell $and $70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  cell $and $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $67
+    connect \A $71
     connect \B \op_is_st
-    connect \Y $69
+    connect \Y $73
   end
-  process $group_75
-    assign \rd__rel 3'000
-    assign \rd__rel $65
-    assign \rd__rel [2] $69
+  process $group_77
+    assign \cu_rd__rel_o 3'000
+    assign \cu_rd__rel_o $69
+    assign \cu_rd__rel_o [2] $73
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414"
-  wire width 1 $71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414"
-  cell $or $72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+  wire width 1 $75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+  cell $or $76
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__go [0]
-    connect \B \rd__go [1]
-    connect \Y $71
+    connect \A \cu_rd__go_i [0]
+    connect \B \cu_rd__go_i [1]
+    connect \Y $75
   end
-  process $group_76
+  process $group_78
     assign \rda_any 1'0
-    assign \rda_any $71
+    assign \rda_any $75
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
-  wire width 1 $73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
-  wire width 1 $74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
-  cell $or $75
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \rd__rel [0]
-    connect \B \rd__rel [1]
-    connect \Y $74
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
-  cell $not $76
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $74
-    connect \Y $73
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
   wire width 1 $77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
-  cell $and $78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  wire width 1 $78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  cell $or $79
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \busy_o
-    connect \B $73
-    connect \Y $77
-  end
-  process $group_77
-    assign \alu_valid 1'0
-    assign \alu_valid $77
-    sync init
+    connect \A \cu_rd__rel_o [0]
+    connect \B \cu_rd__rel_o [1]
+    connect \Y $78
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273"
-  wire width 1 \rd_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
-  wire width 1 $79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
   cell $not $80
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel [2]
-    connect \Y $79
+    connect \A $78
+    connect \Y $77
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
   wire width 1 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
   cell $and $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_valid
-    connect \B $79
+    connect \A \cu_busy_o
+    connect \B $77
     connect \Y $81
   end
-  process $group_78
-    assign \rd_done 1'0
-    assign \rd_done $81
+  process $group_79
+    assign \alu_valid 1'0
+    assign \alu_valid $81
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274"
+  wire width 1 \rd_done
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
   wire width 1 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
-  cell $and $84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+  cell $not $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_valid
-    connect \B \adr_l_q_adr
+    connect \A \cu_rd__rel_o [2]
     connect \Y $83
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
   wire width 1 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
   cell $and $86
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $83
-    connect \B \busy_o
+    connect \A \alu_valid
+    connect \B $83
     connect \Y $85
   end
-  process $group_79
-    assign \ad__rel 1'0
-    assign \ad__rel $85
+  process $group_80
+    assign \rd_done 1'0
+    assign \rd_done $85
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
   wire width 1 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
   cell $and $88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \sto_l_q_sto
-    connect \B \busy_o
+    connect \A \alu_valid
+    connect \B \adr_l_q_adr
     connect \Y $87
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
   wire width 1 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
   cell $and $90
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -110487,25 +110731,30 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $87
-    connect \B \rd_done
+    connect \B \cu_busy_o
     connect \Y $89
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+  process $group_81
+    assign \ad__rel_o 1'0
+    assign \ad__rel_o $89
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
   wire width 1 $91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
   cell $and $92
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $89
-    connect \B \op_is_st
+    connect \A \sto_l_q_sto
+    connect \B \cu_busy_o
     connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
   wire width 1 $93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
   cell $and $94
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -110513,14 +110762,9 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $91
-    connect \B \shadown_i
+    connect \B \rd_done
     connect \Y $93
   end
-  process $group_80
-    assign \st__rel 1'0
-    assign \st__rel $93
-    sync init
-  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
   wire width 1 $95
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
@@ -110530,13 +110774,13 @@ module \ldst0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd_done
-    connect \B \wri_l_q_wri
+    connect \A $93
+    connect \B \op_is_st
     connect \Y $95
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
   wire width 1 $97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
   cell $and $98
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -110544,25 +110788,30 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $95
-    connect \B \busy_o
+    connect \B \cu_shadown_i
     connect \Y $97
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  process $group_82
+    assign \st__rel_o 1'0
+    assign \st__rel_o $97
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   wire width 1 $99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   cell $and $100
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $97
-    connect \B \lod_l_qn_lod
+    connect \A \rd_done
+    connect \B \wri_l_q_wri
     connect \Y $99
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   wire width 1 $101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   cell $and $102
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -110570,12 +110819,12 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $99
-    connect \B \op_is_ld
+    connect \B \cu_busy_o
     connect \Y $101
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   wire width 1 $103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   cell $and $104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -110583,205 +110832,231 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $101
-    connect \B \shadown_i
+    connect \B \lod_l_qn_lod
     connect \Y $103
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   wire width 1 $105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   cell $and $106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \upd_l_q_upd
-    connect \B \busy_o
+    connect \A $103
+    connect \B \op_is_ld
     connect \Y $105
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
   wire width 1 $107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
-  cell $eq $108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  cell $and $108
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \oper_r__ldst_mode
-    connect \B 2'01
+    connect \A $105
+    connect \B \cu_shadown_i
     connect \Y $107
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
   wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
   cell $and $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $105
-    connect \B $107
+    connect \A \upd_l_q_upd
+    connect \B \cu_busy_o
     connect \Y $109
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
   wire width 1 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
-  cell $and $112
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  cell $eq $112
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A $109
-    connect \B \alu_valid
+    connect \A \oper_r__ldst_mode
+    connect \B 2'01
     connect \Y $111
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:438"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
   wire width 1 $113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:438"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
   cell $and $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $111
-    connect \B \shadown_i
+    connect \A $109
+    connect \B $111
     connect \Y $113
   end
-  process $group_81
-    assign \wr__rel 2'00
-    assign \wr__rel [0] $103
-    assign \wr__rel [1] $113
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271"
-  wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
   wire width 1 $115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
-  cell $or $116
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  cell $and $116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \st__go
-    connect \B \p_st_go
+    connect \A $113
+    connect \B \alu_valid
     connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
   wire width 1 $117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
-  cell $or $118
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  cell $and $118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $115
-    connect \B \wr__go [0]
+    connect \B \cu_shadown_i
     connect \Y $117
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+  process $group_83
+    assign \cu_wr__rel_o 2'00
+    assign \cu_wr__rel_o [0] $107
+    assign \cu_wr__rel_o [1] $117
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272"
+  wire width 1 \wr_any
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
   wire width 1 $119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
   cell $or $120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $117
-    connect \B \wr__go [1]
+    connect \A \st__go_i
+    connect \B \p_st_go
     connect \Y $119
   end
-  process $group_82
-    assign \wr_any 1'0
-    assign \wr_any $119
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
   wire width 1 $121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $and $122
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  cell $or $122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rst_l_q_rst
-    connect \B \busy_o
+    connect \A $119
+    connect \B \cu_wr__go_i [0]
     connect \Y $121
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
   wire width 1 $123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $and $124
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  cell $or $124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $121
-    connect \B \shadown_i
+    connect \B \cu_wr__go_i [1]
     connect \Y $123
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  process $group_84
+    assign \wr_any 1'0
+    assign \wr_any $123
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
   wire width 1 $125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  wire width 1 $126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $or $127
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $and $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \st__rel
-    connect \B \wr__rel [0]
-    connect \Y $126
+    connect \A \rst_l_q_rst
+    connect \B \cu_busy_o
+    connect \Y $125
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  wire width 1 $128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $or $129
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $127
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $and $128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $126
-    connect \B \wr__rel [1]
-    connect \Y $128
+    connect \A $125
+    connect \B \cu_shadown_i
+    connect \Y $127
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $not $130
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $129
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $130
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $or $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $128
-    connect \Y $125
+    connect \A \st__rel_o
+    connect \B \cu_wr__rel_o [0]
+    connect \Y $130
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  wire width 1 $131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $and $132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $or $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $123
-    connect \B $125
-    connect \Y $131
+    connect \A $130
+    connect \B \cu_wr__rel_o [1]
+    connect \Y $132
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
-  wire width 1 $133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
-  cell $or $134
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $not $134
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $132
+    connect \Y $129
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $135
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $and $136
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $127
+    connect \B $129
+    connect \Y $135
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  wire width 1 $137
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  cell $or $138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -110789,59 +111064,59 @@ module \ldst0
     parameter \Y_WIDTH 1
     connect \A \lod_l_qn_lod
     connect \B \op_is_st
-    connect \Y $133
+    connect \Y $137
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
-  wire width 1 $135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
-  cell $and $136
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  wire width 1 $139
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  cell $and $140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $131
-    connect \B $133
-    connect \Y $135
+    connect \A $135
+    connect \B $137
+    connect \Y $139
   end
-  process $group_83
+  process $group_85
     assign \wr_reset 1'0
-    assign \wr_reset $135
+    assign \wr_reset $139
     sync init
   end
-  process $group_84
-    assign \done_o 1'0
-    assign \done_o \wr_reset
+  process $group_86
+    assign \cu_done_o 1'0
+    assign \cu_done_o \wr_reset
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 \dest1_o
-  process $group_85
+  process $group_87
     assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \o \dest1_o
     sync init
   end
-  process $group_86
+  process $group_88
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452"
-    switch { \wr__go [0] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
+    switch { \cu_wr__go_i [0] }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
       case 1'1
         assign \dest1_o \ldd_r
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 \dest2_o
-  process $group_87
+  process $group_89
     assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \ea \dest2_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
-  wire width 1 $137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
-  cell $eq $138
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  wire width 1 $141
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  cell $eq $142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -110849,39 +111124,39 @@ module \ldst0
     parameter \Y_WIDTH 1
     connect \A \oper_r__ldst_mode
     connect \B 2'01
-    connect \Y $137
+    connect \Y $141
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
-  wire width 1 $139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
-  cell $and $140
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
+  wire width 1 $143
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
+  cell $and $144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $137
-    connect \B \wr__go [1]
-    connect \Y $139
+    connect \A $141
+    connect \B \cu_wr__go_i [1]
+    connect \Y $143
   end
-  process $group_88
+  process $group_90
     assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
-    switch { $139 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
+    switch { $143 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
       case 1'1
         assign \dest2_o \addr_r
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
-  wire width 2 \wrmask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
-  wire width 3 $141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
-  wire width 1 $142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
-  cell $eq $143
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 2 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+  wire width 3 $145
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  wire width 1 $146
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  cell $eq $147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -110889,151 +111164,138 @@ module \ldst0
     parameter \Y_WIDTH 1
     connect \A \oper_r__ldst_mode
     connect \B 2'01
-    connect \Y $142
+    connect \Y $146
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
-  wire width 3 $144
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
-  cell $and $145
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+  wire width 3 $148
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+  cell $and $149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 3
-    connect \A { \busy_o \busy_o \busy_o }
-    connect \B { $142 \op_is_ld }
-    connect \Y $144
+    connect \A { \cu_busy_o \cu_busy_o \cu_busy_o }
+    connect \B { $146 \op_is_ld }
+    connect \Y $148
   end
-  connect $141 $144
-  process $group_89
-    assign \wrmask 2'00
-    assign \wrmask $141 [1:0]
+  connect $145 $148
+  process $group_91
+    assign \cu_wrmask_o 2'00
+    assign \cu_wrmask_o $145 [1:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
-  wire width 1 $146
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
-  cell $and $147
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476"
+  wire width 1 $150
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476"
+  cell $and $151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \op_is_ld
-    connect \B \busy_o
-    connect \Y $146
+    connect \B \cu_busy_o
+    connect \Y $150
   end
-  process $group_90
+  process $group_92
     assign \ldst_port0_is_ld_i 1'0
-    assign \ldst_port0_is_ld_i $146
+    assign \ldst_port0_is_ld_i $150
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:470"
-  wire width 1 $148
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:470"
-  cell $and $149
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477"
+  wire width 1 $152
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477"
+  cell $and $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \op_is_st
-    connect \B \busy_o
-    connect \Y $148
+    connect \B \cu_busy_o
+    connect \Y $152
   end
-  process $group_91
+  process $group_93
     assign \ldst_port0_is_st_i 1'0
-    assign \ldst_port0_is_st_i $148
+    assign \ldst_port0_is_st_i $152
     sync init
   end
-  process $group_92
+  process $group_94
     assign \ldst_port0_data_len 4'0000
-    assign \ldst_port0_data_len \oper_i__data_len
+    assign \ldst_port0_data_len \oper_i_ldst_ldst0__data_len
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
-  wire width 96 $150
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
-  cell $pos $151
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
+  wire width 96 $154
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
+  cell $pos $155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 96
     connect \A \addr_r
-    connect \Y $150
+    connect \Y $154
   end
-  process $group_93
+  process $group_95
     assign \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    assign \ldst_port0_addr_i $150
+    assign \ldst_port0_addr_i $154
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
-  wire width 1 $152
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
-  cell $or $153
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \lod_l_q_lod
-    connect \B \sto_l_q_sto
-    connect \Y $152
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
-  wire width 1 $154
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
-  cell $and $155
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
+  wire width 1 $156
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
+  cell $and $157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \alu_ok
-    connect \B $152
-    connect \Y $154
+    connect \B \lsd_l_q_lsd
+    connect \Y $156
   end
-  process $group_94
+  process $group_96
     assign \ldst_port0_addr_i_ok 1'0
-    assign \ldst_port0_addr_i_ok $154
+    assign \ldst_port0_addr_i_ok $156
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:106"
   wire width 1 \addr_exc_o
-  process $group_95
+  process $group_97
     assign \addr_exc_o 1'0
     assign \addr_exc_o \ldst_port0_addr_exc_o
     sync init
   end
-  process $group_96
+  process $group_98
     assign \addr_ok 1'0
     assign \addr_ok \ldst_port0_addr_ok_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
   wire width 64 \lddata_r
-  process $group_97
+  process $group_99
     assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
-    switch { \oper_i__byte_reverse }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
       case 1'1
         assign \ldd_o \ldst_port0_ld_data_o
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488"
       case
         assign \ldd_o \lddata_r
     end
     sync init
   end
-  process $group_98
+  process $group_100
     assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
-    switch { \oper_i__byte_reverse }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
       case 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488"
       case
         attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
-        switch \oper_i__data_len
+        switch \oper_i_ldst_ldst0__data_len
           attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
           case 4'0001
             assign \lddata_r [7:0] \ldst_port0_ld_data_o [7:0]
@@ -111061,36 +111323,36 @@ module \ldst0
     end
     sync init
   end
-  process $group_99
+  process $group_101
     assign \ld_ok 1'0
     assign \ld_ok \ldst_port0_ld_data_o_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
   wire width 64 \stdata_r
-  process $group_100
+  process $group_102
     assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
-    switch { \oper_i__byte_reverse }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:497"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:497"
       case 1'1
         assign \ldst_port0_st_data_i \src_r2
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499"
       case
         assign \ldst_port0_st_data_i \stdata_r
     end
     sync init
   end
-  process $group_101
+  process $group_103
     assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
-    switch { \oper_i__byte_reverse }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:497"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:497"
       case 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499"
       case
         attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
-        switch \oper_i__data_len
+        switch \oper_i_ldst_ldst0__data_len
           attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
           case 4'0001
             assign \stdata_r [7:0] \src_r2 [7:0]
@@ -111118,9 +111380,9 @@ module \ldst0
     end
     sync init
   end
-  process $group_102
+  process $group_104
     assign \ldst_port0_st_data_i_ok 1'0
-    assign \ldst_port0_st_data_i_ok \st__go
+    assign \ldst_port0_st_data_i_ok \st__go_i
     sync init
   end
 end
@@ -111128,13 +111390,13 @@ attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus"
 module \fus
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 0 \ad__go
+  wire width 1 input 0 \ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 1 \ad__rel
+  wire width 1 output 1 \ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 2 \st__go
+  wire width 1 input 2 \st__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 3 \st__rel
+  wire width 1 output 3 \st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 4 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
@@ -111212,8 +111474,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 6 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 6 \oper_i_alu_alu0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111226,50 +111488,50 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 7 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 8 \oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 9 \oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 10 \oper_i__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 11 \oper_i__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 12 \oper_i__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 13 \oper_i__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 14 \oper_i__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 15 \oper_i__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 16 \oper_i__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 17 \oper_i__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 7 \oper_i_alu_alu0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 8 \oper_i_alu_alu0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_alu_alu0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \oper_i_alu_alu0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_alu_alu0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_alu_alu0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_alu_alu0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_alu_alu0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_alu_alu0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \oper_i_alu_alu0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \oper_i_alu_alu0__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 18 \oper_i__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 19 \oper_i__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 20 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 21 \oper_i__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 22 \oper_i__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 23 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 24 \issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 18 \oper_i_alu_alu0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \oper_i_alu_alu0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \oper_i_alu_alu0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 21 \oper_i_alu_alu0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 22 \oper_i_alu_alu0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 23 \oper_i_alu_alu0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 25 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 input 26 \rdmaskn
+  wire width 1 input 24 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 25 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 26 \cu_rdmaskn_i
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111343,8 +111605,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 27 \oper_i__insn_type$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 27 \oper_i_alu_cr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111357,22 +111619,22 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 28 \oper_i__fn_unit$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 29 \oper_i__insn$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 30 \oper_i__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 31 \oper_i__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 32 \issue_i$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 28 \oper_i_alu_cr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 29 \oper_i_alu_cr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 30 \oper_i_alu_cr0__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 31 \oper_i_alu_cr0__write_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 33 \busy_o$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 6 input 34 \rdmaskn$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 35 \oper_i__cia
+  wire width 1 input 32 \cu_issue_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 33 \cu_busy_o$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 input 34 \cu_rdmaskn_i$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 35 \oper_i_alu_branch0__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111446,8 +111708,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 36 \oper_i__insn_type$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 36 \oper_i_alu_branch0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111460,24 +111722,24 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 37 \oper_i__fn_unit$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 38 \oper_i__insn$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 39 \oper_i__imm_data__imm$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 40 \oper_i__imm_data__imm_ok$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 41 \oper_i__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 42 \oper_i__is_32bit$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 43 \issue_i$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 37 \oper_i_alu_branch0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 38 \oper_i_alu_branch0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 39 \oper_i_alu_branch0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 40 \oper_i_alu_branch0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 41 \oper_i_alu_branch0__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 42 \oper_i_alu_branch0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 44 \busy_o$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 input 45 \rdmaskn$15
+  wire width 1 input 43 \cu_issue_i$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 44 \cu_busy_o$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 45 \cu_rdmaskn_i$6
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111551,8 +111813,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 46 \oper_i__insn_type$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 46 \oper_i_alu_trap0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111565,26 +111827,26 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 47 \oper_i__fn_unit$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 48 \oper_i__insn$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 49 \oper_i__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 50 \oper_i__cia$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 51 \oper_i__is_32bit$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 input 52 \oper_i__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 input 53 \oper_i__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 54 \issue_i$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 47 \oper_i_alu_trap0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 48 \oper_i_alu_trap0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 49 \oper_i_alu_trap0__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 50 \oper_i_alu_trap0__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 51 \oper_i_alu_trap0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 input 52 \oper_i_alu_trap0__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 input 53 \oper_i_alu_trap0__trapaddr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 55 \busy_o$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 input 56 \rdmaskn$23
+  wire width 1 input 54 \cu_issue_i$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 55 \cu_busy_o$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 56 \cu_rdmaskn_i$9
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111658,8 +111920,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 57 \oper_i__insn_type$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 57 \oper_i_alu_logical0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111672,50 +111934,50 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 58 \oper_i__fn_unit$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 59 \oper_i__imm_data__imm$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 60 \oper_i__imm_data__imm_ok$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 61 \oper_i__rc__rc$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 62 \oper_i__rc__rc_ok$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 63 \oper_i__oe__oe$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 64 \oper_i__oe__oe_ok$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 65 \oper_i__invert_a$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 66 \oper_i__zero_a$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 58 \oper_i_alu_logical0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 59 \oper_i_alu_logical0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 60 \oper_i_alu_logical0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 61 \oper_i_alu_logical0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 62 \oper_i_alu_logical0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 63 \oper_i_alu_logical0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 64 \oper_i_alu_logical0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 65 \oper_i_alu_logical0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 66 \oper_i_alu_logical0__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 67 \oper_i__input_carry$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 68 \oper_i__invert_out$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 69 \oper_i__write_cr0$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 70 \oper_i__output_carry$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 71 \oper_i__is_32bit$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 72 \oper_i__is_signed$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 73 \oper_i__data_len$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 74 \oper_i__insn$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 75 \issue_i$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 67 \oper_i_alu_logical0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 68 \oper_i_alu_logical0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 69 \oper_i_alu_logical0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 70 \oper_i_alu_logical0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 71 \oper_i_alu_logical0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 72 \oper_i_alu_logical0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 73 \oper_i_alu_logical0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 74 \oper_i_alu_logical0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 76 \busy_o$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 2 input 77 \rdmaskn$44
+  wire width 1 input 75 \cu_issue_i$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 76 \cu_busy_o$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 2 input 77 \cu_rdmaskn_i$12
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111789,8 +112051,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 78 \oper_i__insn_type$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 78 \oper_i_alu_spr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111803,18 +112065,18 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 79 \oper_i__fn_unit$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 80 \oper_i__insn$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 81 \oper_i__is_32bit$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 82 \issue_i$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 79 \oper_i_alu_spr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 80 \oper_i_alu_spr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 81 \oper_i_alu_spr0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 83 \busy_o$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 6 input 84 \rdmaskn$51
+  wire width 1 input 82 \cu_issue_i$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 83 \cu_busy_o$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 input 84 \cu_rdmaskn_i$15
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111888,8 +112150,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 85 \oper_i__insn_type$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 85 \oper_i_alu_mul0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111902,40 +112164,40 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 86 \oper_i__fn_unit$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 87 \oper_i__imm_data__imm$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 88 \oper_i__imm_data__imm_ok$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 89 \oper_i__rc__rc$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 90 \oper_i__rc__rc_ok$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 91 \oper_i__oe__oe$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 92 \oper_i__oe__oe_ok$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 93 \oper_i__invert_a$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 94 \oper_i__zero_a$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 95 \oper_i__invert_out$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 96 \oper_i__write_cr0$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 97 \oper_i__is_32bit$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 98 \oper_i__is_signed$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 99 \oper_i__insn$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 100 \issue_i$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 86 \oper_i_alu_mul0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 87 \oper_i_alu_mul0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 88 \oper_i_alu_mul0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 89 \oper_i_alu_mul0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 90 \oper_i_alu_mul0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 91 \oper_i_alu_mul0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 92 \oper_i_alu_mul0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 93 \oper_i_alu_mul0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 94 \oper_i_alu_mul0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 95 \oper_i_alu_mul0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 96 \oper_i_alu_mul0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 97 \oper_i_alu_mul0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 98 \oper_i_alu_mul0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 99 \oper_i_alu_mul0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 101 \busy_o$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 input 102 \rdmaskn$69
+  wire width 1 input 100 \cu_issue_i$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 101 \cu_busy_o$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 102 \cu_rdmaskn_i$18
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -112009,8 +112271,8 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 103 \oper_i__insn_type$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 103 \oper_i_alu_shift_rot0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -112023,44 +112285,44 @@ module \fus
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 input 104 \oper_i__fn_unit$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 105 \oper_i__imm_data__imm$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 106 \oper_i__imm_data__imm_ok$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 107 \oper_i__rc__rc$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 108 \oper_i__rc__rc_ok$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 109 \oper_i__oe__oe$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 110 \oper_i__oe__oe_ok$77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 104 \oper_i_alu_shift_rot0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 105 \oper_i_alu_shift_rot0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 106 \oper_i_alu_shift_rot0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 107 \oper_i_alu_shift_rot0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 108 \oper_i_alu_shift_rot0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 109 \oper_i_alu_shift_rot0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 110 \oper_i_alu_shift_rot0__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 112 \oper_i__input_carry$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 113 \oper_i__output_carry$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 114 \oper_i__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 115 \oper_i__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 116 \oper_i__is_32bit$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 117 \oper_i__is_signed$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 input 118 \oper_i__insn$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 119 \issue_i$83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 112 \oper_i_alu_shift_rot0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 113 \oper_i_alu_shift_rot0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 114 \oper_i_alu_shift_rot0__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 115 \oper_i_alu_shift_rot0__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 116 \oper_i_alu_shift_rot0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 117 \oper_i_alu_shift_rot0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 118 \oper_i_alu_shift_rot0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 120 \busy_o$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 input 121 \rdmaskn$85
+  wire width 1 input 119 \cu_issue_i$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 120 \cu_busy_o$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 121 \cu_rdmaskn_i$21
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -112134,709 +112396,709 @@ module \fus
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 input 122 \oper_i__insn_type$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 input 123 \oper_i__imm_data__imm$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 124 \oper_i__imm_data__imm_ok$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 125 \oper_i__zero_a$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 126 \oper_i__rc__rc$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 127 \oper_i__rc__rc_ok$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 128 \oper_i__oe__oe$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 129 \oper_i__oe__oe_ok$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 130 \oper_i__is_32bit$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 131 \oper_i__is_signed$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 input 132 \oper_i__data_len$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 133 \oper_i__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 input 134 \oper_i__sign_extend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 122 \oper_i_ldst_ldst0__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 123 \oper_i_ldst_ldst0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 124 \oper_i_ldst_ldst0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 125 \oper_i_ldst_ldst0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 126 \oper_i_ldst_ldst0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 127 \oper_i_ldst_ldst0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 128 \oper_i_ldst_ldst0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 129 \oper_i_ldst_ldst0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 130 \oper_i_ldst_ldst0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 131 \oper_i_ldst_ldst0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 132 \oper_i_ldst_ldst0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 133 \oper_i_ldst_ldst0__byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 134 \oper_i_ldst_ldst0__sign_extend
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 input 135 \oper_i__ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 input 136 \issue_i$97
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 135 \oper_i_ldst_ldst0__ldst_mode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 137 \busy_o$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 input 138 \rdmaskn$99
+  wire width 1 input 136 \cu_issue_i$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 137 \cu_busy_o$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 138 \cu_rdmaskn_i$24
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 139 \rd__rel
+  wire width 4 output 139 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 140 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 4 input 140 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 141 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 142 \rd__rel$100
+  wire width 6 output 142 \cu_rd__rel_o$25
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 143 \rd__go$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 144 \src1_i$102
+  wire width 6 input 143 \cu_rd__go_i$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 144 \src1_i$27
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 145 \rd__rel$103
+  wire width 4 output 145 \cu_rd__rel_o$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 146 \rd__go$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 147 \src1_i$105
+  wire width 4 input 146 \cu_rd__go_i$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 147 \src1_i$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 148 \rd__rel$106
+  wire width 2 output 148 \cu_rd__rel_o$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 input 149 \rd__go$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 150 \src1_i$108
+  wire width 2 input 149 \cu_rd__go_i$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 150 \src1_i$33
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 151 \rd__rel$109
+  wire width 6 output 151 \cu_rd__rel_o$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 152 \rd__go$110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 153 \src1_i$111
+  wire width 6 input 152 \cu_rd__go_i$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 153 \src1_i$36
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 154 \rd__rel$112
+  wire width 3 output 154 \cu_rd__rel_o$37
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 155 \rd__go$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 156 \src1_i$114
+  wire width 3 input 155 \cu_rd__go_i$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 156 \src1_i$39
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 157 \rd__rel$115
+  wire width 4 output 157 \cu_rd__rel_o$40
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 158 \rd__go$116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 159 \src1_i$117
+  wire width 4 input 158 \cu_rd__go_i$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 159 \src1_i$42
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 160 \rd__rel$118
+  wire width 3 output 160 \cu_rd__rel_o$43
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 161 \rd__go$119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 162 \src1_i$120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 3 input 161 \cu_rd__go_i$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 162 \src1_i$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 163 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 164 \src2_i$121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 165 \src2_i$122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 166 \src2_i$123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 167 \src2_i$124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 168 \src2_i$125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 169 \src2_i$126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 164 \src2_i$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 165 \src2_i$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 166 \src2_i$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 167 \src2_i$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 168 \src2_i$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 169 \src2_i$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 input 170 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 171 \src3_i$127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 1 input 172 \src3_i$128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 171 \src3_i$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 1 input 172 \src3_i$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 1 input 173 \src4_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 1 input 174 \src3_i$129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 2 input 175 \src4_i$130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 1 input 174 \src3_i$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 input 175 \src4_i$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 input 176 \src6_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 2 input 177 \src4_i$131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 input 177 \src4_i$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 input 178 \src5_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 32 input 179 \src3_i$132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 4 input 180 \src4_i$133
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 32 input 179 \src3_i$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 180 \src4_i$58
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 181 \rd__rel$134
+  wire width 3 output 181 \cu_rd__rel_o$59
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 182 \rd__go$135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 4 input 183 \src3_i$136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 4 input 184 \src5_i$137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 4 input 185 \src6_i$138
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 186 \src1_i$139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 187 \src3_i$140
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 188 \src3_i$141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 189 \src2_i$142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 190 \src4_i$143
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 input 191 \src2_i$144
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 3 input 182 \cu_rd__go_i$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 183 \src3_i$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 184 \src5_i$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 185 \src6_i$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 186 \src1_i$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 187 \src3_i$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 188 \src3_i$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 189 \src2_i$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 190 \src4_i$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 191 \src2_i$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 192 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 193 \wr__rel
+  wire width 5 output 193 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 input 194 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 195 \o_ok$145
+  wire width 5 input 194 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 195 \o_ok$70
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 196 \wr__rel$146
+  wire width 3 output 196 \cu_wr__rel_o$71
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 197 \wr__go$147
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 198 \o_ok$148
+  wire width 3 input 197 \cu_wr__go_i$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 198 \o_ok$73
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 199 \wr__rel$149
+  wire width 5 output 199 \cu_wr__rel_o$74
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 292 \go_die_i$222
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 275 \dest2_o$132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 276 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 277 \cu_shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 278 \cu_go_die_i$133
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 279 \cu_shadown_i$134
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 280 \cu_go_die_i$135
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 281 \cu_shadown_i$136
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 282 \cu_go_die_i$137
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 283 \cu_shadown_i$138
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 284 \cu_go_die_i$139
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 285 \cu_shadown_i$140
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 286 \cu_go_die_i$141
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 287 \cu_shadown_i$142
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 288 \cu_go_die_i$143
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 289 \cu_shadown_i$144
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 290 \cu_go_die_i$145
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 291 \cu_shadown_i$146
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 292 \cu_go_die_i$147
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
   wire width 1 output 293 \load_mem_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
   wire width 1 output 294 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 295 \shadown_i$223
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 295 \cu_shadown_i$148
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 296 \ldst_port0_is_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
   wire width 1 output 297 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 output 298 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 96 output 299 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 300 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 input 301 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 input 302 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 303 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 304 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 305 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 306 \ldst_port0_st_data_i_ok
   cell \alu0 \alu0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type
-    connect \oper_i__fn_unit \oper_i__fn_unit
-    connect \oper_i__imm_data__imm \oper_i__imm_data__imm
-    connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok
-    connect \oper_i__rc__rc \oper_i__rc__rc
-    connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok
-    connect \oper_i__oe__oe \oper_i__oe__oe
-    connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok
-    connect \oper_i__invert_a \oper_i__invert_a
-    connect \oper_i__zero_a \oper_i__zero_a
-    connect \oper_i__invert_out \oper_i__invert_out
-    connect \oper_i__write_cr0 \oper_i__write_cr0
-    connect \oper_i__input_carry \oper_i__input_carry
-    connect \oper_i__output_carry \oper_i__output_carry
-    connect \oper_i__is_32bit \oper_i__is_32bit
-    connect \oper_i__is_signed \oper_i__is_signed
-    connect \oper_i__data_len \oper_i__data_len
-    connect \oper_i__insn \oper_i__insn
-    connect \issue_i \issue_i
-    connect \busy_o \busy_o
-    connect \rdmaskn \rdmaskn
-    connect \rd__rel \rd__rel
-    connect \rd__go \rd__go
+    connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type
+    connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit
+    connect \oper_i_alu_alu0__imm_data__imm \oper_i_alu_alu0__imm_data__imm
+    connect \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm_ok
+    connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc
+    connect \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc_ok
+    connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe
+    connect \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe_ok
+    connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a
+    connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a
+    connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out
+    connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0
+    connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry
+    connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry
+    connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit
+    connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed
+    connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len
+    connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn
+    connect \cu_issue_i \cu_issue_i
+    connect \cu_busy_o \cu_busy_o
+    connect \cu_rdmaskn_i \cu_rdmaskn_i
+    connect \cu_rd__rel_o \cu_rd__rel_o
+    connect \cu_rd__go_i \cu_rd__go_i
     connect \src1_i \src1_i
     connect \src2_i \src2_i
-    connect \src3_i \src3_i$128
-    connect \src4_i \src4_i$130
+    connect \src3_i \src3_i$53
+    connect \src4_i \src4_i$55
     connect \o_ok \o_ok
-    connect \wr__rel \wr__rel
-    connect \wr__go \wr__go
+    connect \cu_wr__rel_o \cu_wr__rel_o
+    connect \cu_wr__go_i \cu_wr__go_i
     connect \dest1_o \dest1_o
     connect \cr_a_ok \cr_a_ok
-    connect \dest2_o \dest2_o$175
+    connect \dest2_o \dest2_o$100
     connect \xer_ca_ok \xer_ca_ok
-    connect \dest3_o \dest3_o$182
+    connect \dest3_o \dest3_o$107
     connect \xer_ov_ok \xer_ov_ok
     connect \dest4_o \dest4_o
     connect \xer_so_ok \xer_so_ok
-    connect \dest5_o \dest5_o$190
-    connect \go_die_i \go_die_i
-    connect \shadown_i \shadown_i
+    connect \dest5_o \dest5_o$115
+    connect \cu_go_die_i \cu_go_die_i
+    connect \cu_shadown_i \cu_shadown_i
   end
   cell \cr0 \cr0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type$1
-    connect \oper_i__fn_unit \oper_i__fn_unit$2
-    connect \oper_i__insn \oper_i__insn$3
-    connect \oper_i__read_cr_whole \oper_i__read_cr_whole
-    connect \oper_i__write_cr_whole \oper_i__write_cr_whole
-    connect \issue_i \issue_i$4
-    connect \busy_o \busy_o$5
-    connect \rdmaskn \rdmaskn$6
-    connect \rd__rel \rd__rel$100
-    connect \rd__go \rd__go$101
-    connect \src1_i \src1_i$102
-    connect \src2_i \src2_i$121
-    connect \src3_i \src3_i$132
-    connect \src4_i \src4_i$133
-    connect \src5_i \src5_i$137
-    connect \src6_i \src6_i$138
-    connect \o_ok \o_ok$145
-    connect \wr__rel \wr__rel$146
-    connect \wr__go \wr__go$147
-    connect \dest1_o \dest1_o$165
+    connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
+    connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
+    connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
+    connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole
+    connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole
+    connect \cu_issue_i \cu_issue_i$1
+    connect \cu_busy_o \cu_busy_o$2
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$3
+    connect \cu_rd__rel_o \cu_rd__rel_o$25
+    connect \cu_rd__go_i \cu_rd__go_i$26
+    connect \src1_i \src1_i$27
+    connect \src2_i \src2_i$46
+    connect \src3_i \src3_i$57
+    connect \src4_i \src4_i$58
+    connect \src5_i \src5_i$62
+    connect \src6_i \src6_i$63
+    connect \o_ok \o_ok$70
+    connect \cu_wr__rel_o \cu_wr__rel_o$71
+    connect \cu_wr__go_i \cu_wr__go_i$72
+    connect \dest1_o \dest1_o$90
     connect \full_cr_ok \full_cr_ok
     connect \dest2_o \dest2_o
-    connect \cr_a_ok \cr_a_ok$171
+    connect \cr_a_ok \cr_a_ok$96
     connect \dest3_o \dest3_o
-    connect \go_die_i \go_die_i$208
-    connect \shadown_i \shadown_i$209
+    connect \cu_go_die_i \cu_go_die_i$133
+    connect \cu_shadown_i \cu_shadown_i$134
   end
   cell \branch0 \branch0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__cia \oper_i__cia
-    connect \oper_i__insn_type \oper_i__insn_type$7
-    connect \oper_i__fn_unit \oper_i__fn_unit$8
-    connect \oper_i__insn \oper_i__insn$9
-    connect \oper_i__imm_data__imm \oper_i__imm_data__imm$10
-    connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$11
-    connect \oper_i__lk \oper_i__lk
-    connect \oper_i__is_32bit \oper_i__is_32bit$12
-    connect \issue_i \issue_i$13
-    connect \busy_o \busy_o$14
-    connect \rdmaskn \rdmaskn$15
-    connect \rd__rel \rd__rel$134
-    connect \rd__go \rd__go$135
-    connect \src3_i \src3_i$136
-    connect \src1_i \src1_i$139
-    connect \src2_i \src2_i$142
+    connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia
+    connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type
+    connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit
+    connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn
+    connect \oper_i_alu_branch0__imm_data__imm \oper_i_alu_branch0__imm_data__imm
+    connect \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm_ok
+    connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk
+    connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit
+    connect \cu_issue_i \cu_issue_i$4
+    connect \cu_busy_o \cu_busy_o$5
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$6
+    connect \cu_rd__rel_o \cu_rd__rel_o$59
+    connect \cu_rd__go_i \cu_rd__go_i$60
+    connect \src3_i \src3_i$61
+    connect \src1_i \src1_i$64
+    connect \src2_i \src2_i$67
     connect \fast1_ok \fast1_ok
-    connect \wr__rel \wr__rel$193
-    connect \wr__go \wr__go$194
-    connect \dest1_o \dest1_o$197
+    connect \cu_wr__rel_o \cu_wr__rel_o$118
+    connect \cu_wr__go_i \cu_wr__go_i$119
+    connect \dest1_o \dest1_o$122
     connect \fast2_ok \fast2_ok
-    connect \dest2_o \dest2_o$201
+    connect \dest2_o \dest2_o$126
     connect \nia_ok \nia_ok
-    connect \dest3_o \dest3_o$204
-    connect \go_die_i \go_die_i$210
-    connect \shadown_i \shadown_i$211
+    connect \dest3_o \dest3_o$129
+    connect \cu_go_die_i \cu_go_die_i$135
+    connect \cu_shadown_i \cu_shadown_i$136
   end
   cell \trap0 \trap0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type$16
-    connect \oper_i__fn_unit \oper_i__fn_unit$17
-    connect \oper_i__insn \oper_i__insn$18
-    connect \oper_i__msr \oper_i__msr
-    connect \oper_i__cia \oper_i__cia$19
-    connect \oper_i__is_32bit \oper_i__is_32bit$20
-    connect \oper_i__traptype \oper_i__traptype
-    connect \oper_i__trapaddr \oper_i__trapaddr
-    connect \issue_i \issue_i$21
-    connect \busy_o \busy_o$22
-    connect \rdmaskn \rdmaskn$23
-    connect \rd__rel \rd__rel$103
-    connect \rd__go \rd__go$104
-    connect \src1_i \src1_i$105
-    connect \src2_i \src2_i$122
-    connect \src3_i \src3_i$140
-    connect \src4_i \src4_i$143
-    connect \o_ok \o_ok$148
-    connect \wr__rel \wr__rel$149
-    connect \wr__go \wr__go$150
-    connect \dest1_o \dest1_o$166
-    connect \fast1_ok \fast1_ok$195
-    connect \dest2_o \dest2_o$198
-    connect \fast2_ok \fast2_ok$200
-    connect \dest3_o \dest3_o$202
-    connect \nia_ok \nia_ok$203
-    connect \dest4_o \dest4_o$205
+    connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type
+    connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit
+    connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn
+    connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
+    connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia
+    connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit
+    connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
+    connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
+    connect \cu_issue_i \cu_issue_i$7
+    connect \cu_busy_o \cu_busy_o$8
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$9
+    connect \cu_rd__rel_o \cu_rd__rel_o$28
+    connect \cu_rd__go_i \cu_rd__go_i$29
+    connect \src1_i \src1_i$30
+    connect \src2_i \src2_i$47
+    connect \src3_i \src3_i$65
+    connect \src4_i \src4_i$68
+    connect \o_ok \o_ok$73
+    connect \cu_wr__rel_o \cu_wr__rel_o$74
+    connect \cu_wr__go_i \cu_wr__go_i$75
+    connect \dest1_o \dest1_o$91
+    connect \fast1_ok \fast1_ok$120
+    connect \dest2_o \dest2_o$123
+    connect \fast2_ok \fast2_ok$125
+    connect \dest3_o \dest3_o$127
+    connect \nia_ok \nia_ok$128
+    connect \dest4_o \dest4_o$130
     connect \msr_ok \msr_ok
-    connect \dest5_o \dest5_o$206
-    connect \go_die_i \go_die_i$212
-    connect \shadown_i \shadown_i$213
+    connect \dest5_o \dest5_o$131
+    connect \cu_go_die_i \cu_go_die_i$137
+    connect \cu_shadown_i \cu_shadown_i$138
   end
   cell \logical0 \logical0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type$24
-    connect \oper_i__fn_unit \oper_i__fn_unit$25
-    connect \oper_i__imm_data__imm \oper_i__imm_data__imm$26
-    connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$27
-    connect \oper_i__rc__rc \oper_i__rc__rc$28
-    connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$29
-    connect \oper_i__oe__oe \oper_i__oe__oe$30
-    connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$31
-    connect \oper_i__invert_a \oper_i__invert_a$32
-    connect \oper_i__zero_a \oper_i__zero_a$33
-    connect \oper_i__input_carry \oper_i__input_carry$34
-    connect \oper_i__invert_out \oper_i__invert_out$35
-    connect \oper_i__write_cr0 \oper_i__write_cr0$36
-    connect \oper_i__output_carry \oper_i__output_carry$37
-    connect \oper_i__is_32bit \oper_i__is_32bit$38
-    connect \oper_i__is_signed \oper_i__is_signed$39
-    connect \oper_i__data_len \oper_i__data_len$40
-    connect \oper_i__insn \oper_i__insn$41
-    connect \issue_i \issue_i$42
-    connect \busy_o \busy_o$43
-    connect \rdmaskn \rdmaskn$44
-    connect \rd__rel \rd__rel$106
-    connect \rd__go \rd__go$107
-    connect \src1_i \src1_i$108
-    connect \src2_i \src2_i$123
-    connect \o_ok \o_ok$151
-    connect \wr__rel \wr__rel$152
-    connect \wr__go \wr__go$153
-    connect \dest1_o \dest1_o$167
-    connect \cr_a_ok \cr_a_ok$172
-    connect \dest2_o \dest2_o$176
-    connect \xer_ca_ok \xer_ca_ok$179
-    connect \dest3_o \dest3_o$183
-    connect \go_die_i \go_die_i$214
-    connect \shadown_i \shadown_i$215
+    connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type
+    connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit
+    connect \oper_i_alu_logical0__imm_data__imm \oper_i_alu_logical0__imm_data__imm
+    connect \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm_ok
+    connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc
+    connect \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc_ok
+    connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe
+    connect \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe_ok
+    connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a
+    connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
+    connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry
+    connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out
+    connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
+    connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry
+    connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit
+    connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed
+    connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len
+    connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn
+    connect \cu_issue_i \cu_issue_i$10
+    connect \cu_busy_o \cu_busy_o$11
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$12
+    connect \cu_rd__rel_o \cu_rd__rel_o$31
+    connect \cu_rd__go_i \cu_rd__go_i$32
+    connect \src1_i \src1_i$33
+    connect \src2_i \src2_i$48
+    connect \o_ok \o_ok$76
+    connect \cu_wr__rel_o \cu_wr__rel_o$77
+    connect \cu_wr__go_i \cu_wr__go_i$78
+    connect \dest1_o \dest1_o$92
+    connect \cr_a_ok \cr_a_ok$97
+    connect \dest2_o \dest2_o$101
+    connect \xer_ca_ok \xer_ca_ok$104
+    connect \dest3_o \dest3_o$108
+    connect \cu_go_die_i \cu_go_die_i$139
+    connect \cu_shadown_i \cu_shadown_i$140
   end
   cell \spr0 \spr0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type$45
-    connect \oper_i__fn_unit \oper_i__fn_unit$46
-    connect \oper_i__insn \oper_i__insn$47
-    connect \oper_i__is_32bit \oper_i__is_32bit$48
-    connect \issue_i \issue_i$49
-    connect \busy_o \busy_o$50
-    connect \rdmaskn \rdmaskn$51
-    connect \rd__rel \rd__rel$109
-    connect \rd__go \rd__go$110
-    connect \src1_i \src1_i$111
+    connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
+    connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit
+    connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn
+    connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
+    connect \cu_issue_i \cu_issue_i$13
+    connect \cu_busy_o \cu_busy_o$14
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$15
+    connect \cu_rd__rel_o \cu_rd__rel_o$34
+    connect \cu_rd__go_i \cu_rd__go_i$35
+    connect \src1_i \src1_i$36
     connect \src4_i \src4_i
     connect \src6_i \src6_i
     connect \src5_i \src5_i
-    connect \src3_i \src3_i$141
-    connect \src2_i \src2_i$144
-    connect \o_ok \o_ok$154
-    connect \wr__rel \wr__rel$155
-    connect \wr__go \wr__go$156
-    connect \dest1_o \dest1_o$168
-    connect \xer_ca_ok \xer_ca_ok$180
+    connect \src3_i \src3_i$66
+    connect \src2_i \src2_i$69
+    connect \o_ok \o_ok$79
+    connect \cu_wr__rel_o \cu_wr__rel_o$80
+    connect \cu_wr__go_i \cu_wr__go_i$81
+    connect \dest1_o \dest1_o$93
+    connect \xer_ca_ok \xer_ca_ok$105
     connect \dest6_o \dest6_o
-    connect \xer_ov_ok \xer_ov_ok$185
+    connect \xer_ov_ok \xer_ov_ok$110
     connect \dest5_o \dest5_o
-    connect \xer_so_ok \xer_so_ok$188
-    connect \dest4_o \dest4_o$191
-    connect \fast1_ok \fast1_ok$196
-    connect \dest3_o \dest3_o$199
+    connect \xer_so_ok \xer_so_ok$113
+    connect \dest4_o \dest4_o$116
+    connect \fast1_ok \fast1_ok$121
+    connect \dest3_o \dest3_o$124
     connect \spr1_ok \spr1_ok
-    connect \dest2_o \dest2_o$207
-    connect \go_die_i \go_die_i$216
-    connect \shadown_i \shadown_i$217
+    connect \dest2_o \dest2_o$132
+    connect \cu_go_die_i \cu_go_die_i$141
+    connect \cu_shadown_i \cu_shadown_i$142
   end
   cell \mul0 \mul0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type$52
-    connect \oper_i__fn_unit \oper_i__fn_unit$53
-    connect \oper_i__imm_data__imm \oper_i__imm_data__imm$54
-    connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$55
-    connect \oper_i__rc__rc \oper_i__rc__rc$56
-    connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$57
-    connect \oper_i__oe__oe \oper_i__oe__oe$58
-    connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$59
-    connect \oper_i__invert_a \oper_i__invert_a$60
-    connect \oper_i__zero_a \oper_i__zero_a$61
-    connect \oper_i__invert_out \oper_i__invert_out$62
-    connect \oper_i__write_cr0 \oper_i__write_cr0$63
-    connect \oper_i__is_32bit \oper_i__is_32bit$64
-    connect \oper_i__is_signed \oper_i__is_signed$65
-    connect \oper_i__insn \oper_i__insn$66
-    connect \issue_i \issue_i$67
-    connect \busy_o \busy_o$68
-    connect \rdmaskn \rdmaskn$69
-    connect \rd__rel \rd__rel$112
-    connect \rd__go \rd__go$113
-    connect \src1_i \src1_i$114
-    connect \src2_i \src2_i$124
-    connect \src3_i \src3_i$129
-    connect \o_ok \o_ok$157
-    connect \wr__rel \wr__rel$158
-    connect \wr__go \wr__go$159
-    connect \dest1_o \dest1_o$169
-    connect \cr_a_ok \cr_a_ok$173
-    connect \dest2_o \dest2_o$177
-    connect \xer_ov_ok \xer_ov_ok$186
-    connect \dest3_o \dest3_o$187
-    connect \xer_so_ok \xer_so_ok$189
-    connect \dest4_o \dest4_o$192
-    connect \go_die_i \go_die_i$218
-    connect \shadown_i \shadown_i$219
+    connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type
+    connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit
+    connect \oper_i_alu_mul0__imm_data__imm \oper_i_alu_mul0__imm_data__imm
+    connect \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm_ok
+    connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc
+    connect \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc_ok
+    connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe
+    connect \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe_ok
+    connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a
+    connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a
+    connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out
+    connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
+    connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit
+    connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed
+    connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn
+    connect \cu_issue_i \cu_issue_i$16
+    connect \cu_busy_o \cu_busy_o$17
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$18
+    connect \cu_rd__rel_o \cu_rd__rel_o$37
+    connect \cu_rd__go_i \cu_rd__go_i$38
+    connect \src1_i \src1_i$39
+    connect \src2_i \src2_i$49
+    connect \src3_i \src3_i$54
+    connect \o_ok \o_ok$82
+    connect \cu_wr__rel_o \cu_wr__rel_o$83
+    connect \cu_wr__go_i \cu_wr__go_i$84
+    connect \dest1_o \dest1_o$94
+    connect \cr_a_ok \cr_a_ok$98
+    connect \dest2_o \dest2_o$102
+    connect \xer_ov_ok \xer_ov_ok$111
+    connect \dest3_o \dest3_o$112
+    connect \xer_so_ok \xer_so_ok$114
+    connect \dest4_o \dest4_o$117
+    connect \cu_go_die_i \cu_go_die_i$143
+    connect \cu_shadown_i \cu_shadown_i$144
   end
   cell \shiftrot0 \shiftrot0
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type$70
-    connect \oper_i__fn_unit \oper_i__fn_unit$71
-    connect \oper_i__imm_data__imm \oper_i__imm_data__imm$72
-    connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$73
-    connect \oper_i__rc__rc \oper_i__rc__rc$74
-    connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$75
-    connect \oper_i__oe__oe \oper_i__oe__oe$76
-    connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$77
-    connect \oper_i__input_carry \oper_i__input_carry$78
-    connect \oper_i__output_carry \oper_i__output_carry$79
-    connect \oper_i__input_cr \oper_i__input_cr
-    connect \oper_i__output_cr \oper_i__output_cr
-    connect \oper_i__is_32bit \oper_i__is_32bit$80
-    connect \oper_i__is_signed \oper_i__is_signed$81
-    connect \oper_i__insn \oper_i__insn$82
-    connect \issue_i \issue_i$83
-    connect \busy_o \busy_o$84
-    connect \rdmaskn \rdmaskn$85
-    connect \rd__rel \rd__rel$115
-    connect \rd__go \rd__go$116
-    connect \src1_i \src1_i$117
-    connect \src2_i \src2_i$125
+    connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type
+    connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit
+    connect \oper_i_alu_shift_rot0__imm_data__imm \oper_i_alu_shift_rot0__imm_data__imm
+    connect \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm_ok
+    connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc
+    connect \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc_ok
+    connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe
+    connect \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe_ok
+    connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry
+    connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry
+    connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr
+    connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr
+    connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit
+    connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed
+    connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn
+    connect \cu_issue_i \cu_issue_i$19
+    connect \cu_busy_o \cu_busy_o$20
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$21
+    connect \cu_rd__rel_o \cu_rd__rel_o$40
+    connect \cu_rd__go_i \cu_rd__go_i$41
+    connect \src1_i \src1_i$42
+    connect \src2_i \src2_i$50
     connect \src3_i \src3_i
-    connect \src4_i \src4_i$131
-    connect \o_ok \o_ok$160
-    connect \wr__rel \wr__rel$161
-    connect \wr__go \wr__go$162
-    connect \dest1_o \dest1_o$170
-    connect \cr_a_ok \cr_a_ok$174
-    connect \dest2_o \dest2_o$178
-    connect \xer_ca_ok \xer_ca_ok$181
-    connect \dest3_o \dest3_o$184
-    connect \go_die_i \go_die_i$220
-    connect \shadown_i \shadown_i$221
+    connect \src4_i \src4_i$56
+    connect \o_ok \o_ok$85
+    connect \cu_wr__rel_o \cu_wr__rel_o$86
+    connect \cu_wr__go_i \cu_wr__go_i$87
+    connect \dest1_o \dest1_o$95
+    connect \cr_a_ok \cr_a_ok$99
+    connect \dest2_o \dest2_o$103
+    connect \xer_ca_ok \xer_ca_ok$106
+    connect \dest3_o \dest3_o$109
+    connect \cu_go_die_i \cu_go_die_i$145
+    connect \cu_shadown_i \cu_shadown_i$146
   end
   cell \ldst0 \ldst0
-    connect \ad__go \ad__go
-    connect \ad__rel \ad__rel
-    connect \st__go \st__go
-    connect \st__rel \st__rel
+    connect \ad__go_i \ad__go_i
+    connect \ad__rel_o \ad__rel_o
+    connect \st__go_i \st__go_i
+    connect \st__rel_o \st__rel_o
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i__insn_type \oper_i__insn_type$86
-    connect \oper_i__imm_data__imm \oper_i__imm_data__imm$87
-    connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$88
-    connect \oper_i__zero_a \oper_i__zero_a$89
-    connect \oper_i__rc__rc \oper_i__rc__rc$90
-    connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$91
-    connect \oper_i__oe__oe \oper_i__oe__oe$92
-    connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$93
-    connect \oper_i__is_32bit \oper_i__is_32bit$94
-    connect \oper_i__is_signed \oper_i__is_signed$95
-    connect \oper_i__data_len \oper_i__data_len$96
-    connect \oper_i__byte_reverse \oper_i__byte_reverse
-    connect \oper_i__sign_extend \oper_i__sign_extend
-    connect \oper_i__ldst_mode \oper_i__ldst_mode
-    connect \issue_i \issue_i$97
-    connect \busy_o \busy_o$98
-    connect \rdmaskn \rdmaskn$99
-    connect \rd__rel \rd__rel$118
-    connect \rd__go \rd__go$119
-    connect \src1_i \src1_i$120
-    connect \src2_i \src2_i$126
-    connect \src3_i \src3_i$127
-    connect \wr__rel \wr__rel$163
-    connect \wr__go \wr__go$164
+    connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
+    connect \oper_i_ldst_ldst0__imm_data__imm \oper_i_ldst_ldst0__imm_data__imm
+    connect \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm_ok
+    connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
+    connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc
+    connect \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc_ok
+    connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe
+    connect \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe_ok
+    connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit
+    connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed
+    connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len
+    connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse
+    connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
+    connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode
+    connect \cu_issue_i \cu_issue_i$22
+    connect \cu_busy_o \cu_busy_o$23
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$24
+    connect \cu_rd__rel_o \cu_rd__rel_o$43
+    connect \cu_rd__go_i \cu_rd__go_i$44
+    connect \src1_i \src1_i$45
+    connect \src2_i \src2_i$51
+    connect \src3_i \src3_i$52
+    connect \cu_wr__rel_o \cu_wr__rel_o$88
+    connect \cu_wr__go_i \cu_wr__go_i$89
     connect \o \o
     connect \ea \ea
-    connect \go_die_i \go_die_i$222
+    connect \cu_go_die_i \cu_go_die_i$147
     connect \load_mem_o \load_mem_o
     connect \stwd_mem_o \stwd_mem_o
-    connect \shadown_i \shadown_i$223
+    connect \cu_shadown_i \cu_shadown_i$148
     connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
     connect \ldst_port0_is_st_i \ldst_port0_is_st_i
     connect \ldst_port0_data_len \ldst_port0_data_len
@@ -113651,21 +113913,21 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp"
 module \lenexp
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:129"
-  wire width 4 input 0 \len_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
-  wire width 4 input 1 \addr_i
+  wire width 4 input 0 \len_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
+  wire width 4 input 1 \addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132"
   wire width 64 output 2 \lexp_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
   wire width 176 output 3 \rexp_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148"
   wire width 17 \binlen
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
   wire width 21 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
   wire width 20 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
   cell $sshl $3
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -113676,9 +113938,9 @@ module \lenexp
     connect \B \len_i
     connect \Y $2
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
   wire width 21 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:149"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
   cell $sub $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 20
@@ -113695,11 +113957,11 @@ module \lenexp
     assign \binlen $1 [16:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
   wire width 64 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
   wire width 32 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
   cell $sshl $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 17
@@ -113710,7 +113972,7 @@ module \lenexp
     connect \B \addr_i
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
   cell $pos $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 32
@@ -113889,9 +114151,9 @@ module \pimem
   wire width 1 input 4 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 input 5 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 48 input 6 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 7 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
   wire width 8 output 8 \x_mask_i
@@ -113901,15 +114163,15 @@ module \pimem
   wire width 1 output 10 \ldst_port0_addr_ok_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
   wire width 64 input 11 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 12 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 13 \ldst_port0_ld_data_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
   wire width 1 input 14 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 15 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 16 \ldst_port0_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
   wire width 64 output 17 \x_st_data_i
@@ -114006,13 +114268,13 @@ module \pimem
     connect \r_cyc \cyc_l_r_cyc
     connect \q_cyc \cyc_l_q_cyc
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:129"
-  wire width 4 \lenexp_len_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
-  wire width 4 \lenexp_addr_i
+  wire width 4 \lenexp_len_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
+  wire width 4 \lenexp_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132"
   wire width 64 \lenexp_lexp_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:133"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
   wire width 176 \lenexp_rexp_o
   cell \lenexp \lenexp
     connect \len_i \lenexp_len_i
@@ -115088,21 +115350,21 @@ module \l0$106
   wire width 1 input 3 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 input 4 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 96 input 5 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 6 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 output 7 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 output 8 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 9 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 10 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 11 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 12 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 13 \ldst_port0_is_ld_i$1
@@ -115112,19 +115374,19 @@ module \l0$106
   wire width 1 output 15 \ldst_port0_is_st_i$2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 output 16 \ldst_port0_data_len$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 48 output 17 \ldst_port0_addr_i$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 18 \ldst_port0_addr_i_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 input 19 \ldst_port0_addr_ok_o$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 20 \ldst_port0_ld_data_o$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 21 \ldst_port0_ld_data_o_ok$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 22 \ldst_port0_st_data_i_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 23 \ldst_port0_st_data_i$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 input 24 \ldst_port0_addr_exc_o$11
@@ -115171,9 +115433,9 @@ module \l0$106
     connect \o \pick_o
     connect \n \pick_n
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:222"
   wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:221"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:222"
   cell $or $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115229,9 +115491,9 @@ module \l0$106
     sync posedge \clk
       update \idx_l$17 \idx_l$17$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
   wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
   cell $not $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115241,17 +115503,17 @@ module \l0$106
   end
   process $group_3
     assign \idx_l_s_idx_l 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
     switch { $20 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:237"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
       case 1'1
         assign \idx_l_s_idx_l 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
   wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
   cell $not $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115262,13 +115524,13 @@ module \l0$106
   process $group_4
     assign \reset_l_s_reset 1'0
     assign \reset_l_s_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
         switch { $22 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:247"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
           case 1'1
             assign \reset_l_s_reset 1'1
         end
@@ -115278,9 +115540,9 @@ module \l0$106
   process $group_5
     assign \reset_l_r_reset 1'1
     assign \reset_l_r_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
     switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
       case 1'1
         assign \reset_l_r_reset 1'1
     end
@@ -115288,9 +115550,9 @@ module \l0$106
   end
   process $group_6
     assign \ldst_port0_is_ld_i$1 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:115"
         switch { }
@@ -115302,9 +115564,9 @@ module \l0$106
   end
   process $group_7
     assign \ldst_port0_is_st_i$2 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:116"
         switch { }
@@ -115316,9 +115578,9 @@ module \l0$106
   end
   process $group_8
     assign \ldst_port0_data_len$3 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:117"
         switch { }
@@ -115330,9 +115592,9 @@ module \l0$106
   end
   process $group_9
     assign \ldst_port0_go_die_i 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118"
         switch { }
@@ -115349,9 +115611,9 @@ module \l0$106
   connect $25 \ldst_port0_addr_i
   process $group_10
     assign \ldst_port0_addr_i$4 48'000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
         switch { }
@@ -115363,9 +115625,9 @@ module \l0$106
   end
   process $group_11
     assign \ldst_port0_addr_i_ok$5 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120"
         switch { }
@@ -115378,9 +115640,9 @@ module \l0$106
   process $group_12
     assign \ldst_port0_st_data_i$10 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \ldst_port0_st_data_i_ok$9 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:121"
         switch { }
@@ -115393,9 +115655,9 @@ module \l0$106
   process $group_14
     assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \ldst_port0_ld_data_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122"
         switch { }
@@ -115407,9 +115669,9 @@ module \l0$106
   end
   process $group_16
     assign \ldst_port0_busy_o$13 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123"
         switch { }
@@ -115421,9 +115683,9 @@ module \l0$106
   end
   process $group_17
     assign \ldst_port0_addr_ok_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:124"
         switch { }
@@ -115435,9 +115697,9 @@ module \l0$106
   end
   process $group_18
     assign \ldst_port0_addr_exc_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:245"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:125"
         switch { }
@@ -115447,9 +115709,9 @@ module \l0$106
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:251"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:252"
   wire width 1 \reset_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:251"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:252"
   wire width 1 \reset_delay$next
   process $group_19
     assign \reset_delay$next \reset_delay
@@ -115461,9 +115723,9 @@ module \l0$106
   end
   process $group_20
     assign \idx_l_r_idx_l 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
     switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:255"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
       case 1'1
         assign \idx_l_r_idx_l 1'1
     end
@@ -115539,15 +115801,15 @@ module \lsmem
   wire width 1 output 23 \m_store_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
   wire width 1 \m_store_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
   wire width 45 output 24 \m_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
   wire width 45 \m_badaddr_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
   wire width 1 output 25 \m_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $or $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115558,9 +115820,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115571,9 +115833,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115581,9 +115843,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115594,9 +115856,9 @@ module \lsmem
     connect \B $5
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115607,9 +115869,9 @@ module \lsmem
     connect \B \dbus__err
     connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115617,9 +115879,9 @@ module \lsmem
     connect \A \m_valid_i
     connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $or $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115632,20 +115894,20 @@ module \lsmem
   end
   process $group_0
     assign \dbus__cyc$next \dbus__cyc
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $7 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
         switch { $13 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
           case 1'1
             assign \dbus__cyc$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
       case 2'1-
         assign \dbus__cyc$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
       case
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -115658,9 +115920,9 @@ module \lsmem
     sync posedge \clk
       update \dbus__cyc \dbus__cyc$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115671,9 +115933,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115684,9 +115946,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115694,9 +115956,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115707,9 +115969,9 @@ module \lsmem
     connect \B $19
     connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $or $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115720,9 +115982,9 @@ module \lsmem
     connect \B \dbus__err
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115730,9 +115992,9 @@ module \lsmem
     connect \A \m_valid_i
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $or $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115745,20 +116007,20 @@ module \lsmem
   end
   process $group_1
     assign \dbus__stb$next \dbus__stb
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $21 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
         switch { $27 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
           case 1'1
             assign \dbus__stb$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
       case 2'1-
         assign \dbus__stb$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
       case
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -115771,9 +116033,9 @@ module \lsmem
     sync posedge \clk
       update \dbus__stb \dbus__stb$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $or $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115784,9 +116046,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $29
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115797,9 +116059,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115807,9 +116069,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115820,9 +116082,9 @@ module \lsmem
     connect \B $33
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $or $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115833,9 +116095,9 @@ module \lsmem
     connect \B \dbus__err
     connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115843,9 +116105,9 @@ module \lsmem
     connect \A \m_valid_i
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
   cell $or $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115858,19 +116120,19 @@ module \lsmem
   end
   process $group_2
     assign \m_ld_data_o$next \m_ld_data_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $35 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
         switch { $41 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
           case 1'1
             assign \m_ld_data_o$next \dbus__dat_r
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
       case 2'1-
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
       case
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -115883,9 +116145,9 @@ module \lsmem
     sync posedge \clk
       update \m_ld_data_o \m_ld_data_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $or $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115896,9 +116158,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115909,9 +116171,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115919,9 +116181,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115934,14 +116196,14 @@ module \lsmem
   end
   process $group_3
     assign \dbus__adr$next \dbus__adr
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $49 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
       case 2'1-
         assign \dbus__adr$next \x_addr_i [47:3]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
       case
         assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
     end
@@ -115955,9 +116217,9 @@ module \lsmem
     sync posedge \clk
       update \dbus__adr \dbus__adr$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $or $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115968,9 +116230,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115981,9 +116243,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -115991,9 +116253,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $55
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116006,14 +116268,14 @@ module \lsmem
   end
   process $group_4
     assign \dbus__sel$next \dbus__sel
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $57 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
       case 2'1-
         assign \dbus__sel$next \x_mask_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
       case
         assign \dbus__sel$next 8'00000000
         assign \dbus__sel$next 8'00000000
@@ -116028,9 +116290,9 @@ module \lsmem
     sync posedge \clk
       update \dbus__sel \dbus__sel$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $or $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116041,9 +116303,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $59
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $62
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116054,9 +116316,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $61
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $64
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116064,9 +116326,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $63
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $66
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116079,14 +116341,14 @@ module \lsmem
   end
   process $group_5
     assign \dbus__we$next \dbus__we
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $65 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
       case 2'1-
         assign \dbus__we$next \x_st_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
       case
         assign \dbus__we$next 1'0
     end
@@ -116100,9 +116362,9 @@ module \lsmem
     sync posedge \clk
       update \dbus__we \dbus__we$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $or $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116113,9 +116375,9 @@ module \lsmem
     connect \B \x_st_i
     connect \Y $67
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116126,9 +116388,9 @@ module \lsmem
     connect \B \x_valid_i
     connect \Y $69
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $not $72
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116136,9 +116398,9 @@ module \lsmem
     connect \A \x_stall_i
     connect \Y $71
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   wire width 1 $73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
   cell $and $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116151,14 +116413,14 @@ module \lsmem
   end
   process $group_6
     assign \dbus__dat_w$next \dbus__dat_w
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
     switch { $73 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:82"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:90"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
       case 2'1-
         assign \dbus__dat_w$next \x_st_data_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
       case
         assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
@@ -116172,9 +116434,9 @@ module \lsmem
     sync posedge \clk
       update \dbus__dat_w \dbus__dat_w$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   wire width 1 $75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   cell $and $76
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116185,9 +116447,9 @@ module \lsmem
     connect \B \dbus__err
     connect \Y $75
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   wire width 1 $77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   cell $not $78
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116195,9 +116457,9 @@ module \lsmem
     connect \A \m_stall_i
     connect \Y $77
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
   wire width 1 $79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
   cell $not $80
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116207,12 +116469,12 @@ module \lsmem
   end
   process $group_7
     assign \m_load_err_o$next \m_load_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
     switch { $77 $75 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
       case 2'-1
         assign \m_load_err_o$next $79
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
       case 2'1-
         assign \m_load_err_o$next 1'0
     end
@@ -116226,9 +116488,9 @@ module \lsmem
     sync posedge \clk
       update \m_load_err_o \m_load_err_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   wire width 1 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   cell $and $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116239,9 +116501,9 @@ module \lsmem
     connect \B \dbus__err
     connect \Y $81
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   wire width 1 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   cell $not $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116251,12 +116513,12 @@ module \lsmem
   end
   process $group_8
     assign \m_store_err_o$next \m_store_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
     switch { $83 $81 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
       case 2'-1
         assign \m_store_err_o$next \dbus__we
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
       case 2'1-
         assign \m_store_err_o$next 1'0
     end
@@ -116270,9 +116532,9 @@ module \lsmem
     sync posedge \clk
       update \m_store_err_o \m_store_err_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   wire width 1 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
   cell $and $86
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116283,9 +116545,9 @@ module \lsmem
     connect \B \dbus__err
     connect \Y $85
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   wire width 1 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
   cell $not $88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116295,12 +116557,12 @@ module \lsmem
   end
   process $group_9
     assign \m_badaddr_o$next \m_badaddr_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
     switch { $87 $85 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:108"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
       case 2'-1
         assign \m_badaddr_o$next \dbus__adr
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
       case 2'1-
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -116318,9 +116580,9 @@ module \lsmem
     assign \x_busy_o \dbus__cyc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
   wire width 1 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
   cell $or $90
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -116333,12 +116595,12 @@ module \lsmem
   end
   process $group_11
     assign \m_busy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
     switch { $89 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
       case 1'1
         assign \m_busy_o 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:125"
       case
         assign \m_busy_o \dbus__cyc
     end
@@ -116358,21 +116620,21 @@ module \l0
   wire width 1 input 3 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 input 4 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 96 input 5 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 6 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 output 7 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 output 8 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 9 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 10 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 11 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 12 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 13 \ldst_port0_is_ld_i$1
@@ -116382,9 +116644,9 @@ module \l0
   wire width 1 output 15 \ldst_port0_is_st_i$2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 output 16 \ldst_port0_data_len$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 48 output 17 \ldst_port0_addr_i$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 18 \ldst_port0_addr_i_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
   wire width 8 output 19 \x_mask_i
@@ -116394,15 +116656,15 @@ module \l0
   wire width 1 output 21 \ldst_port0_addr_ok_o$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
   wire width 64 output 22 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 23 \ldst_port0_ld_data_o$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 24 \ldst_port0_ld_data_o_ok$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
   wire width 1 output 25 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 26 \ldst_port0_st_data_i_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 27 \ldst_port0_st_data_i$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
   wire width 64 output 28 \x_st_data_i
@@ -116448,7 +116710,7 @@ module \l0
   wire width 1 output 48 \m_load_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
   wire width 1 output 49 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
   wire width 45 output 50 \m_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
   wire width 1 output 51 \m_busy_o
@@ -142831,13 +143093,13 @@ module \spr
   wire width 1 input 4 \dest__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 input 5 \dest__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:197"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:199"
   wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:201"
-  wire width 1 \addrmatch
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+  wire width 1 \addrmatch
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
   cell $and $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -142850,14 +143112,14 @@ module \spr
   end
   process $group_0
     assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
     switch { \src__ren }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
       case 1'1
         assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
         switch { $1 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
           case 1'1
             assign \wr_detect 1'1
         end
@@ -142868,9 +143130,9 @@ module \spr
   wire width 6 \dest__waddr
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 6 \src__raddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:202"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:204"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:202"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:204"
   cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
@@ -142883,17 +143145,17 @@ module \spr
   end
   process $group_1
     assign \addrmatch 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
     switch { \src__ren }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
       case 1'1
         assign \addrmatch $3
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
   cell $and $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -142904,9 +143166,9 @@ module \spr
     connect \B \addrmatch
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
   cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -142914,279 +143176,279 @@ module \spr
     connect \A \wr_detect
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$9$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$10$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$13$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$18$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$19$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$20$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$21$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$22$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$23$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$24$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$25$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$26$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$27$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$28$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$29$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$30$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$31$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$32$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$33$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$34$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$35$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$36$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$37$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$38$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$39$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$40$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$41$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$42$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$43$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$44$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$45$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$46$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$47$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$48$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$49$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$50$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$51$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$52$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$53$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$54$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$55$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$56$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$57$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$58$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$59$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$60$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$61$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$62$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$63$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$64$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$65$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$66$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$67$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$68$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$69$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$70$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$71$next
   process $group_2
     assign \src__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
     switch { \src__ren }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:198"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:200"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
         switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205"
           case 1'1
             assign \src__data_o \dest__data_i
         end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
         switch { $7 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:207"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209"
             switch \src__raddr
               case 6'000000
                 assign \src__data_o \reg
@@ -143321,189 +143583,189 @@ module \spr
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$72$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$73$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$74$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$75$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$76$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$77$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$78$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$79$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$80$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$81$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$82$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$83$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$84$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$85$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$86$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$87$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$88$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$89$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$90$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$91$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$92$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$93$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$94$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$95$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$96$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$97$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$98$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$99$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$100$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$101$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$102$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$103$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$104$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$105$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$106$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$107$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$108$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$109$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$110$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$111$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$112$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$113$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$114$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$115$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$116$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:195"
   wire width 64 \reg$117$next
   process $group_3
     assign \reg$next \reg
@@ -143616,11 +143878,11 @@ module \spr
     assign \reg$115$next \reg$115
     assign \reg$116$next \reg$116
     assign \reg$117$next \reg$117
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
     switch { \dest__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:212"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:214"
         switch \dest__waddr
           case 6'000000
             assign \reg$next \dest__data_i
@@ -146633,41 +146895,41 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core"
 module \core
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
   wire width 1 output 0 \corebusy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
   wire width 1 output 1 \core_terminated_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:86"
-  wire width 1 input 2 \core_start_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
+  wire width 1 input 2 \core_start_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
   wire width 1 input 3 \core_stop_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 input 4 \bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 5 \ad__go
+  wire width 1 input 5 \ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 6 \ad__rel
+  wire width 1 output 6 \ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 7 \st__go
+  wire width 1 input 7 \st__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 8 \st__rel
+  wire width 1 output 8 \st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 input 9 \cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 10 \cia__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:562"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571"
   wire width 1 input 11 \valid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:78"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
   wire width 1 input 12 \issue_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
   wire width 32 input 13 \raw_opcode_in
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 input 14 \msr__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 15 \msr__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574"
   wire width 64 input 16 \msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
   wire width 64 input 17 \cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -146742,7 +147004,7 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
   wire width 7 output 18 \insn_type
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 output 19 \fast_nia_wen
@@ -146766,7 +147028,7 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40"
   wire width 11 output 24 \fn_unit
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -146841,8 +147103,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 25 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 25 \oper_i_alu_alu0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -146855,77 +147117,77 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 26 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 26 \oper_i_alu_alu0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 27 \imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 28 \imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 30 \rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 31 \oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 32 \oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 33 \oper_i__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
-  wire width 1 output 34 \invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 35 \oper_i__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \oper_i_alu_alu0__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
+  wire width 1 output 34 \invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \oper_i_alu_alu0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
   wire width 1 output 36 \zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \oper_i__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \oper_i_alu_alu0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
   wire width 1 output 38 \invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 39 \oper_i__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \oper_i_alu_alu0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
   wire width 1 output 40 \write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 41 \oper_i__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 41 \oper_i_alu_alu0__input_carry
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
-  wire width 2 output 42 \input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 43 \oper_i__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+  wire width 2 output 42 \input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 43 \oper_i_alu_alu0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
   wire width 1 output 44 \output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 45 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
-  wire width 1 output 46 \is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 47 \oper_i__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 45 \oper_i_alu_alu0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
-  wire width 1 output 48 \is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 49 \oper_i__data_len
+  wire width 1 output 46 \is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 47 \oper_i_alu_alu0__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+  wire width 1 output 48 \is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 49 \oper_i_alu_alu0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
   wire width 4 output 50 \data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 51 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 51 \oper_i_alu_alu0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
   wire width 32 output 52 \insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 53 \issue_i$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 54 \busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 1 output 53 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 54 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 55 \reg1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 56 \reg2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:81"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
   wire width 1 output 57 \xer_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -147000,8 +147262,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 58 \oper_i__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 58 \oper_i_alu_cr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147014,32 +147276,32 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 59 \oper_i__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 60 \oper_i__insn$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 61 \oper_i__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
-  wire width 1 output 62 \read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 63 \oper_i__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 59 \oper_i_alu_cr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 60 \oper_i_alu_cr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 61 \oper_i_alu_cr0__read_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
+  wire width 1 output 62 \read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 63 \oper_i_alu_cr0__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
   wire width 1 output 64 \write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 65 \issue_i$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 66 \busy_o$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 1 output 65 \cu_issue_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 66 \cu_busy_o$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 67 \cr_in1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 68 \cr_in2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 69 \cr_in2_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 70 \oper_i__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
-  wire width 64 output 71 \cia$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 69 \cr_in2_ok$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 70 \oper_i_alu_branch0__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
+  wire width 64 output 71 \cia$4
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147113,8 +147375,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 72 \oper_i__insn_type$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 72 \oper_i_alu_branch0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147127,23 +147389,23 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 73 \oper_i__fn_unit$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 74 \oper_i__insn$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 75 \oper_i__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 73 \oper_i_alu_branch0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 74 \oper_i_alu_branch0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 75 \oper_i_alu_branch0__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
   wire width 1 output 76 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 77 \oper_i__is_32bit$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 78 \issue_i$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 77 \oper_i_alu_branch0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 79 \busy_o$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 1 output 78 \cu_issue_i$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 79 \cu_busy_o$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 80 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 81 \fast2_ok
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -147218,8 +147480,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 82 \oper_i__insn_type$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 82 \oper_i_alu_trap0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147232,30 +147494,30 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 83 \oper_i__fn_unit$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 84 \oper_i__insn$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 85 \oper_i__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
-  wire width 64 output 86 \msr$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 87 \oper_i__cia$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 88 \oper_i__is_32bit$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 output 89 \oper_i__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
-  wire width 5 output 90 \traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 output 91 \oper_i__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 83 \oper_i_alu_trap0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 84 \oper_i_alu_trap0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 85 \oper_i_alu_trap0__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+  wire width 64 output 86 \msr$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 87 \oper_i_alu_trap0__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 88 \oper_i_alu_trap0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 output 89 \oper_i_alu_trap0__traptype
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+  wire width 5 output 90 \traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 output 91 \oper_i_alu_trap0__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
   wire width 13 output 92 \trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 93 \issue_i$21
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 94 \busy_o$22
+  wire width 1 output 93 \cu_issue_i$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 94 \cu_busy_o$9
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147329,8 +147591,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 95 \oper_i__insn_type$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 95 \oper_i_alu_logical0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147343,36 +147605,36 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 96 \oper_i__fn_unit$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 97 \oper_i__invert_a$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 98 \oper_i__zero_a$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 96 \oper_i_alu_logical0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 97 \oper_i_alu_logical0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 98 \oper_i_alu_logical0__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 99 \oper_i__input_carry$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 100 \oper_i__invert_out$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 101 \oper_i__write_cr0$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 102 \oper_i__output_carry$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 103 \oper_i__is_32bit$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 104 \oper_i__is_signed$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 105 \oper_i__data_len$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 106 \oper_i__insn$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 107 \issue_i$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 99 \oper_i_alu_logical0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 100 \oper_i_alu_logical0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 101 \oper_i_alu_logical0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 102 \oper_i_alu_logical0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 103 \oper_i_alu_logical0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 104 \oper_i_alu_logical0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 105 \oper_i_alu_logical0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 106 \oper_i_alu_logical0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 108 \busy_o$36
+  wire width 1 output 107 \cu_issue_i$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 108 \cu_busy_o$11
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147446,8 +147708,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 109 \oper_i__insn_type$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 109 \oper_i_alu_spr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147460,17 +147722,17 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 110 \oper_i__fn_unit$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 111 \oper_i__insn$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 112 \oper_i__is_32bit$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 113 \issue_i$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 110 \oper_i_alu_spr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 111 \oper_i_alu_spr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 112 \oper_i_alu_spr0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 114 \busy_o$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 1 output 113 \cu_issue_i$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 114 \cu_busy_o$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 115 \spr1_ok
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -147545,8 +147807,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 116 \oper_i__insn_type$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 116 \oper_i_alu_mul0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147559,26 +147821,26 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 117 \oper_i__fn_unit$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 118 \oper_i__invert_a$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 119 \oper_i__zero_a$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 120 \oper_i__invert_out$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 121 \oper_i__write_cr0$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 122 \oper_i__is_32bit$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 123 \oper_i__is_signed$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 124 \oper_i__insn$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 125 \issue_i$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 117 \oper_i_alu_mul0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 118 \oper_i_alu_mul0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 119 \oper_i_alu_mul0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 120 \oper_i_alu_mul0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 121 \oper_i_alu_mul0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 122 \oper_i_alu_mul0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 123 \oper_i_alu_mul0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 124 \oper_i_alu_mul0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 126 \busy_o$53
+  wire width 1 output 125 \cu_issue_i$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 126 \cu_busy_o$15
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147652,8 +147914,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 127 \oper_i__insn_type$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 127 \oper_i_alu_shift_rot0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147666,35 +147928,35 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 128 \oper_i__fn_unit$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 128 \oper_i_alu_shift_rot0__fn_unit
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 130 \oper_i__input_carry$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 131 \oper_i__output_carry$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 132 \oper_i__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
-  wire width 1 output 133 \input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 134 \oper_i__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 130 \oper_i_alu_shift_rot0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 131 \oper_i_alu_shift_rot0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 132 \oper_i_alu_shift_rot0__input_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+  wire width 1 output 133 \input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 134 \oper_i_alu_shift_rot0__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
   wire width 1 output 135 \output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 136 \oper_i__is_32bit$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 137 \oper_i__is_signed$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 138 \oper_i__insn$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 139 \issue_i$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 136 \oper_i_alu_shift_rot0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 137 \oper_i_alu_shift_rot0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 138 \oper_i_alu_shift_rot0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 140 \busy_o$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 1 output 139 \cu_issue_i$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 140 \cu_busy_o$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 141 \reg3_ok
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -147769,130 +148031,130 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 142 \oper_i__insn_type$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 143 \oper_i__zero_a$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 144 \oper_i__is_32bit$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 145 \oper_i__is_signed$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 146 \oper_i__data_len$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 147 \oper_i__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
-  wire width 1 output 148 \byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 149 \oper_i__sign_extend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 142 \oper_i_ldst_ldst0__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 143 \oper_i_ldst_ldst0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 144 \oper_i_ldst_ldst0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 145 \oper_i_ldst_ldst0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 146 \oper_i_ldst_ldst0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 147 \oper_i_ldst_ldst0__byte_reverse
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+  wire width 1 output 148 \byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 149 \oper_i_ldst_ldst0__sign_extend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
   wire width 1 output 150 \sign_extend
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 151 \oper_i__ldst_mode
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 151 \oper_i_ldst_ldst0__ldst_mode
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
   wire width 2 output 152 \ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 153 \issue_i$68
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 154 \busy_o$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 1 output 153 \cu_issue_i$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 154 \cu_busy_o$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 155 \reg1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 156 \rd__rel
+  wire width 4 output 156 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 157 \rd__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  wire width 4 output 157 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 output 158 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 159 \rd__rel$70
+  wire width 6 output 159 \cu_rd__rel_o$20
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 160 \rd__go$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 161 \src1_i$72
+  wire width 6 output 160 \cu_rd__go_i$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 161 \src1_i$22
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 162 \rd__rel$73
+  wire width 4 output 162 \cu_rd__rel_o$23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 163 \rd__go$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 164 \src1_i$75
+  wire width 4 output 163 \cu_rd__go_i$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 164 \src1_i$25
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 165 \rd__rel$76
+  wire width 2 output 165 \cu_rd__rel_o$26
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 166 \rd__go$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 167 \src1_i$78
+  wire width 2 output 166 \cu_rd__go_i$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 167 \src1_i$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 168 \rd__rel$79
+  wire width 6 output 168 \cu_rd__rel_o$29
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 169 \rd__go$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 170 \src1_i$81
+  wire width 6 output 169 \cu_rd__go_i$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 170 \src1_i$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 171 \rd__rel$82
+  wire width 3 output 171 \cu_rd__rel_o$32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 172 \rd__go$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 173 \src1_i$84
+  wire width 3 output 172 \cu_rd__go_i$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 173 \src1_i$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 174 \rd__rel$85
+  wire width 4 output 174 \cu_rd__rel_o$35
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 175 \rd__go$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 176 \src1_i$87
+  wire width 4 output 175 \cu_rd__go_i$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 176 \src1_i$37
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 177 \rd__rel$88
+  wire width 3 output 177 \cu_rd__rel_o$38
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 178 \rd__go$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 179 \src1_i$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 3 output 178 \cu_rd__go_i$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 179 \src1_i$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 180 \reg2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 output 181 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 182 \src2_i$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 183 \src2_i$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 184 \src2_i$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 185 \src2_i$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 186 \src2_i$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 187 \src2_i$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 182 \src2_i$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 183 \src2_i$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 184 \src2_i$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 185 \src2_i$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 186 \src2_i$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 187 \src2_i$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 188 \reg3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 output 189 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 190 \cr_in1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 191 \rd__rel$97
+  wire width 3 output 191 \cu_rd__rel_o$47
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 192 \rd__go$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 3 output 192 \cu_rd__go_i$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 193 \cr_in2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 3 output 194 \cr_in2$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 output 194 \cr_in2$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 195 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 196 \src1_i$100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 196 \src1_i$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 197 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 198 \src2_i$101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 198 \src2_i$51
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
   attribute \enum_value_0000000011 "DSCR"
@@ -148004,79 +148266,79 @@ module \core
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 199 \spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 200 \src2_i$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 200 \src2_i$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 201 \rego
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 202 \wr__rel
+  wire width 5 output 202 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 203 \wr__go
+  wire width 5 output 203 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 204 \wr__rel$103
+  wire width 3 output 204 \cu_wr__rel_o$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 205 \wr__go$104
+  wire width 3 output 205 \cu_wr__go_i$54
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 206 \wr__rel$105
+  wire width 5 output 206 \cu_wr__rel_o$55
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 207 \wr__go$106
+  wire width 5 output 207 \cu_wr__go_i$56
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 208 \wr__rel$107
+  wire width 3 output 208 \cu_wr__rel_o$57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 209 \wr__go$108
+  wire width 3 output 209 \cu_wr__go_i$58
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 210 \wr__rel$109
+  wire width 6 output 210 \cu_wr__rel_o$59
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 211 \wr__go$110
+  wire width 6 output 211 \cu_wr__go_i$60
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 212 \wr__rel$111
+  wire width 4 output 212 \cu_wr__rel_o$61
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 213 \wr__go$112
+  wire width 4 output 213 \cu_wr__go_i$62
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 214 \wr__rel$113
+  wire width 3 output 214 \cu_wr__rel_o$63
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 215 \wr__go$114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 3 output 215 \cu_wr__go_i$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 216 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 217 \wr__rel$115
+  wire width 2 output 217 \cu_wr__rel_o$65
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 218 \wr__go$116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 2 output 218 \cu_wr__go_i$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 219 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 220 \dest1_o$117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 221 \dest1_o$118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 222 \dest1_o$119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 223 \dest1_o$120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 224 \dest1_o$121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 225 \dest1_o$122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 220 \dest1_o$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 221 \dest1_o$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 222 \dest1_o$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 223 \dest1_o$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 224 \dest1_o$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 225 \dest1_o$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 226 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 227 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 228 \ea_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 64 output 229 \ea$123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 229 \ea$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 230 \cr_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 231 \fasto1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 232 \wr__rel$124
+  wire width 3 output 232 \cu_wr__rel_o$74
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 233 \wr__go$125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 234 \dest1_o$126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 3 output 233 \cu_wr__go_i$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 234 \dest1_o$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 235 \fasto2
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -148189,9 +148451,9 @@ module \core
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 236 \spro
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 output 237 \opcode_in
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -148199,7 +148461,7 @@ module \core
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 238 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -148216,26 +148478,26 @@ module \core
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 239 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 240 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 241 \out_sel
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 242 \rc_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -148245,7 +148507,7 @@ module \core
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 243 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -148253,8 +148515,8 @@ module \core
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
-  wire width 3 output 244 \cr_out$127
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  wire width 3 output 244 \cr_out$77
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -148328,7 +148590,7 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 245 \internal_op
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -148342,19 +148604,19 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 246 \function_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 247 \rego_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 248 \ea_ok$128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 248 \ea_ok$78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 249 \spro_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 250 \fasto1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 251 \fasto2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 252 \cr_out_ok
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -148362,27 +148624,27 @@ module \core
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 253 \ldst_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 254 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 255 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 256 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 257 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 258 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
-  wire width 1 output 259 \lk$129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 output 259 \lk$79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 260 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 261 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83"
   wire width 1 output 262 \xer_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
   wire width 8 output 263 \asmcode
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -148414,110 +148676,110 @@ module \core
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 264 \form
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 265 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 266 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
-  wire width 8 output 267 \asmcode$130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 268 \go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 269 \shadown_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 270 \go_die_i$131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 271 \shadown_i$132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 272 \go_die_i$133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 273 \shadown_i$134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 274 \go_die_i$135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 275 \shadown_i$136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 276 \go_die_i$137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 277 \shadown_i$138
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 278 \go_die_i$139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 279 \shadown_i$140
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 280 \go_die_i$141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 281 \shadown_i$142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 282 \go_die_i$143
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 283 \shadown_i$144
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 284 \go_die_i$145
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  wire width 8 output 267 \asmcode$80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 268 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 269 \cu_shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 270 \cu_go_die_i$81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 271 \cu_shadown_i$82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 272 \cu_go_die_i$83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 273 \cu_shadown_i$84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 274 \cu_go_die_i$85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 275 \cu_shadown_i$86
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 276 \cu_go_die_i$87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 277 \cu_shadown_i$88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 278 \cu_go_die_i$89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 279 \cu_shadown_i$90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 280 \cu_go_die_i$91
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 281 \cu_shadown_i$92
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 282 \cu_go_die_i$93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 283 \cu_shadown_i$94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 284 \cu_go_die_i$95
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
   wire width 1 output 285 \load_mem_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
   wire width 1 output 286 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 287 \shadown_i$146
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 287 \cu_shadown_i$96
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 288 \ldst_port0_is_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
   wire width 1 output 289 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
   wire width 4 output 290 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 96 output 291 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 292 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 output 293 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 output 294 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 295 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 296 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 297 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 298 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 299 \ldst_port0_is_ld_i$147
+  wire width 1 output 299 \ldst_port0_is_ld_i$97
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
   wire width 1 output 300 \ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 301 \ldst_port0_is_st_i$148
+  wire width 1 output 301 \ldst_port0_is_st_i$98
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 302 \ldst_port0_data_len$149
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 48 output 303 \ldst_port0_addr_i$150
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 304 \ldst_port0_addr_i_ok$151
+  wire width 4 output 302 \ldst_port0_data_len$99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 48 output 303 \ldst_port0_addr_i$100
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 304 \ldst_port0_addr_i_ok$101
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
   wire width 8 output 305 \x_mask_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
   wire width 48 output 306 \x_addr_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 307 \ldst_port0_addr_ok_o$152
+  wire width 1 output 307 \ldst_port0_addr_ok_o$102
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
   wire width 64 output 308 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 64 output 309 \ldst_port0_ld_data_o$153
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 310 \ldst_port0_ld_data_o_ok$154
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 309 \ldst_port0_ld_data_o$103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 310 \ldst_port0_ld_data_o_ok$104
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
   wire width 1 output 311 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 312 \ldst_port0_st_data_i_ok$155
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 64 output 313 \ldst_port0_st_data_i$156
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 312 \ldst_port0_st_data_i_ok$105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 313 \ldst_port0_st_data_i$106
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
   wire width 64 output 314 \x_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 315 \ldst_port0_addr_exc_o$157
+  wire width 1 input 315 \ldst_port0_addr_exc_o$107
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
   wire width 1 output 316 \x_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
@@ -148529,9 +148791,9 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
   wire width 1 output 320 \ldst_port0_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 input 321 \ldst_port0_go_die_i$158
+  wire width 1 input 321 \ldst_port0_go_die_i$108
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 322 \ldst_port0_busy_o$159
+  wire width 1 output 322 \ldst_port0_busy_o$109
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 output 323 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
@@ -148558,7 +148820,7 @@ module \core
   wire width 1 output 334 \m_load_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
   wire width 1 output 335 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
   wire width 45 output 336 \m_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
   wire width 1 output 337 \m_busy_o
@@ -148592,12 +148854,12 @@ module \core
     connect \write_cr_whole \write_cr_whole
     connect \cr_in1_ok \cr_in1_ok
     connect \cr_in2_ok \cr_in2_ok
-    connect \cr_in2_ok$1 \cr_in2_ok$7
-    connect \cia$2 \cia$8
+    connect \cr_in2_ok$1 \cr_in2_ok$3
+    connect \cia$2 \cia$4
     connect \lk \lk
     connect \fast1_ok \fast1_ok
     connect \fast2_ok \fast2_ok
-    connect \msr$3 \msr$18
+    connect \msr$3 \msr$7
     connect \traptype \traptype
     connect \trapaddr \trapaddr
     connect \spr1_ok \spr1_ok
@@ -148612,7 +148874,7 @@ module \core
     connect \reg3 \reg3
     connect \cr_in1 \cr_in1
     connect \cr_in2 \cr_in2
-    connect \cr_in2$4 \cr_in2$99
+    connect \cr_in2$4 \cr_in2$49
     connect \fast1 \fast1
     connect \fast2 \fast2
     connect \spr1 \spr1
@@ -148629,11 +148891,11 @@ module \core
     connect \out_sel \out_sel
     connect \rc_sel \rc_sel
     connect \cr_in \cr_in
-    connect \cr_out$5 \cr_out$127
+    connect \cr_out$5 \cr_out$77
     connect \internal_op \internal_op
     connect \function_unit \function_unit
     connect \rego_ok \rego_ok
-    connect \ea_ok \ea_ok$128
+    connect \ea_ok \ea_ok$78
     connect \spro_ok \spro_ok
     connect \fasto1_ok \fasto1_ok
     connect \fasto2_ok \fasto2_ok
@@ -148644,7 +148906,7 @@ module \core
     connect \cry_out \cry_out
     connect \is_32b \is_32b
     connect \sgn \sgn
-    connect \lk$6 \lk$129
+    connect \lk$6 \lk$79
     connect \br \br
     connect \sgn_ext \sgn_ext
     connect \xer_out \xer_out
@@ -148652,530 +148914,530 @@ module \core
     connect \form \form
     connect \rsrv \rsrv
     connect \sgl_pipe \sgl_pipe
-    connect \asmcode$7 \asmcode$130
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \fus_oper_i__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 \fus_rdmaskn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 6 \fus_rdmaskn$160
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \fus_oper_i__imm_data__imm$161
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__imm_data__imm_ok$162
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 \fus_rdmaskn$163
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 4 \fus_rdmaskn$164
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \fus_oper_i__imm_data__imm$165
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__imm_data__imm_ok$166
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__rc__rc$167
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__rc__rc_ok$168
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__oe__oe$169
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__oe__oe_ok$170
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 2 \fus_rdmaskn$171
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 6 \fus_rdmaskn$172
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \fus_oper_i__imm_data__imm$173
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__imm_data__imm_ok$174
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__rc__rc$175
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__rc__rc_ok$176
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__oe__oe$177
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 \fus_oper_i__oe__oe_ok$178
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
-  wire width 3 \fus_rdmaskn$179
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 \fus_oper_i__imm_data__imm$180
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
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-    connect \ad__go \ad__go
-    connect \ad__rel \ad__rel
-    connect \st__go \st__go
-    connect \st__rel \st__rel
+    connect \ad__go_i \ad__go_i
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+    connect \st__go_i \st__go_i
+    connect \st__rel_o \st__rel_o
     connect \rst \rst
     connect \clk \clk
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-    connect \rd__rel \rd__rel
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+    connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type
+    connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit
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+    connect \oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm_ok
+    connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc
+    connect \oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc_ok
+    connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe
+    connect \oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe_ok
+    connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a
+    connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a
+    connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out
+    connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0
+    connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry
+    connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry
+    connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit
+    connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed
+    connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len
+    connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn
+    connect \cu_issue_i \cu_issue_i
+    connect \cu_busy_o \cu_busy_o
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+    connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
+    connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
+    connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
+    connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole
+    connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole
+    connect \cu_issue_i$1 \cu_issue_i$1
+    connect \cu_busy_o$2 \cu_busy_o$2
+    connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$110
+    connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia
+    connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type
+    connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit
+    connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn
+    connect \oper_i_alu_branch0__imm_data__imm \fus_oper_i_alu_branch0__imm_data__imm
+    connect \oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm_ok
+    connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk
+    connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit
+    connect \cu_issue_i$4 \cu_issue_i$5
+    connect \cu_busy_o$5 \cu_busy_o$6
+    connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$111
+    connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type
+    connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit
+    connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn
+    connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
+    connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia
+    connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit
+    connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
+    connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
+    connect \cu_issue_i$7 \cu_issue_i$8
+    connect \cu_busy_o$8 \cu_busy_o$9
+    connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$112
+    connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type
+    connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit
+    connect \oper_i_alu_logical0__imm_data__imm \fus_oper_i_alu_logical0__imm_data__imm
+    connect \oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm_ok
+    connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc
+    connect \oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc_ok
+    connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe
+    connect \oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe_ok
+    connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a
+    connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
+    connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry
+    connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out
+    connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
+    connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry
+    connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit
+    connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed
+    connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len
+    connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn
+    connect \cu_issue_i$10 \cu_issue_i$10
+    connect \cu_busy_o$11 \cu_busy_o$11
+    connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$113
+    connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
+    connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit
+    connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn
+    connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
+    connect \cu_issue_i$13 \cu_issue_i$12
+    connect \cu_busy_o$14 \cu_busy_o$13
+    connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$114
+    connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type
+    connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit
+    connect \oper_i_alu_mul0__imm_data__imm \fus_oper_i_alu_mul0__imm_data__imm
+    connect \oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm_ok
+    connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc
+    connect \oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc_ok
+    connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe
+    connect \oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe_ok
+    connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a
+    connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a
+    connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out
+    connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
+    connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit
+    connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed
+    connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn
+    connect \cu_issue_i$16 \cu_issue_i$14
+    connect \cu_busy_o$17 \cu_busy_o$15
+    connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$115
+    connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type
+    connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit
+    connect \oper_i_alu_shift_rot0__imm_data__imm \fus_oper_i_alu_shift_rot0__imm_data__imm
+    connect \oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm_ok
+    connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc
+    connect \oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc_ok
+    connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe
+    connect \oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe_ok
+    connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry
+    connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry
+    connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr
+    connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr
+    connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit
+    connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed
+    connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn
+    connect \cu_issue_i$19 \cu_issue_i$16
+    connect \cu_busy_o$20 \cu_busy_o$17
+    connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$116
+    connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
+    connect \oper_i_ldst_ldst0__imm_data__imm \fus_oper_i_ldst_ldst0__imm_data__imm
+    connect \oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm_ok
+    connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
+    connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc
+    connect \oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc_ok
+    connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe
+    connect \oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe_ok
+    connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit
+    connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed
+    connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len
+    connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse
+    connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
+    connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode
+    connect \cu_issue_i$22 \cu_issue_i$18
+    connect \cu_busy_o$23 \cu_busy_o$19
+    connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$117
+    connect \cu_rd__rel_o \cu_rd__rel_o
+    connect \cu_rd__go_i \cu_rd__go_i
     connect \src1_i \src1_i
-    connect \rd__rel$100 \rd__rel$70
-    connect \rd__go$101 \rd__go$71
-    connect \src1_i$102 \src1_i$72
-    connect \rd__rel$103 \rd__rel$73
-    connect \rd__go$104 \rd__go$74
-    connect \src1_i$105 \src1_i$75
-    connect \rd__rel$106 \rd__rel$76
-    connect \rd__go$107 \rd__go$77
-    connect \src1_i$108 \src1_i$78
-    connect \rd__rel$109 \rd__rel$79
-    connect \rd__go$110 \rd__go$80
-    connect \src1_i$111 \src1_i$81
-    connect \rd__rel$112 \rd__rel$82
-    connect \rd__go$113 \rd__go$83
-    connect \src1_i$114 \src1_i$84
-    connect \rd__rel$115 \rd__rel$85
-    connect \rd__go$116 \rd__go$86
-    connect \src1_i$117 \src1_i$87
-    connect \rd__rel$118 \rd__rel$88
-    connect \rd__go$119 \rd__go$89
-    connect \src1_i$120 \src1_i$90
+    connect \cu_rd__rel_o$25 \cu_rd__rel_o$20
+    connect \cu_rd__go_i$26 \cu_rd__go_i$21
+    connect \src1_i$27 \src1_i$22
+    connect \cu_rd__rel_o$28 \cu_rd__rel_o$23
+    connect \cu_rd__go_i$29 \cu_rd__go_i$24
+    connect \src1_i$30 \src1_i$25
+    connect \cu_rd__rel_o$31 \cu_rd__rel_o$26
+    connect \cu_rd__go_i$32 \cu_rd__go_i$27
+    connect \src1_i$33 \src1_i$28
+    connect \cu_rd__rel_o$34 \cu_rd__rel_o$29
+    connect \cu_rd__go_i$35 \cu_rd__go_i$30
+    connect \src1_i$36 \src1_i$31
+    connect \cu_rd__rel_o$37 \cu_rd__rel_o$32
+    connect \cu_rd__go_i$38 \cu_rd__go_i$33
+    connect \src1_i$39 \src1_i$34
+    connect \cu_rd__rel_o$40 \cu_rd__rel_o$35
+    connect \cu_rd__go_i$41 \cu_rd__go_i$36
+    connect \src1_i$42 \src1_i$37
+    connect \cu_rd__rel_o$43 \cu_rd__rel_o$38
+    connect \cu_rd__go_i$44 \cu_rd__go_i$39
+    connect \src1_i$45 \src1_i$40
     connect \src2_i \src2_i
-    connect \src2_i$121 \src2_i$91
-    connect \src2_i$122 \src2_i$92
-    connect \src2_i$123 \src2_i$93
-    connect \src2_i$124 \src2_i$94
-    connect \src2_i$125 \src2_i$95
-    connect \src2_i$126 \src2_i$96
+    connect \src2_i$46 \src2_i$41
+    connect \src2_i$47 \src2_i$42
+    connect \src2_i$48 \src2_i$43
+    connect \src2_i$49 \src2_i$44
+    connect \src2_i$50 \src2_i$45
+    connect \src2_i$51 \src2_i$46
     connect \src3_i \fus_src3_i
-    connect \src3_i$127 \src3_i
-    connect \src3_i$128 \fus_src3_i$194
+    connect \src3_i$52 \src3_i
+    connect \src3_i$53 \fus_src3_i$118
     connect \src4_i \fus_src4_i
-    connect \src3_i$129 \fus_src3_i$195
-    connect \src4_i$130 \fus_src4_i$196
+    connect \src3_i$54 \fus_src3_i$119
+    connect \src4_i$55 \fus_src4_i$120
     connect \src6_i \fus_src6_i
-    connect \src4_i$131 \fus_src4_i$197
+    connect \src4_i$56 \fus_src4_i$121
     connect \src5_i \fus_src5_i
-    connect \src3_i$132 \fus_src3_i$198
-    connect \src4_i$133 \fus_src4_i$199
-    connect \rd__rel$134 \rd__rel$97
-    connect \rd__go$135 \rd__go$98
-    connect \src3_i$136 \fus_src3_i$200
-    connect \src5_i$137 \fus_src5_i$201
-    connect \src6_i$138 \fus_src6_i$202
-    connect \src1_i$139 \src1_i$100
-    connect \src3_i$140 \fus_src3_i$203
-    connect \src3_i$141 \fus_src3_i$204
-    connect \src2_i$142 \src2_i$101
-    connect \src4_i$143 \fus_src4_i$205
-    connect \src2_i$144 \src2_i$102
+    connect \src3_i$57 \fus_src3_i$122
+    connect \src4_i$58 \fus_src4_i$123
+    connect \cu_rd__rel_o$59 \cu_rd__rel_o$47
+    connect \cu_rd__go_i$60 \cu_rd__go_i$48
+    connect \src3_i$61 \fus_src3_i$124
+    connect \src5_i$62 \fus_src5_i$125
+    connect \src6_i$63 \fus_src6_i$126
+    connect \src1_i$64 \src1_i$50
+    connect \src3_i$65 \fus_src3_i$127
+    connect \src3_i$66 \fus_src3_i$128
+    connect \src2_i$67 \src2_i$51
+    connect \src4_i$68 \fus_src4_i$129
+    connect \src2_i$69 \src2_i$52
     connect \o_ok \fus_o_ok
-    connect \wr__rel \wr__rel
-    connect \wr__go \wr__go
-    connect \o_ok$145 \fus_o_ok$206
-    connect \wr__rel$146 \wr__rel$103
-    connect \wr__go$147 \wr__go$104
-    connect \o_ok$148 \fus_o_ok$207
-    connect \wr__rel$149 \wr__rel$105
-    connect \wr__go$150 \wr__go$106
-    connect \o_ok$151 \fus_o_ok$208
-    connect \wr__rel$152 \wr__rel$107
-    connect \wr__go$153 \wr__go$108
-    connect \o_ok$154 \fus_o_ok$209
-    connect \wr__rel$155 \wr__rel$109
-    connect \wr__go$156 \wr__go$110
-    connect \o_ok$157 \fus_o_ok$210
-    connect \wr__rel$158 \wr__rel$111
-    connect \wr__go$159 \wr__go$112
-    connect \o_ok$160 \fus_o_ok$211
-    connect \wr__rel$161 \wr__rel$113
-    connect \wr__go$162 \wr__go$114
-    connect \wr__rel$163 \wr__rel$115
-    connect \wr__go$164 \wr__go$116
+    connect \cu_wr__rel_o \cu_wr__rel_o
+    connect \cu_wr__go_i \cu_wr__go_i
+    connect \o_ok$70 \fus_o_ok$130
+    connect \cu_wr__rel_o$71 \cu_wr__rel_o$53
+    connect \cu_wr__go_i$72 \cu_wr__go_i$54
+    connect \o_ok$73 \fus_o_ok$131
+    connect \cu_wr__rel_o$74 \cu_wr__rel_o$55
+    connect \cu_wr__go_i$75 \cu_wr__go_i$56
+    connect \o_ok$76 \fus_o_ok$132
+    connect \cu_wr__rel_o$77 \cu_wr__rel_o$57
+    connect \cu_wr__go_i$78 \cu_wr__go_i$58
+    connect \o_ok$79 \fus_o_ok$133
+    connect \cu_wr__rel_o$80 \cu_wr__rel_o$59
+    connect \cu_wr__go_i$81 \cu_wr__go_i$60
+    connect \o_ok$82 \fus_o_ok$134
+    connect \cu_wr__rel_o$83 \cu_wr__rel_o$61
+    connect \cu_wr__go_i$84 \cu_wr__go_i$62
+    connect \o_ok$85 \fus_o_ok$135
+    connect \cu_wr__rel_o$86 \cu_wr__rel_o$63
+    connect \cu_wr__go_i$87 \cu_wr__go_i$64
+    connect \cu_wr__rel_o$88 \cu_wr__rel_o$65
+    connect \cu_wr__go_i$89 \cu_wr__go_i$66
     connect \dest1_o \dest1_o
-    connect \dest1_o$165 \dest1_o$117
-    connect \dest1_o$166 \dest1_o$118
-    connect \dest1_o$167 \dest1_o$119
-    connect \dest1_o$168 \dest1_o$120
-    connect \dest1_o$169 \dest1_o$121
-    connect \dest1_o$170 \dest1_o$122
+    connect \dest1_o$90 \dest1_o$67
+    connect \dest1_o$91 \dest1_o$68
+    connect \dest1_o$92 \dest1_o$69
+    connect \dest1_o$93 \dest1_o$70
+    connect \dest1_o$94 \dest1_o$71
+    connect \dest1_o$95 \dest1_o$72
     connect \o \o
-    connect \ea \ea$123
+    connect \ea \ea$73
     connect \full_cr_ok \fus_full_cr_ok
     connect \dest2_o \fus_dest2_o
     connect \cr_a_ok \fus_cr_a_ok
-    connect \cr_a_ok$171 \fus_cr_a_ok$212
-    connect \cr_a_ok$172 \fus_cr_a_ok$213
-    connect \cr_a_ok$173 \fus_cr_a_ok$214
-    connect \cr_a_ok$174 \fus_cr_a_ok$215
-    connect \dest2_o$175 \fus_dest2_o$216
+    connect \cr_a_ok$96 \fus_cr_a_ok$136
+    connect \cr_a_ok$97 \fus_cr_a_ok$137
+    connect \cr_a_ok$98 \fus_cr_a_ok$138
+    connect \cr_a_ok$99 \fus_cr_a_ok$139
+    connect \dest2_o$100 \fus_dest2_o$140
     connect \dest3_o \fus_dest3_o
-    connect \dest2_o$176 \fus_dest2_o$217
-    connect \dest2_o$177 \fus_dest2_o$218
-    connect \dest2_o$178 \fus_dest2_o$219
+    connect \dest2_o$101 \fus_dest2_o$141
+    connect \dest2_o$102 \fus_dest2_o$142
+    connect \dest2_o$103 \fus_dest2_o$143
     connect \xer_ca_ok \fus_xer_ca_ok
-    connect \xer_ca_ok$179 \fus_xer_ca_ok$220
-    connect \xer_ca_ok$180 \fus_xer_ca_ok$221
-    connect \xer_ca_ok$181 \fus_xer_ca_ok$222
-    connect \dest3_o$182 \fus_dest3_o$223
-    connect \dest3_o$183 \fus_dest3_o$224
+    connect \xer_ca_ok$104 \fus_xer_ca_ok$144
+    connect \xer_ca_ok$105 \fus_xer_ca_ok$145
+    connect \xer_ca_ok$106 \fus_xer_ca_ok$146
+    connect \dest3_o$107 \fus_dest3_o$147
+    connect \dest3_o$108 \fus_dest3_o$148
     connect \dest6_o \fus_dest6_o
-    connect \dest3_o$184 \fus_dest3_o$225
+    connect \dest3_o$109 \fus_dest3_o$149
     connect \xer_ov_ok \fus_xer_ov_ok
-    connect \xer_ov_ok$185 \fus_xer_ov_ok$226
-    connect \xer_ov_ok$186 \fus_xer_ov_ok$227
+    connect \xer_ov_ok$110 \fus_xer_ov_ok$150
+    connect \xer_ov_ok$111 \fus_xer_ov_ok$151
     connect \dest4_o \fus_dest4_o
     connect \dest5_o \fus_dest5_o
-    connect \dest3_o$187 \fus_dest3_o$228
+    connect \dest3_o$112 \fus_dest3_o$152
     connect \xer_so_ok \fus_xer_so_ok
-    connect \xer_so_ok$188 \fus_xer_so_ok$229
-    connect \xer_so_ok$189 \fus_xer_so_ok$230
-    connect \dest5_o$190 \fus_dest5_o$231
-    connect \dest4_o$191 \fus_dest4_o$232
-    connect \dest4_o$192 \fus_dest4_o$233
+    connect \xer_so_ok$113 \fus_xer_so_ok$153
+    connect \xer_so_ok$114 \fus_xer_so_ok$154
+    connect \dest5_o$115 \fus_dest5_o$155
+    connect \dest4_o$116 \fus_dest4_o$156
+    connect \dest4_o$117 \fus_dest4_o$157
     connect \fast1_ok \fus_fast1_ok
-    connect \wr__rel$193 \wr__rel$124
-    connect \wr__go$194 \wr__go$125
-    connect \fast1_ok$195 \fus_fast1_ok$234
-    connect \fast1_ok$196 \fus_fast1_ok$235
-    connect \dest1_o$197 \dest1_o$126
-    connect \dest2_o$198 \fus_dest2_o$236
-    connect \dest3_o$199 \fus_dest3_o$237
+    connect \cu_wr__rel_o$118 \cu_wr__rel_o$74
+    connect \cu_wr__go_i$119 \cu_wr__go_i$75
+    connect \fast1_ok$120 \fus_fast1_ok$158
+    connect \fast1_ok$121 \fus_fast1_ok$159
+    connect \dest1_o$122 \dest1_o$76
+    connect \dest2_o$123 \fus_dest2_o$160
+    connect \dest3_o$124 \fus_dest3_o$161
     connect \fast2_ok \fus_fast2_ok
-    connect \fast2_ok$200 \fus_fast2_ok$238
-    connect \dest2_o$201 \fus_dest2_o$239
-    connect \dest3_o$202 \fus_dest3_o$240
+    connect \fast2_ok$125 \fus_fast2_ok$162
+    connect \dest2_o$126 \fus_dest2_o$163
+    connect \dest3_o$127 \fus_dest3_o$164
     connect \nia_ok \fus_nia_ok
-    connect \nia_ok$203 \fus_nia_ok$241
-    connect \dest3_o$204 \fus_dest3_o$242
-    connect \dest4_o$205 \fus_dest4_o$243
+    connect \nia_ok$128 \fus_nia_ok$165
+    connect \dest3_o$129 \fus_dest3_o$166
+    connect \dest4_o$130 \fus_dest4_o$167
     connect \msr_ok \fus_msr_ok
-    connect \dest5_o$206 \fus_dest5_o$244
+    connect \dest5_o$131 \fus_dest5_o$168
     connect \spr1_ok \fus_spr1_ok
-    connect \dest2_o$207 \fus_dest2_o$245
-    connect \go_die_i \go_die_i
-    connect \shadown_i \shadown_i
-    connect \go_die_i$208 \go_die_i$131
-    connect \shadown_i$209 \shadown_i$132
-    connect \go_die_i$210 \go_die_i$133
-    connect \shadown_i$211 \shadown_i$134
-    connect \go_die_i$212 \go_die_i$135
-    connect \shadown_i$213 \shadown_i$136
-    connect \go_die_i$214 \go_die_i$137
-    connect \shadown_i$215 \shadown_i$138
-    connect \go_die_i$216 \go_die_i$139
-    connect \shadown_i$217 \shadown_i$140
-    connect \go_die_i$218 \go_die_i$141
-    connect \shadown_i$219 \shadown_i$142
-    connect \go_die_i$220 \go_die_i$143
-    connect \shadown_i$221 \shadown_i$144
-    connect \go_die_i$222 \go_die_i$145
+    connect \dest2_o$132 \fus_dest2_o$169
+    connect \cu_go_die_i \cu_go_die_i
+    connect \cu_shadown_i \cu_shadown_i
+    connect \cu_go_die_i$133 \cu_go_die_i$81
+    connect \cu_shadown_i$134 \cu_shadown_i$82
+    connect \cu_go_die_i$135 \cu_go_die_i$83
+    connect \cu_shadown_i$136 \cu_shadown_i$84
+    connect \cu_go_die_i$137 \cu_go_die_i$85
+    connect \cu_shadown_i$138 \cu_shadown_i$86
+    connect \cu_go_die_i$139 \cu_go_die_i$87
+    connect \cu_shadown_i$140 \cu_shadown_i$88
+    connect \cu_go_die_i$141 \cu_go_die_i$89
+    connect \cu_shadown_i$142 \cu_shadown_i$90
+    connect \cu_go_die_i$143 \cu_go_die_i$91
+    connect \cu_shadown_i$144 \cu_shadown_i$92
+    connect \cu_go_die_i$145 \cu_go_die_i$93
+    connect \cu_shadown_i$146 \cu_shadown_i$94
+    connect \cu_go_die_i$147 \cu_go_die_i$95
     connect \load_mem_o \load_mem_o
     connect \stwd_mem_o \stwd_mem_o
-    connect \shadown_i$223 \shadown_i$146
+    connect \cu_shadown_i$148 \cu_shadown_i$96
     connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
     connect \ldst_port0_is_st_i \ldst_port0_is_st_i
     connect \ldst_port0_data_len \ldst_port0_data_len
@@ -149202,30 +149464,30 @@ module \core
     connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
     connect \ldst_port0_st_data_i \ldst_port0_st_data_i
     connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
-    connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$147
+    connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$97
     connect \ldst_port0_busy_o \ldst_port0_busy_o
-    connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$148
-    connect \ldst_port0_data_len$3 \ldst_port0_data_len$149
-    connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$150
-    connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$151
+    connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$98
+    connect \ldst_port0_data_len$3 \ldst_port0_data_len$99
+    connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$100
+    connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$101
     connect \x_mask_i \x_mask_i
     connect \x_addr_i \x_addr_i
-    connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$152
+    connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$102
     connect \m_ld_data_o \m_ld_data_o
-    connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$153
-    connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$154
+    connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$103
+    connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$104
     connect \x_busy_o \x_busy_o
-    connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$155
-    connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$156
+    connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$105
+    connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$106
     connect \x_st_data_i \x_st_data_i
-    connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$157
+    connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$107
     connect \x_ld_i \x_ld_i
     connect \x_st_i \x_st_i
     connect \m_valid_i \m_valid_i
     connect \x_valid_i \x_valid_i
     connect \ldst_port0_go_die_i \ldst_port0_go_die_i
-    connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$158
-    connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$159
+    connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$108
+    connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$109
     connect \dbus__cyc \dbus__cyc
     connect \x_stall_i \x_stall_i
     connect \dbus__ack \dbus__ack
@@ -149259,9 +149521,9 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \int_data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_wen$246
+  wire width 32 \int_wen$170
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_data_i$247
+  wire width 64 \int_data_i$171
   cell \int \int
     connect \rst \rst
     connect \clk \clk
@@ -149273,8 +149535,8 @@ module \core
     connect \src3__data_o \int_src3__data_o
     connect \wen \int_wen
     connect \data_i \int_data_i
-    connect \wen$1 \int_wen$246
-    connect \data_i$2 \int_data_i$247
+    connect \wen$1 \int_wen$170
+    connect \data_i$2 \int_data_i$171
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \cr_full_rd__ren
@@ -149333,13 +149595,13 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 2 \xer_data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$248
+  wire width 3 \xer_wen$172
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$249
+  wire width 2 \xer_data_i$173
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$250
+  wire width 3 \xer_wen$174
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$251
+  wire width 2 \xer_data_i$175
   cell \xer \xer
     connect \rst \rst
     connect \clk \clk
@@ -149351,10 +149613,10 @@ module \core
     connect \src3__data_o \xer_src3__data_o
     connect \wen \xer_wen
     connect \data_i \xer_data_i
-    connect \wen$1 \xer_wen$248
-    connect \data_i$2 \xer_data_i$249
-    connect \wen$3 \xer_wen$250
-    connect \data_i$4 \xer_data_i$251
+    connect \wen$1 \xer_wen$172
+    connect \data_i$2 \xer_data_i$173
+    connect \wen$3 \xer_wen$174
+    connect \data_i$4 \xer_data_i$175
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \fast_src1__ren
@@ -149369,15 +149631,15 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \fast_data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$252
+  wire width 8 \fast_wen$176
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$253
+  wire width 64 \fast_data_i$177
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$254
+  wire width 64 \fast_data_i$178
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$255
+  wire width 8 \fast_wen$179
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$256
+  wire width 64 \fast_data_i$180
   cell \fast \fast
     connect \cia__ren \cia__ren
     connect \cia__data_o \cia__data_o
@@ -149394,11 +149656,11 @@ module \core
     connect \src2__data_o \fast_src2__data_o
     connect \wen$1 \fast_wen
     connect \data_i$2 \fast_data_i
-    connect \wen$3 \fast_wen$252
-    connect \data_i$4 \fast_data_i$253
-    connect \data_i$5 \fast_data_i$254
-    connect \wen$6 \fast_wen$255
-    connect \data_i$7 \fast_data_i$256
+    connect \wen$3 \fast_wen$176
+    connect \data_i$4 \fast_data_i$177
+    connect \data_i$5 \fast_data_i$178
+    connect \wen$6 \fast_wen$179
+    connect \data_i$7 \fast_data_i$180
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \spr_src__ren
@@ -149691,40 +149953,40 @@ module \core
     connect \i \wrpick_SPR_spr1_i
     connect \o \wrpick_SPR_spr1_o
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
   wire width 1 \core_stopped
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
   wire width 1 \core_stopped$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
   wire width 1 \can_run
   process $group_0
     assign \core_stopped$next \core_stopped
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105"
     switch { \core_start_i }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105"
       case 1'1
         assign \core_stopped$next 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
     switch { \core_stop_i }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
       case 1'1
         assign \core_stopped$next 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
             assign \core_stopped$next 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
         end
@@ -149732,10 +149994,10 @@ module \core
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \core_stopped$next 1'1
+        assign \core_stopped$next 1'0
     end
     sync init
-      update \core_stopped 1'1
+      update \core_stopped 1'0
     sync posedge \clk
       update \core_stopped \core_stopped$next
   end
@@ -149744,42 +150006,42 @@ module \core
     assign \core_terminated_o \core_stopped
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
-  wire width 1 $257
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
-  cell $not $258
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $181
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $not $182
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_stopped
-    connect \Y $257
+    connect \Y $181
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
-  wire width 1 $259
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
-  cell $and $260
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  wire width 1 $183
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
+  cell $and $184
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \valid
-    connect \B $257
-    connect \Y $259
+    connect \B $181
+    connect \Y $183
   end
   process $group_2
     assign \can_run 1'0
-    assign \can_run $259
+    assign \can_run $183
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
-  wire width 1 \en_alu0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $261
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $262
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $263
+  wire width 1 \en_alu0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $185
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $186
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $187
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -149787,38 +150049,38 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 2'10
-    connect \Y $262
+    connect \Y $186
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $264
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $188
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $262
-    connect \Y $261
+    connect \A $186
+    connect \Y $185
   end
   process $group_3
     assign \en_alu0 1'0
-    assign \en_alu0 $261
+    assign \en_alu0 $185
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:134"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:135"
   wire width 9 \fu_enable
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_branch0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_trap0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_logical0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_spr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_mul0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_shiftrot0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_ldst0
   process $group_4
     assign \fu_enable 9'000000000
@@ -149833,12 +150095,12 @@ module \core
     assign \fu_enable [8] \en_ldst0
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $265
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $266
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $267
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $189
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $190
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $191
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -149846,27 +150108,27 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 7'1000000
-    connect \Y $266
+    connect \Y $190
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $268
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $192
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $266
-    connect \Y $265
+    connect \A $190
+    connect \Y $189
   end
   process $group_5
     assign \en_cr0 1'0
-    assign \en_cr0 $265
+    assign \en_cr0 $189
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $269
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $270
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $271
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $193
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $194
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $195
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -149874,27 +150136,27 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 6'100000
-    connect \Y $270
+    connect \Y $194
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $272
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $196
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $270
-    connect \Y $269
+    connect \A $194
+    connect \Y $193
   end
   process $group_6
     assign \en_branch0 1'0
-    assign \en_branch0 $269
+    assign \en_branch0 $193
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $273
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $274
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $275
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $197
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $198
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $199
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -149902,27 +150164,27 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 8'10000000
-    connect \Y $274
+    connect \Y $198
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $276
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $200
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $274
-    connect \Y $273
+    connect \A $198
+    connect \Y $197
   end
   process $group_7
     assign \en_trap0 1'0
-    assign \en_trap0 $273
+    assign \en_trap0 $197
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $277
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $278
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $279
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $201
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $202
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $203
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -149930,27 +150192,27 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 5'10000
-    connect \Y $278
+    connect \Y $202
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $280
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $204
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $278
-    connect \Y $277
+    connect \A $202
+    connect \Y $201
   end
   process $group_8
     assign \en_logical0 1'0
-    assign \en_logical0 $277
+    assign \en_logical0 $201
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $281
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $282
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $283
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $205
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $206
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $207
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -149958,27 +150220,27 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 11'10000000000
-    connect \Y $282
+    connect \Y $206
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $284
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $208
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $282
-    connect \Y $281
+    connect \A $206
+    connect \Y $205
   end
   process $group_9
     assign \en_spr0 1'0
-    assign \en_spr0 $281
+    assign \en_spr0 $205
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $285
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $286
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $287
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $209
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $210
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $211
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -149986,27 +150248,27 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 9'100000000
-    connect \Y $286
+    connect \Y $210
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $288
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $212
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $286
-    connect \Y $285
+    connect \A $210
+    connect \Y $209
   end
   process $group_10
     assign \en_mul0 1'0
-    assign \en_mul0 $285
+    assign \en_mul0 $209
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $289
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $290
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $291
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $213
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $214
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $215
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -150014,27 +150276,27 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 4'1000
-    connect \Y $290
+    connect \Y $214
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $292
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $216
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $290
-    connect \Y $289
+    connect \A $214
+    connect \Y $213
   end
   process $group_11
     assign \en_shiftrot0 1'0
-    assign \en_shiftrot0 $289
+    assign \en_shiftrot0 $213
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 $293
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 11 $294
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $and $295
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 1 $217
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  wire width 11 $218
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $and $219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
@@ -150042,29 +150304,29 @@ module \core
     parameter \Y_WIDTH 11
     connect \A \fn_unit
     connect \B 3'100
-    connect \Y $294
+    connect \Y $218
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  cell $reduce_bool $296
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+  cell $reduce_bool $220
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $294
-    connect \Y $293
+    connect \A $218
+    connect \Y $217
   end
   process $group_12
     assign \en_ldst0 1'0
-    assign \en_ldst0 $293
+    assign \en_ldst0 $217
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
-  wire width 2 \counter
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
-  wire width 2 \counter$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-  wire width 1 $297
+  wire width 2 \counter
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-  cell $ne $298
+  wire width 2 \counter$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+  wire width 1 $221
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+  cell $ne $222
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -150072,14 +150334,14 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \counter
     connect \B 1'0
-    connect \Y $297
+    connect \Y $221
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  wire width 3 $299
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  wire width 3 $300
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  cell $sub $301
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
+  wire width 3 $223
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
+  wire width 3 $224
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
+  cell $sub $225
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -150087,31 +150349,31 @@ module \core
     parameter \Y_WIDTH 3
     connect \A \counter
     connect \B 1'1
-    connect \Y $300
+    connect \Y $224
   end
-  connect $299 $300
+  connect $223 $224
   process $group_13
     assign \counter$next \counter
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-    switch { $297 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+    switch { $221 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
       case 1'1
-        assign \counter$next $299 [1:0]
+        assign \counter$next $223 [1:0]
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
             assign \counter$next 2'10
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
         end
@@ -150126,10 +150388,10 @@ module \core
     sync posedge \clk
       update \counter \counter$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-  wire width 1 $302
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-  cell $ne $303
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+  wire width 1 $226
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+  cell $ne $227
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -150137,531 +150399,531 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \counter
     connect \B 1'0
-    connect \Y $302
+    connect \Y $226
   end
   process $group_14
     assign \corebusy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-    switch { $302 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+    switch { $226 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
       case 1'1
         assign \corebusy_o 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
             assign \corebusy_o 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o
+                assign \corebusy_o \cu_busy_o
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$6
+                assign \corebusy_o \cu_busy_o$2
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$14
+                assign \corebusy_o \cu_busy_o$6
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$22
+                assign \corebusy_o \cu_busy_o$9
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$36
+                assign \corebusy_o \cu_busy_o$11
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$42
+                assign \corebusy_o \cu_busy_o$13
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$53
+                assign \corebusy_o \cu_busy_o$15
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$62
+                assign \corebusy_o \cu_busy_o$17
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \busy_o$69
+                assign \corebusy_o \cu_busy_o$19
             end
         end
     end
     sync init
   end
   process $group_15
-    assign \oper_i__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type \insn_type
+                assign \oper_i_alu_alu0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_16
-    assign \oper_i__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit \fn_unit
+                assign \oper_i_alu_alu0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_17
-    assign \fus_oper_i__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__imm_data__imm_ok \fus_oper_i__imm_data__imm } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \imm_ok \imm }
             end
         end
     end
     sync init
   end
   process $group_19
-    assign \fus_oper_i__rc__rc 1'0
-    assign \fus_oper_i__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_alu0__rc__rc 1'0
+    assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__rc__rc_ok \fus_oper_i__rc__rc } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \rc_ok \rc }
             end
         end
     end
     sync init
   end
   process $group_21
-    assign \fus_oper_i__oe__oe 1'0
-    assign \fus_oper_i__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_alu0__oe__oe 1'0
+    assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__oe__oe_ok \fus_oper_i__oe__oe } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \oe_ok \oe }
             end
         end
     end
     sync init
   end
   process $group_23
-    assign \oper_i__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__invert_a \invert_a
+                assign \oper_i_alu_alu0__invert_a \invert_a
             end
         end
     end
     sync init
   end
   process $group_24
-    assign \oper_i__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__zero_a \zero_a
+                assign \oper_i_alu_alu0__zero_a \zero_a
             end
         end
     end
     sync init
   end
   process $group_25
-    assign \oper_i__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__invert_out \invert_out
+                assign \oper_i_alu_alu0__invert_out \invert_out
             end
         end
     end
     sync init
   end
   process $group_26
-    assign \oper_i__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__write_cr0 \write_cr0
+                assign \oper_i_alu_alu0__write_cr0 \write_cr0
             end
         end
     end
     sync init
   end
   process $group_27
-    assign \oper_i__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__input_carry \input_carry
+                assign \oper_i_alu_alu0__input_carry \input_carry
             end
         end
     end
     sync init
   end
   process $group_28
-    assign \oper_i__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__output_carry \output_carry
+                assign \oper_i_alu_alu0__output_carry \output_carry
             end
         end
     end
     sync init
   end
   process $group_29
-    assign \oper_i__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit \is_32bit
+                assign \oper_i_alu_alu0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_30
-    assign \oper_i__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_signed \is_signed
+                assign \oper_i_alu_alu0__is_signed \is_signed
             end
         end
     end
     sync init
   end
   process $group_31
-    assign \oper_i__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__data_len \data_len
+                assign \oper_i_alu_alu0__data_len \data_len
             end
         end
     end
     sync init
   end
   process $group_32
-    assign \oper_i__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_alu0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn \insn
+                assign \oper_i_alu_alu0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_33
-    assign \issue_i$1 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$1 \issue_i
+                assign \cu_issue_i \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 4 $304
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 4 $228
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $305
+  wire width 1 $229
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $306
+  cell $and $230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -150669,25 +150931,25 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \oe
     connect \B \oe_ok
-    connect \Y $305
+    connect \Y $229
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $307
+  wire width 1 $231
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $308
+  cell $or $232
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $305
+    connect \A $229
     connect \B \xer_in
-    connect \Y $307
+    connect \Y $231
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $309
+  wire width 1 $233
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $310
+  cell $eq $234
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -150695,1402 +150957,1402 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \input_carry
     connect \B 2'10
-    connect \Y $309
+    connect \Y $233
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $311
+  wire width 1 $235
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $312
+  cell $or $236
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $309
+    connect \A $233
     connect \B \xer_in
-    connect \Y $311
+    connect \Y $235
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $313
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $237
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A { $311 $307 \reg2_ok \reg1_ok }
-    connect \Y $304
+    connect \A { $235 $231 \reg2_ok \reg1_ok }
+    connect \Y $228
   end
   process $group_34
-    assign \fus_rdmaskn 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn $304
+                assign \fus_cu_rdmaskn_i $228
             end
         end
     end
     sync init
   end
   process $group_35
-    assign \oper_i__insn_type$2 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_cr0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$2 \insn_type
+                assign \oper_i_alu_cr0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_36
-    assign \oper_i__fn_unit$3 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_cr0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit$3 \fn_unit
+                assign \oper_i_alu_cr0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_37
-    assign \oper_i__insn$4 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_cr0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn$4 \insn
+                assign \oper_i_alu_cr0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_38
-    assign \oper_i__read_cr_whole 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_cr0__read_cr_whole 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__read_cr_whole \read_cr_whole
+                assign \oper_i_alu_cr0__read_cr_whole \read_cr_whole
             end
         end
     end
     sync init
   end
   process $group_39
-    assign \oper_i__write_cr_whole 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_cr0__write_cr_whole 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__write_cr_whole \write_cr_whole
+                assign \oper_i_alu_cr0__write_cr_whole \write_cr_whole
             end
         end
     end
     sync init
   end
   process $group_40
-    assign \issue_i$5 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$1 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$5 \issue_i
+                assign \cu_issue_i$1 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 6 $314
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $315
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 6 $238
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $239
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A { \cr_in2_ok$7 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok }
-    connect \Y $314
+    connect \A { \cr_in2_ok$3 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok }
+    connect \Y $238
   end
   process $group_41
-    assign \fus_rdmaskn$160 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$110 6'000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$160 $314
+                assign \fus_cu_rdmaskn_i$110 $238
             end
         end
     end
     sync init
   end
   process $group_42
-    assign \oper_i__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__cia \cia$8
+                assign \oper_i_alu_branch0__cia \cia$4
             end
         end
     end
     sync init
   end
   process $group_43
-    assign \oper_i__insn_type$9 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_branch0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$9 \insn_type
+                assign \oper_i_alu_branch0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_44
-    assign \oper_i__fn_unit$10 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_branch0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit$10 \fn_unit
+                assign \oper_i_alu_branch0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_45
-    assign \oper_i__insn$11 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_branch0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn$11 \insn
+                assign \oper_i_alu_branch0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_46
-    assign \fus_oper_i__imm_data__imm$161 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i__imm_data__imm_ok$162 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__imm_data__imm_ok$162 \fus_oper_i__imm_data__imm$161 } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \imm_ok \imm }
             end
         end
     end
     sync init
   end
   process $group_48
-    assign \oper_i__lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_branch0__lk 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__lk \lk
+                assign \oper_i_alu_branch0__lk \lk
             end
         end
     end
     sync init
   end
   process $group_49
-    assign \oper_i__is_32bit$12 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_branch0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit$12 \is_32bit
+                assign \oper_i_alu_branch0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_50
-    assign \issue_i$13 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$5 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$13 \issue_i
+                assign \cu_issue_i$5 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 3 $316
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $317
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 3 $240
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $241
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A { \cr_in1_ok \fast2_ok \fast1_ok }
-    connect \Y $316
+    connect \Y $240
   end
   process $group_51
-    assign \fus_rdmaskn$163 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$111 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$163 $316
+                assign \fus_cu_rdmaskn_i$111 $240
             end
         end
     end
     sync init
   end
   process $group_52
-    assign \oper_i__insn_type$15 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$15 \insn_type
+                assign \oper_i_alu_trap0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_53
-    assign \oper_i__fn_unit$16 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit$16 \fn_unit
+                assign \oper_i_alu_trap0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_54
-    assign \oper_i__insn$17 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn$17 \insn
+                assign \oper_i_alu_trap0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_55
-    assign \oper_i__msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__msr \msr$18
+                assign \oper_i_alu_trap0__msr \msr$7
             end
         end
     end
     sync init
   end
   process $group_56
-    assign \oper_i__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__cia$19 \cia$8
+                assign \oper_i_alu_trap0__cia \cia$4
             end
         end
     end
     sync init
   end
   process $group_57
-    assign \oper_i__is_32bit$20 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit$20 \is_32bit
+                assign \oper_i_alu_trap0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_58
-    assign \oper_i__traptype 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__traptype 5'00000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__traptype \traptype
+                assign \oper_i_alu_trap0__traptype \traptype
             end
         end
     end
     sync init
   end
   process $group_59
-    assign \oper_i__trapaddr 13'0000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_trap0__trapaddr 13'0000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__trapaddr \trapaddr
+                assign \oper_i_alu_trap0__trapaddr \trapaddr
             end
         end
     end
     sync init
   end
   process $group_60
-    assign \issue_i$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$8 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$21 \issue_i
+                assign \cu_issue_i$8 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 4 $318
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $319
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 4 $242
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $243
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
     connect \A { \fast2_ok \fast1_ok \reg2_ok \reg1_ok }
-    connect \Y $318
+    connect \Y $242
   end
   process $group_61
-    assign \fus_rdmaskn$164 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$112 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$164 $318
+                assign \fus_cu_rdmaskn_i$112 $242
             end
         end
     end
     sync init
   end
   process $group_62
-    assign \oper_i__insn_type$23 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$23 \insn_type
+                assign \oper_i_alu_logical0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_63
-    assign \oper_i__fn_unit$24 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit$24 \fn_unit
+                assign \oper_i_alu_logical0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_64
-    assign \fus_oper_i__imm_data__imm$165 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i__imm_data__imm_ok$166 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__imm_data__imm_ok$166 \fus_oper_i__imm_data__imm$165 } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \imm_ok \imm }
             end
         end
     end
     sync init
   end
   process $group_66
-    assign \fus_oper_i__rc__rc$167 1'0
-    assign \fus_oper_i__rc__rc_ok$168 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_logical0__rc__rc 1'0
+    assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__rc__rc_ok$168 \fus_oper_i__rc__rc$167 } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \rc_ok \rc }
             end
         end
     end
     sync init
   end
   process $group_68
-    assign \fus_oper_i__oe__oe$169 1'0
-    assign \fus_oper_i__oe__oe_ok$170 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_logical0__oe__oe 1'0
+    assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__oe__oe_ok$170 \fus_oper_i__oe__oe$169 } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \oe_ok \oe }
             end
         end
     end
     sync init
   end
   process $group_70
-    assign \oper_i__invert_a$25 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__invert_a$25 \invert_a
+                assign \oper_i_alu_logical0__invert_a \invert_a
             end
         end
     end
     sync init
   end
   process $group_71
-    assign \oper_i__zero_a$26 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__zero_a$26 \zero_a
+                assign \oper_i_alu_logical0__zero_a \zero_a
             end
         end
     end
     sync init
   end
   process $group_72
-    assign \oper_i__input_carry$27 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__input_carry$27 \input_carry
+                assign \oper_i_alu_logical0__input_carry \input_carry
             end
         end
     end
     sync init
   end
   process $group_73
-    assign \oper_i__invert_out$28 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__invert_out$28 \invert_out
+                assign \oper_i_alu_logical0__invert_out \invert_out
             end
         end
     end
     sync init
   end
   process $group_74
-    assign \oper_i__write_cr0$29 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__write_cr0$29 \write_cr0
+                assign \oper_i_alu_logical0__write_cr0 \write_cr0
             end
         end
     end
     sync init
   end
   process $group_75
-    assign \oper_i__output_carry$30 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__output_carry$30 \output_carry
+                assign \oper_i_alu_logical0__output_carry \output_carry
             end
         end
     end
     sync init
   end
   process $group_76
-    assign \oper_i__is_32bit$31 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit$31 \is_32bit
+                assign \oper_i_alu_logical0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_77
-    assign \oper_i__is_signed$32 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_signed$32 \is_signed
+                assign \oper_i_alu_logical0__is_signed \is_signed
             end
         end
     end
     sync init
   end
   process $group_78
-    assign \oper_i__data_len$33 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__data_len$33 \data_len
+                assign \oper_i_alu_logical0__data_len \data_len
             end
         end
     end
     sync init
   end
   process $group_79
-    assign \oper_i__insn$34 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_logical0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn$34 \insn
+                assign \oper_i_alu_logical0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_80
-    assign \issue_i$35 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$10 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$35 \issue_i
+                assign \cu_issue_i$10 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 2 $320
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $321
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 2 $244
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $245
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A { \reg2_ok \reg1_ok }
-    connect \Y $320
+    connect \Y $244
   end
   process $group_81
-    assign \fus_rdmaskn$171 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$113 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$171 $320
+                assign \fus_cu_rdmaskn_i$113 $244
             end
         end
     end
     sync init
   end
   process $group_82
-    assign \oper_i__insn_type$37 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_spr0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$37 \insn_type
+                assign \oper_i_alu_spr0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_83
-    assign \oper_i__fn_unit$38 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_spr0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit$38 \fn_unit
+                assign \oper_i_alu_spr0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_84
-    assign \oper_i__insn$39 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_spr0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn$39 \insn
+                assign \oper_i_alu_spr0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_85
-    assign \oper_i__is_32bit$40 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_spr0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit$40 \is_32bit
+                assign \oper_i_alu_spr0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_86
-    assign \issue_i$41 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$12 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$41 \issue_i
+                assign \cu_issue_i$12 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 6 $322
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 6 $246
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $323
+  wire width 1 $247
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $324
+  cell $and $248
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -152098,25 +152360,25 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \oe
     connect \B \oe_ok
-    connect \Y $323
+    connect \Y $247
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $325
+  wire width 1 $249
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $326
+  cell $or $250
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $323
+    connect \A $247
     connect \B \xer_in
-    connect \Y $325
+    connect \Y $249
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $327
+  wire width 1 $251
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $and $328
+  cell $and $252
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -152124,25 +152386,25 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \oe
     connect \B \oe_ok
-    connect \Y $327
+    connect \Y $251
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $329
+  wire width 1 $253
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $or $330
+  cell $or $254
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $327
+    connect \A $251
     connect \B \xer_in
-    connect \Y $329
+    connect \Y $253
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $331
+  wire width 1 $255
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $332
+  cell $eq $256
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -152150,416 +152412,416 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \input_carry
     connect \B 2'10
-    connect \Y $331
+    connect \Y $255
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $333
+  wire width 1 $257
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $334
+  cell $or $258
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $331
+    connect \A $255
     connect \B \xer_in
-    connect \Y $333
+    connect \Y $257
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $335
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $259
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A { $333 $329 $325 \fast1_ok \spr1_ok \reg1_ok }
-    connect \Y $322
+    connect \A { $257 $253 $249 \fast1_ok \spr1_ok \reg1_ok }
+    connect \Y $246
   end
   process $group_87
-    assign \fus_rdmaskn$172 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$114 6'000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$172 $322
+                assign \fus_cu_rdmaskn_i$114 $246
             end
         end
     end
     sync init
   end
   process $group_88
-    assign \oper_i__insn_type$43 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$43 \insn_type
+                assign \oper_i_alu_mul0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_89
-    assign \oper_i__fn_unit$44 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit$44 \fn_unit
+                assign \oper_i_alu_mul0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_90
-    assign \fus_oper_i__imm_data__imm$173 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i__imm_data__imm_ok$174 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__imm_data__imm_ok$174 \fus_oper_i__imm_data__imm$173 } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \imm_ok \imm }
             end
         end
     end
     sync init
   end
   process $group_92
-    assign \fus_oper_i__rc__rc$175 1'0
-    assign \fus_oper_i__rc__rc_ok$176 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_mul0__rc__rc 1'0
+    assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__rc__rc_ok$176 \fus_oper_i__rc__rc$175 } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \rc_ok \rc }
             end
         end
     end
     sync init
   end
   process $group_94
-    assign \fus_oper_i__oe__oe$177 1'0
-    assign \fus_oper_i__oe__oe_ok$178 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_mul0__oe__oe 1'0
+    assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__oe__oe_ok$178 \fus_oper_i__oe__oe$177 } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \oe_ok \oe }
             end
         end
     end
     sync init
   end
   process $group_96
-    assign \oper_i__invert_a$45 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__invert_a$45 \invert_a
+                assign \oper_i_alu_mul0__invert_a \invert_a
             end
         end
     end
     sync init
   end
   process $group_97
-    assign \oper_i__zero_a$46 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__zero_a$46 \zero_a
+                assign \oper_i_alu_mul0__zero_a \zero_a
             end
         end
     end
     sync init
   end
   process $group_98
-    assign \oper_i__invert_out$47 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__invert_out$47 \invert_out
+                assign \oper_i_alu_mul0__invert_out \invert_out
             end
         end
     end
     sync init
   end
   process $group_99
-    assign \oper_i__write_cr0$48 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__write_cr0$48 \write_cr0
+                assign \oper_i_alu_mul0__write_cr0 \write_cr0
             end
         end
     end
     sync init
   end
   process $group_100
-    assign \oper_i__is_32bit$49 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit$49 \is_32bit
+                assign \oper_i_alu_mul0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_101
-    assign \oper_i__is_signed$50 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_signed$50 \is_signed
+                assign \oper_i_alu_mul0__is_signed \is_signed
             end
         end
     end
     sync init
   end
   process $group_102
-    assign \oper_i__insn$51 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_mul0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn$51 \insn
+                assign \oper_i_alu_mul0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_103
-    assign \issue_i$52 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$52 \issue_i
+                assign \cu_issue_i$14 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 3 $336
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 3 $260
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $337
+  wire width 1 $261
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $338
+  cell $and $262
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -152567,189 +152829,189 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \oe
     connect \B \oe_ok
-    connect \Y $337
+    connect \Y $261
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $339
+  wire width 1 $263
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $340
+  cell $or $264
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $337
+    connect \A $261
     connect \B \xer_in
-    connect \Y $339
+    connect \Y $263
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $341
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $265
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A { $339 \reg2_ok \reg1_ok }
-    connect \Y $336
+    connect \A { $263 \reg2_ok \reg1_ok }
+    connect \Y $260
   end
   process $group_104
-    assign \fus_rdmaskn$179 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$115 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$179 $336
+                assign \fus_cu_rdmaskn_i$115 $260
             end
         end
     end
     sync init
   end
   process $group_105
-    assign \oper_i__insn_type$54 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$54 \insn_type
+                assign \oper_i_alu_shift_rot0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_106
-    assign \oper_i__fn_unit$55 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__fn_unit$55 \fn_unit
+                assign \oper_i_alu_shift_rot0__fn_unit \fn_unit
             end
         end
     end
     sync init
   end
   process $group_107
-    assign \fus_oper_i__imm_data__imm$180 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i__imm_data__imm_ok$181 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__imm_data__imm_ok$181 \fus_oper_i__imm_data__imm$180 } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \imm_ok \imm }
             end
         end
     end
     sync init
   end
   process $group_109
-    assign \fus_oper_i__rc__rc$182 1'0
-    assign \fus_oper_i__rc__rc_ok$183 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0
+    assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__rc__rc_ok$183 \fus_oper_i__rc__rc$182 } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \rc_ok \rc }
             end
         end
     end
     sync init
   end
   process $group_111
-    assign \fus_oper_i__oe__oe$184 1'0
-    assign \fus_oper_i__oe__oe_ok$185 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0
+    assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__oe__oe_ok$185 \fus_oper_i__oe__oe$184 } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \oe_ok \oe }
             end
         end
     end
@@ -152757,24 +153019,24 @@ module \core
   end
   process $group_113
     assign { } 0'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
                 assign { } {}
             end
@@ -152783,227 +153045,227 @@ module \core
     sync init
   end
   process $group_114
-    assign \oper_i__input_carry$56 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__input_carry$56 \input_carry
+                assign \oper_i_alu_shift_rot0__input_carry \input_carry
             end
         end
     end
     sync init
   end
   process $group_115
-    assign \oper_i__output_carry$57 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__output_carry$57 \output_carry
+                assign \oper_i_alu_shift_rot0__output_carry \output_carry
             end
         end
     end
     sync init
   end
   process $group_116
-    assign \oper_i__input_cr 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__input_cr 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__input_cr \input_cr
+                assign \oper_i_alu_shift_rot0__input_cr \input_cr
             end
         end
     end
     sync init
   end
   process $group_117
-    assign \oper_i__output_cr 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__output_cr 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__output_cr \output_cr
+                assign \oper_i_alu_shift_rot0__output_cr \output_cr
             end
         end
     end
     sync init
   end
   process $group_118
-    assign \oper_i__is_32bit$58 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit$58 \is_32bit
+                assign \oper_i_alu_shift_rot0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_119
-    assign \oper_i__is_signed$59 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_signed$59 \is_signed
+                assign \oper_i_alu_shift_rot0__is_signed \is_signed
             end
         end
     end
     sync init
   end
   process $group_120
-    assign \oper_i__insn$60 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn$60 \insn
+                assign \oper_i_alu_shift_rot0__insn \insn
             end
         end
     end
     sync init
   end
   process $group_121
-    assign \issue_i$61 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$16 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$61 \issue_i
+                assign \cu_issue_i$16 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 4 $342
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 4 $266
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $343
+  wire width 1 $267
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $344
+  cell $eq $268
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -153011,421 +153273,421 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \input_carry
     connect \B 2'10
-    connect \Y $343
+    connect \Y $267
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $345
+  wire width 1 $269
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $346
+  cell $or $270
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $343
+    connect \A $267
     connect \B \xer_in
-    connect \Y $345
+    connect \Y $269
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $347
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $271
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A { $345 \reg3_ok \reg2_ok \reg1_ok }
-    connect \Y $342
+    connect \A { $269 \reg3_ok \reg2_ok \reg1_ok }
+    connect \Y $266
   end
   process $group_122
-    assign \fus_rdmaskn$186 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$116 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$186 $342
+                assign \fus_cu_rdmaskn_i$116 $266
             end
         end
     end
     sync init
   end
   process $group_123
-    assign \oper_i__insn_type$63 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__insn_type$63 \insn_type
+                assign \oper_i_ldst_ldst0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_124
-    assign \fus_oper_i__imm_data__imm$187 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i__imm_data__imm_ok$188 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__imm_data__imm_ok$188 \fus_oper_i__imm_data__imm$187 } { \imm_ok \imm }
+                assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \imm_ok \imm }
             end
         end
     end
     sync init
   end
   process $group_126
-    assign \oper_i__zero_a$64 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__zero_a$64 \zero_a
+                assign \oper_i_ldst_ldst0__zero_a \zero_a
             end
         end
     end
     sync init
   end
   process $group_127
-    assign \fus_oper_i__rc__rc$189 1'0
-    assign \fus_oper_i__rc__rc_ok$190 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_ldst_ldst0__rc__rc 1'0
+    assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__rc__rc_ok$190 \fus_oper_i__rc__rc$189 } { \rc_ok \rc }
+                assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \rc_ok \rc }
             end
         end
     end
     sync init
   end
   process $group_129
-    assign \fus_oper_i__oe__oe$191 1'0
-    assign \fus_oper_i__oe__oe_ok$192 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_oper_i_ldst_ldst0__oe__oe 1'0
+    assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i__oe__oe_ok$192 \fus_oper_i__oe__oe$191 } { \oe_ok \oe }
+                assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \oe_ok \oe }
             end
         end
     end
     sync init
   end
   process $group_131
-    assign \oper_i__is_32bit$65 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_32bit$65 \is_32bit
+                assign \oper_i_ldst_ldst0__is_32bit \is_32bit
             end
         end
     end
     sync init
   end
   process $group_132
-    assign \oper_i__is_signed$66 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__is_signed$66 \is_signed
+                assign \oper_i_ldst_ldst0__is_signed \is_signed
             end
         end
     end
     sync init
   end
   process $group_133
-    assign \oper_i__data_len$67 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__data_len$67 \data_len
+                assign \oper_i_ldst_ldst0__data_len \data_len
             end
         end
     end
     sync init
   end
   process $group_134
-    assign \oper_i__byte_reverse 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__byte_reverse 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__byte_reverse \byte_reverse
+                assign \oper_i_ldst_ldst0__byte_reverse \byte_reverse
             end
         end
     end
     sync init
   end
   process $group_135
-    assign \oper_i__sign_extend 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__sign_extend 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__sign_extend \sign_extend
+                assign \oper_i_ldst_ldst0__sign_extend \sign_extend
             end
         end
     end
     sync init
   end
   process $group_136
-    assign \oper_i__ldst_mode 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \oper_i_ldst_ldst0__ldst_mode 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i__ldst_mode \ldst_mode
+                assign \oper_i_ldst_ldst0__ldst_mode \ldst_mode
             end
         end
     end
     sync init
   end
   process $group_137
-    assign \issue_i$68 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \cu_issue_i$18 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \issue_i$68 \issue_i
+                assign \cu_issue_i$18 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  wire width 3 $348
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
-  cell $not $349
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  wire width 3 $272
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
+  cell $not $273
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
     connect \A { \reg3_ok \reg2_ok \reg1_ok }
-    connect \Y $348
+    connect \Y $272
   end
   process $group_138
-    assign \fus_rdmaskn$193 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+    assign \fus_cu_rdmaskn_i$117 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_rdmaskn$193 $348
+                assign \fus_cu_rdmaskn_i$117 $272
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_INT_ra
   process $group_139
     assign \rdflag_INT_ra 1'0
@@ -153433,9 +153695,9 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  wire width 32 $350
+  wire width 32 $274
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  cell $sshl $351
+  cell $sshl $275
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -153443,244 +153705,244 @@ module \core
     parameter \Y_WIDTH 32
     connect \A 1'1
     connect \B \reg1
-    connect \Y $350
+    connect \Y $274
   end
   process $group_140
     assign \int_src1__ren 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_INT_ra_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \int_src1__ren $350
+        assign \int_src1__ren $274
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $352
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $353
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $276
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $277
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel [0]
+    connect \A \cu_rd__rel_o [0]
     connect \B \fu_enable [0]
-    connect \Y $352
+    connect \Y $276
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $354
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $355
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $278
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $279
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $352
+    connect \A $276
     connect \B \rdflag_INT_ra
-    connect \Y $354
+    connect \Y $278
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $356
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $357
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $280
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $281
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$70 [0]
+    connect \A \cu_rd__rel_o$20 [0]
     connect \B \fu_enable [1]
-    connect \Y $356
+    connect \Y $280
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $358
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $359
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $282
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $283
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $356
+    connect \A $280
     connect \B \rdflag_INT_ra
-    connect \Y $358
+    connect \Y $282
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $360
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $361
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $284
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $285
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$73 [0]
+    connect \A \cu_rd__rel_o$23 [0]
     connect \B \fu_enable [3]
-    connect \Y $360
+    connect \Y $284
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $362
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $363
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $286
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $287
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $360
+    connect \A $284
     connect \B \rdflag_INT_ra
-    connect \Y $362
+    connect \Y $286
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $364
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $365
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $288
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $289
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$76 [0]
+    connect \A \cu_rd__rel_o$26 [0]
     connect \B \fu_enable [4]
-    connect \Y $364
+    connect \Y $288
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $366
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $367
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $290
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $291
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $364
+    connect \A $288
     connect \B \rdflag_INT_ra
-    connect \Y $366
+    connect \Y $290
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $368
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $369
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $292
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $293
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$79 [0]
+    connect \A \cu_rd__rel_o$29 [0]
     connect \B \fu_enable [5]
-    connect \Y $368
+    connect \Y $292
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $370
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $371
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $294
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $295
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $368
+    connect \A $292
     connect \B \rdflag_INT_ra
-    connect \Y $370
+    connect \Y $294
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $372
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $373
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $296
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $297
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$82 [0]
+    connect \A \cu_rd__rel_o$32 [0]
     connect \B \fu_enable [6]
-    connect \Y $372
+    connect \Y $296
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $374
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $375
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $298
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $299
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $372
+    connect \A $296
     connect \B \rdflag_INT_ra
-    connect \Y $374
+    connect \Y $298
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $376
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $377
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $300
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $301
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$85 [0]
+    connect \A \cu_rd__rel_o$35 [0]
     connect \B \fu_enable [7]
-    connect \Y $376
+    connect \Y $300
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $378
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $379
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $302
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $303
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $376
+    connect \A $300
     connect \B \rdflag_INT_ra
-    connect \Y $378
+    connect \Y $302
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $380
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $381
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $304
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $305
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$88 [0]
+    connect \A \cu_rd__rel_o$38 [0]
     connect \B \fu_enable [8]
-    connect \Y $380
+    connect \Y $304
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $382
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $383
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $306
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $307
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $380
+    connect \A $304
     connect \B \rdflag_INT_ra
-    connect \Y $382
+    connect \Y $306
   end
   process $group_141
     assign \rdpick_INT_ra_i 8'00000000
-    assign \rdpick_INT_ra_i [0] $354
-    assign \rdpick_INT_ra_i [1] $358
-    assign \rdpick_INT_ra_i [2] $362
-    assign \rdpick_INT_ra_i [3] $366
-    assign \rdpick_INT_ra_i [4] $370
-    assign \rdpick_INT_ra_i [5] $374
-    assign \rdpick_INT_ra_i [6] $378
-    assign \rdpick_INT_ra_i [7] $382
+    assign \rdpick_INT_ra_i [0] $278
+    assign \rdpick_INT_ra_i [1] $282
+    assign \rdpick_INT_ra_i [2] $286
+    assign \rdpick_INT_ra_i [3] $290
+    assign \rdpick_INT_ra_i [4] $294
+    assign \rdpick_INT_ra_i [5] $298
+    assign \rdpick_INT_ra_i [6] $302
+    assign \rdpick_INT_ra_i [7] $306
     sync init
   end
   process $group_142
-    assign \rd__go 4'0000
-    assign \rd__go [0] \rdpick_INT_ra_o [0]
-    assign \rd__go [1] \rdpick_INT_rb_o [0]
-    assign \rd__go [2] \rdpick_XER_xer_so_o [0]
-    assign \rd__go [3] \rdpick_XER_xer_ca_o [0]
+    assign \cu_rd__go_i 4'0000
+    assign \cu_rd__go_i [0] \rdpick_INT_ra_o [0]
+    assign \cu_rd__go_i [1] \rdpick_INT_rb_o [0]
+    assign \cu_rd__go_i [2] \rdpick_XER_xer_so_o [0]
+    assign \cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0]
     sync init
   end
   process $group_143
@@ -153689,97 +153951,97 @@ module \core
     sync init
   end
   process $group_144
-    assign \rd__go$71 6'000000
-    assign \rd__go$71 [0] \rdpick_INT_ra_o [1]
-    assign \rd__go$71 [1] \rdpick_INT_rb_o [1]
-    assign \rd__go$71 [2] \rdpick_CR_full_cr_o
-    assign \rd__go$71 [3] \rdpick_CR_cr_a_o [0]
-    assign \rd__go$71 [4] \rdpick_CR_cr_b_o
-    assign \rd__go$71 [5] \rdpick_CR_cr_c_o
+    assign \cu_rd__go_i$21 6'000000
+    assign \cu_rd__go_i$21 [0] \rdpick_INT_ra_o [1]
+    assign \cu_rd__go_i$21 [1] \rdpick_INT_rb_o [1]
+    assign \cu_rd__go_i$21 [2] \rdpick_CR_full_cr_o
+    assign \cu_rd__go_i$21 [3] \rdpick_CR_cr_a_o [0]
+    assign \cu_rd__go_i$21 [4] \rdpick_CR_cr_b_o
+    assign \cu_rd__go_i$21 [5] \rdpick_CR_cr_c_o
     sync init
   end
   process $group_145
-    assign \src1_i$72 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$72 \int_src1__data_o
+    assign \src1_i$22 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$22 \int_src1__data_o
     sync init
   end
   process $group_146
-    assign \rd__go$74 4'0000
-    assign \rd__go$74 [0] \rdpick_INT_ra_o [2]
-    assign \rd__go$74 [1] \rdpick_INT_rb_o [2]
-    assign \rd__go$74 [2] \rdpick_FAST_fast1_o [1]
-    assign \rd__go$74 [3] \rdpick_FAST_fast2_o [1]
+    assign \cu_rd__go_i$24 4'0000
+    assign \cu_rd__go_i$24 [0] \rdpick_INT_ra_o [2]
+    assign \cu_rd__go_i$24 [1] \rdpick_INT_rb_o [2]
+    assign \cu_rd__go_i$24 [2] \rdpick_FAST_fast1_o [1]
+    assign \cu_rd__go_i$24 [3] \rdpick_FAST_fast2_o [1]
     sync init
   end
   process $group_147
-    assign \src1_i$75 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$75 \int_src1__data_o
+    assign \src1_i$25 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$25 \int_src1__data_o
     sync init
   end
   process $group_148
-    assign \rd__go$77 2'00
-    assign \rd__go$77 [0] \rdpick_INT_ra_o [3]
-    assign \rd__go$77 [1] \rdpick_INT_rb_o [3]
+    assign \cu_rd__go_i$27 2'00
+    assign \cu_rd__go_i$27 [0] \rdpick_INT_ra_o [3]
+    assign \cu_rd__go_i$27 [1] \rdpick_INT_rb_o [3]
     sync init
   end
   process $group_149
-    assign \src1_i$78 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$78 \int_src1__data_o
+    assign \src1_i$28 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$28 \int_src1__data_o
     sync init
   end
   process $group_150
-    assign \rd__go$80 6'000000
-    assign \rd__go$80 [0] \rdpick_INT_ra_o [4]
-    assign \rd__go$80 [3] \rdpick_XER_xer_so_o [1]
-    assign \rd__go$80 [5] \rdpick_XER_xer_ca_o [1]
-    assign \rd__go$80 [4] \rdpick_XER_xer_ov_o
-    assign \rd__go$80 [2] \rdpick_FAST_fast1_o [2]
-    assign \rd__go$80 [1] \rdpick_SPR_spr1_o
+    assign \cu_rd__go_i$30 6'000000
+    assign \cu_rd__go_i$30 [0] \rdpick_INT_ra_o [4]
+    assign \cu_rd__go_i$30 [3] \rdpick_XER_xer_so_o [1]
+    assign \cu_rd__go_i$30 [5] \rdpick_XER_xer_ca_o [1]
+    assign \cu_rd__go_i$30 [4] \rdpick_XER_xer_ov_o
+    assign \cu_rd__go_i$30 [2] \rdpick_FAST_fast1_o [2]
+    assign \cu_rd__go_i$30 [1] \rdpick_SPR_spr1_o
     sync init
   end
   process $group_151
-    assign \src1_i$81 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$81 \int_src1__data_o
+    assign \src1_i$31 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$31 \int_src1__data_o
     sync init
   end
   process $group_152
-    assign \rd__go$83 3'000
-    assign \rd__go$83 [0] \rdpick_INT_ra_o [5]
-    assign \rd__go$83 [1] \rdpick_INT_rb_o [4]
-    assign \rd__go$83 [2] \rdpick_XER_xer_so_o [2]
+    assign \cu_rd__go_i$33 3'000
+    assign \cu_rd__go_i$33 [0] \rdpick_INT_ra_o [5]
+    assign \cu_rd__go_i$33 [1] \rdpick_INT_rb_o [4]
+    assign \cu_rd__go_i$33 [2] \rdpick_XER_xer_so_o [2]
     sync init
   end
   process $group_153
-    assign \src1_i$84 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$84 \int_src1__data_o
+    assign \src1_i$34 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$34 \int_src1__data_o
     sync init
   end
   process $group_154
-    assign \rd__go$86 4'0000
-    assign \rd__go$86 [0] \rdpick_INT_ra_o [6]
-    assign \rd__go$86 [1] \rdpick_INT_rb_o [5]
-    assign \rd__go$86 [2] \rdpick_INT_rc_o [0]
-    assign \rd__go$86 [3] \rdpick_XER_xer_ca_o [2]
+    assign \cu_rd__go_i$36 4'0000
+    assign \cu_rd__go_i$36 [0] \rdpick_INT_ra_o [6]
+    assign \cu_rd__go_i$36 [1] \rdpick_INT_rb_o [5]
+    assign \cu_rd__go_i$36 [2] \rdpick_INT_rc_o [0]
+    assign \cu_rd__go_i$36 [3] \rdpick_XER_xer_ca_o [2]
     sync init
   end
   process $group_155
-    assign \src1_i$87 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$87 \int_src1__data_o
+    assign \src1_i$37 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$37 \int_src1__data_o
     sync init
   end
   process $group_156
-    assign \rd__go$89 3'000
-    assign \rd__go$89 [0] \rdpick_INT_ra_o [7]
-    assign \rd__go$89 [1] \rdpick_INT_rb_o [6]
-    assign \rd__go$89 [2] \rdpick_INT_rc_o [1]
+    assign \cu_rd__go_i$39 3'000
+    assign \cu_rd__go_i$39 [0] \rdpick_INT_ra_o [7]
+    assign \cu_rd__go_i$39 [1] \rdpick_INT_rb_o [6]
+    assign \cu_rd__go_i$39 [2] \rdpick_INT_rc_o [1]
     sync init
   end
   process $group_157
-    assign \src1_i$90 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$90 \int_src1__data_o
+    assign \src1_i$40 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$40 \int_src1__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_INT_rb
   process $group_158
     assign \rdflag_INT_rb 1'0
@@ -153787,9 +154049,9 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
-  wire width 32 $384
+  wire width 32 $308
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
-  cell $sshl $385
+  cell $sshl $309
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -153797,209 +154059,209 @@ module \core
     parameter \Y_WIDTH 32
     connect \A 1'1
     connect \B \reg2
-    connect \Y $384
+    connect \Y $308
   end
   process $group_159
     assign \int_src2__ren 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_INT_rb_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \int_src2__ren $384
+        assign \int_src2__ren $308
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $386
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $387
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $310
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $311
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel [1]
+    connect \A \cu_rd__rel_o [1]
     connect \B \fu_enable [0]
-    connect \Y $386
+    connect \Y $310
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $388
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $389
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $312
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $313
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $386
+    connect \A $310
     connect \B \rdflag_INT_rb
-    connect \Y $388
+    connect \Y $312
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $390
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $391
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $314
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $315
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$70 [1]
+    connect \A \cu_rd__rel_o$20 [1]
     connect \B \fu_enable [1]
-    connect \Y $390
+    connect \Y $314
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $392
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $393
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $316
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $317
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $390
+    connect \A $314
     connect \B \rdflag_INT_rb
-    connect \Y $392
+    connect \Y $316
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $394
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $395
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $318
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $319
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$73 [1]
+    connect \A \cu_rd__rel_o$23 [1]
     connect \B \fu_enable [3]
-    connect \Y $394
+    connect \Y $318
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $396
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $397
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $320
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $321
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $394
+    connect \A $318
     connect \B \rdflag_INT_rb
-    connect \Y $396
+    connect \Y $320
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $398
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $399
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $322
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $323
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$76 [1]
+    connect \A \cu_rd__rel_o$26 [1]
     connect \B \fu_enable [4]
-    connect \Y $398
+    connect \Y $322
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $400
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $401
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $324
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $325
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $398
+    connect \A $322
     connect \B \rdflag_INT_rb
-    connect \Y $400
+    connect \Y $324
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $402
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $403
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $326
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $327
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$82 [1]
+    connect \A \cu_rd__rel_o$32 [1]
     connect \B \fu_enable [6]
-    connect \Y $402
+    connect \Y $326
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $404
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $405
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $328
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $329
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $402
+    connect \A $326
     connect \B \rdflag_INT_rb
-    connect \Y $404
+    connect \Y $328
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $406
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $407
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $330
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $331
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$85 [1]
+    connect \A \cu_rd__rel_o$35 [1]
     connect \B \fu_enable [7]
-    connect \Y $406
+    connect \Y $330
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $408
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $409
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $332
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $333
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $406
+    connect \A $330
     connect \B \rdflag_INT_rb
-    connect \Y $408
+    connect \Y $332
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $410
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $411
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $334
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $335
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$88 [1]
+    connect \A \cu_rd__rel_o$38 [1]
     connect \B \fu_enable [8]
-    connect \Y $410
+    connect \Y $334
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $412
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $413
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $336
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $337
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $410
+    connect \A $334
     connect \B \rdflag_INT_rb
-    connect \Y $412
+    connect \Y $336
   end
   process $group_160
     assign \rdpick_INT_rb_i 7'0000000
-    assign \rdpick_INT_rb_i [0] $388
-    assign \rdpick_INT_rb_i [1] $392
-    assign \rdpick_INT_rb_i [2] $396
-    assign \rdpick_INT_rb_i [3] $400
-    assign \rdpick_INT_rb_i [4] $404
-    assign \rdpick_INT_rb_i [5] $408
-    assign \rdpick_INT_rb_i [6] $412
+    assign \rdpick_INT_rb_i [0] $312
+    assign \rdpick_INT_rb_i [1] $316
+    assign \rdpick_INT_rb_i [2] $320
+    assign \rdpick_INT_rb_i [3] $324
+    assign \rdpick_INT_rb_i [4] $328
+    assign \rdpick_INT_rb_i [5] $332
+    assign \rdpick_INT_rb_i [6] $336
     sync init
   end
   process $group_161
@@ -154008,36 +154270,36 @@ module \core
     sync init
   end
   process $group_162
-    assign \src2_i$91 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$91 \int_src2__data_o
+    assign \src2_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$41 \int_src2__data_o
     sync init
   end
   process $group_163
-    assign \src2_i$92 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$92 \int_src2__data_o
+    assign \src2_i$42 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$42 \int_src2__data_o
     sync init
   end
   process $group_164
-    assign \src2_i$93 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$93 \int_src2__data_o
+    assign \src2_i$43 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$43 \int_src2__data_o
     sync init
   end
   process $group_165
-    assign \src2_i$94 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$94 \int_src2__data_o
+    assign \src2_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$44 \int_src2__data_o
     sync init
   end
   process $group_166
-    assign \src2_i$95 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$95 \int_src2__data_o
+    assign \src2_i$45 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$45 \int_src2__data_o
     sync init
   end
   process $group_167
-    assign \src2_i$96 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$96 \int_src2__data_o
+    assign \src2_i$46 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$46 \int_src2__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_INT_rc
   process $group_168
     assign \rdflag_INT_rc 1'0
@@ -154045,9 +154307,9 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
-  wire width 32 $414
+  wire width 32 $338
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
-  cell $sshl $415
+  cell $sshl $339
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -154055,74 +154317,74 @@ module \core
     parameter \Y_WIDTH 32
     connect \A 1'1
     connect \B \reg3
-    connect \Y $414
+    connect \Y $338
   end
   process $group_169
     assign \int_src3__ren 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_INT_rc_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \int_src3__ren $414
+        assign \int_src3__ren $338
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $416
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $417
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $340
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $341
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$85 [2]
+    connect \A \cu_rd__rel_o$35 [2]
     connect \B \fu_enable [7]
-    connect \Y $416
+    connect \Y $340
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $418
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $419
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $342
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $343
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $416
+    connect \A $340
     connect \B \rdflag_INT_rc
-    connect \Y $418
+    connect \Y $342
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $420
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $421
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $344
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $345
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$88 [2]
+    connect \A \cu_rd__rel_o$38 [2]
     connect \B \fu_enable [8]
-    connect \Y $420
+    connect \Y $344
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $422
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $423
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $346
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $347
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $420
+    connect \A $344
     connect \B \rdflag_INT_rc
-    connect \Y $422
+    connect \Y $346
   end
   process $group_170
     assign \rdpick_INT_rc_i 2'00
-    assign \rdpick_INT_rc_i [0] $418
-    assign \rdpick_INT_rc_i [1] $422
+    assign \rdpick_INT_rc_i [0] $342
+    assign \rdpick_INT_rc_i [1] $346
     sync init
   end
   process $group_171
@@ -154135,12 +154397,12 @@ module \core
     assign \src3_i \int_src3__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_XER_xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $424
+  wire width 1 $348
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $425
+  cell $and $349
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -154148,124 +154410,124 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \oe
     connect \B \oe_ok
-    connect \Y $424
+    connect \Y $348
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $426
+  wire width 1 $350
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $427
+  cell $or $351
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $424
+    connect \A $348
     connect \B \xer_in
-    connect \Y $426
+    connect \Y $350
   end
   process $group_173
     assign \rdflag_XER_xer_so 1'0
-    assign \rdflag_XER_xer_so $426
+    assign \rdflag_XER_xer_so $350
     sync init
   end
   process $group_174
     assign \xer_src1__ren 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_XER_xer_so_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
         assign \xer_src1__ren 3'001
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $428
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $429
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $352
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $353
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel [2]
+    connect \A \cu_rd__rel_o [2]
     connect \B \fu_enable [0]
-    connect \Y $428
+    connect \Y $352
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $430
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $431
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $354
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $355
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $428
+    connect \A $352
     connect \B \rdflag_XER_xer_so
-    connect \Y $430
+    connect \Y $354
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $432
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $433
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $356
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $357
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$79 [3]
+    connect \A \cu_rd__rel_o$29 [3]
     connect \B \fu_enable [5]
-    connect \Y $432
+    connect \Y $356
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $434
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $435
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $358
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $359
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $432
+    connect \A $356
     connect \B \rdflag_XER_xer_so
-    connect \Y $434
+    connect \Y $358
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $436
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $437
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $360
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $361
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$82 [2]
+    connect \A \cu_rd__rel_o$32 [2]
     connect \B \fu_enable [6]
-    connect \Y $436
+    connect \Y $360
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $438
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $439
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $362
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $436
+    connect \A $360
     connect \B \rdflag_XER_xer_so
-    connect \Y $438
+    connect \Y $362
   end
   process $group_175
     assign \rdpick_XER_xer_so_i 3'000
-    assign \rdpick_XER_xer_so_i [0] $430
-    assign \rdpick_XER_xer_so_i [1] $434
-    assign \rdpick_XER_xer_so_i [2] $438
+    assign \rdpick_XER_xer_so_i [0] $354
+    assign \rdpick_XER_xer_so_i [1] $358
+    assign \rdpick_XER_xer_so_i [2] $362
     sync init
   end
   process $group_176
-    assign \fus_src3_i$194 1'0
-    assign \fus_src3_i$194 \xer_src1__data_o [0]
+    assign \fus_src3_i$118 1'0
+    assign \fus_src3_i$118 \xer_src1__data_o [0]
     sync init
   end
   process $group_177
@@ -154274,16 +154536,16 @@ module \core
     sync init
   end
   process $group_178
-    assign \fus_src3_i$195 1'0
-    assign \fus_src3_i$195 \xer_src1__data_o [0]
+    assign \fus_src3_i$119 1'0
+    assign \fus_src3_i$119 \xer_src1__data_o [0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_XER_xer_ca
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $440
+  wire width 1 $364
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $441
+  cell $eq $365
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -154291,124 +154553,124 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \input_carry
     connect \B 2'10
-    connect \Y $440
+    connect \Y $364
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $442
+  wire width 1 $366
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $443
+  cell $or $367
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $440
+    connect \A $364
     connect \B \xer_in
-    connect \Y $442
+    connect \Y $366
   end
   process $group_179
     assign \rdflag_XER_xer_ca 1'0
-    assign \rdflag_XER_xer_ca $442
+    assign \rdflag_XER_xer_ca $366
     sync init
   end
   process $group_180
     assign \xer_src2__ren 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_XER_xer_ca_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
         assign \xer_src2__ren 3'010
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $444
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $445
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $368
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel [3]
+    connect \A \cu_rd__rel_o [3]
     connect \B \fu_enable [0]
-    connect \Y $444
+    connect \Y $368
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $446
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $447
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $370
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $371
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $444
+    connect \A $368
     connect \B \rdflag_XER_xer_ca
-    connect \Y $446
+    connect \Y $370
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $448
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $449
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $372
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $373
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$79 [5]
+    connect \A \cu_rd__rel_o$29 [5]
     connect \B \fu_enable [5]
-    connect \Y $448
+    connect \Y $372
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $450
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $451
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $374
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $375
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $448
+    connect \A $372
     connect \B \rdflag_XER_xer_ca
-    connect \Y $450
+    connect \Y $374
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $452
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $453
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $376
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $377
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$85 [3]
+    connect \A \cu_rd__rel_o$35 [3]
     connect \B \fu_enable [7]
-    connect \Y $452
+    connect \Y $376
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $454
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $455
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $378
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $379
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $452
+    connect \A $376
     connect \B \rdflag_XER_xer_ca
-    connect \Y $454
+    connect \Y $378
   end
   process $group_181
     assign \rdpick_XER_xer_ca_i 3'000
-    assign \rdpick_XER_xer_ca_i [0] $446
-    assign \rdpick_XER_xer_ca_i [1] $450
-    assign \rdpick_XER_xer_ca_i [2] $454
+    assign \rdpick_XER_xer_ca_i [0] $370
+    assign \rdpick_XER_xer_ca_i [1] $374
+    assign \rdpick_XER_xer_ca_i [2] $378
     sync init
   end
   process $group_182
-    assign \fus_src4_i$196 2'00
-    assign \fus_src4_i$196 \xer_src2__data_o
+    assign \fus_src4_i$120 2'00
+    assign \fus_src4_i$120 \xer_src2__data_o
     sync init
   end
   process $group_183
@@ -154417,16 +154679,16 @@ module \core
     sync init
   end
   process $group_184
-    assign \fus_src4_i$197 2'00
-    assign \fus_src4_i$197 \xer_src2__data_o
+    assign \fus_src4_i$121 2'00
+    assign \fus_src4_i$121 \xer_src2__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_XER_xer_ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $456
+  wire width 1 $380
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $and $457
+  cell $and $381
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -154434,65 +154696,65 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \oe
     connect \B \oe_ok
-    connect \Y $456
+    connect \Y $380
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $458
+  wire width 1 $382
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $or $459
+  cell $or $383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $456
+    connect \A $380
     connect \B \xer_in
-    connect \Y $458
+    connect \Y $382
   end
   process $group_185
     assign \rdflag_XER_xer_ov 1'0
-    assign \rdflag_XER_xer_ov $458
+    assign \rdflag_XER_xer_ov $382
     sync init
   end
   process $group_186
     assign \xer_src3__ren 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_XER_xer_ov_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
         assign \xer_src3__ren 3'100
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $460
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $461
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $384
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $385
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$79 [4]
+    connect \A \cu_rd__rel_o$29 [4]
     connect \B \fu_enable [5]
-    connect \Y $460
+    connect \Y $384
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $462
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $463
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $386
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $387
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $460
+    connect \A $384
     connect \B \rdflag_XER_xer_ov
-    connect \Y $462
+    connect \Y $386
   end
   process $group_187
     assign \rdpick_XER_xer_ov_i 1'0
-    assign \rdpick_XER_xer_ov_i $462
+    assign \rdpick_XER_xer_ov_i $386
     sync init
   end
   process $group_188
@@ -154500,7 +154762,7 @@ module \core
     assign \fus_src5_i \xer_src3__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_CR_full_cr
   process $group_189
     assign \rdflag_CR_full_cr 1'0
@@ -154509,51 +154771,51 @@ module \core
   end
   process $group_190
     assign \cr_full_rd__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_CR_full_cr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
         assign \cr_full_rd__ren 8'11111111
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $464
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $465
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $388
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $389
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$70 [2]
+    connect \A \cu_rd__rel_o$20 [2]
     connect \B \fu_enable [1]
-    connect \Y $464
+    connect \Y $388
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $466
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $467
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $390
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $391
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $464
+    connect \A $388
     connect \B \rdflag_CR_full_cr
-    connect \Y $466
+    connect \Y $390
   end
   process $group_191
     assign \rdpick_CR_full_cr_i 1'0
-    assign \rdpick_CR_full_cr_i $466
+    assign \rdpick_CR_full_cr_i $390
     sync init
   end
   process $group_192
-    assign \fus_src3_i$198 32'00000000000000000000000000000000
-    assign \fus_src3_i$198 \cr_full_rd__data_o
+    assign \fus_src3_i$122 32'00000000000000000000000000000000
+    assign \fus_src3_i$122 \cr_full_rd__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_CR_cr_a
   process $group_193
     assign \rdflag_CR_cr_a 1'0
@@ -154561,11 +154823,11 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $468
+  wire width 16 $392
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 4 $469
+  wire width 4 $393
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sub $470
+  cell $sub $394
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -154573,108 +154835,108 @@ module \core
     parameter \Y_WIDTH 4
     connect \A 3'111
     connect \B \cr_in1
-    connect \Y $469
+    connect \Y $393
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $471
+  wire width 16 $395
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sshl $472
+  cell $sshl $396
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $469
-    connect \Y $471
+    connect \B $393
+    connect \Y $395
   end
-  connect $468 $471
+  connect $392 $395
   process $group_194
     assign \cr_src1__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_CR_cr_a_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \cr_src1__ren $468 [7:0]
+        assign \cr_src1__ren $392 [7:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $473
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $474
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $397
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $398
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$70 [3]
+    connect \A \cu_rd__rel_o$20 [3]
     connect \B \fu_enable [1]
-    connect \Y $473
+    connect \Y $397
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $475
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $476
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $399
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $400
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $473
+    connect \A $397
     connect \B \rdflag_CR_cr_a
-    connect \Y $475
+    connect \Y $399
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $477
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $478
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $401
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $402
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$97 [2]
+    connect \A \cu_rd__rel_o$47 [2]
     connect \B \fu_enable [2]
-    connect \Y $477
+    connect \Y $401
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $479
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $480
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $403
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $404
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $477
+    connect \A $401
     connect \B \rdflag_CR_cr_a
-    connect \Y $479
+    connect \Y $403
   end
   process $group_195
     assign \rdpick_CR_cr_a_i 2'00
-    assign \rdpick_CR_cr_a_i [0] $475
-    assign \rdpick_CR_cr_a_i [1] $479
+    assign \rdpick_CR_cr_a_i [0] $399
+    assign \rdpick_CR_cr_a_i [1] $403
     sync init
   end
   process $group_196
-    assign \fus_src4_i$199 4'0000
-    assign \fus_src4_i$199 \cr_src1__data_o
+    assign \fus_src4_i$123 4'0000
+    assign \fus_src4_i$123 \cr_src1__data_o
     sync init
   end
   process $group_197
-    assign \rd__go$98 3'000
-    assign \rd__go$98 [2] \rdpick_CR_cr_a_o [1]
-    assign \rd__go$98 [0] \rdpick_FAST_fast1_o [0]
-    assign \rd__go$98 [1] \rdpick_FAST_fast2_o [0]
+    assign \cu_rd__go_i$48 3'000
+    assign \cu_rd__go_i$48 [2] \rdpick_CR_cr_a_o [1]
+    assign \cu_rd__go_i$48 [0] \rdpick_FAST_fast1_o [0]
+    assign \cu_rd__go_i$48 [1] \rdpick_FAST_fast2_o [0]
     sync init
   end
   process $group_198
-    assign \fus_src3_i$200 4'0000
-    assign \fus_src3_i$200 \cr_src1__data_o
+    assign \fus_src3_i$124 4'0000
+    assign \fus_src3_i$124 \cr_src1__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_CR_cr_b
   process $group_199
     assign \rdflag_CR_cr_b 1'0
@@ -154682,11 +154944,11 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $481
+  wire width 16 $405
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 4 $482
+  wire width 4 $406
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sub $483
+  cell $sub $407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -154694,151 +154956,151 @@ module \core
     parameter \Y_WIDTH 4
     connect \A 3'111
     connect \B \cr_in2
-    connect \Y $482
+    connect \Y $406
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $484
+  wire width 16 $408
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sshl $485
+  cell $sshl $409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $482
-    connect \Y $484
+    connect \B $406
+    connect \Y $408
   end
-  connect $481 $484
+  connect $405 $408
   process $group_200
     assign \cr_src2__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_CR_cr_b_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \cr_src2__ren $481 [7:0]
+        assign \cr_src2__ren $405 [7:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $486
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $487
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $410
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$70 [4]
+    connect \A \cu_rd__rel_o$20 [4]
     connect \B \fu_enable [1]
-    connect \Y $486
+    connect \Y $410
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $488
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $489
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $412
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $486
+    connect \A $410
     connect \B \rdflag_CR_cr_b
-    connect \Y $488
+    connect \Y $412
   end
   process $group_201
     assign \rdpick_CR_cr_b_i 1'0
-    assign \rdpick_CR_cr_b_i $488
+    assign \rdpick_CR_cr_b_i $412
     sync init
   end
   process $group_202
-    assign \fus_src5_i$201 4'0000
-    assign \fus_src5_i$201 \cr_src2__data_o
+    assign \fus_src5_i$125 4'0000
+    assign \fus_src5_i$125 \cr_src2__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_CR_cr_c
   process $group_203
     assign \rdflag_CR_cr_c 1'0
-    assign \rdflag_CR_cr_c \cr_in2_ok$7
+    assign \rdflag_CR_cr_c \cr_in2_ok$3
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $490
+  wire width 16 $414
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 4 $491
+  wire width 4 $415
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sub $492
+  cell $sub $416
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A 3'111
-    connect \B \cr_in2$99
-    connect \Y $491
+    connect \B \cr_in2$49
+    connect \Y $415
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $493
+  wire width 16 $417
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sshl $494
+  cell $sshl $418
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $491
-    connect \Y $493
+    connect \B $415
+    connect \Y $417
   end
-  connect $490 $493
+  connect $414 $417
   process $group_204
     assign \cr_src3__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_CR_cr_c_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \cr_src3__ren $490 [7:0]
+        assign \cr_src3__ren $414 [7:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $495
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $496
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $419
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $420
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$70 [5]
+    connect \A \cu_rd__rel_o$20 [5]
     connect \B \fu_enable [1]
-    connect \Y $495
+    connect \Y $419
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $497
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $498
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $421
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $422
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $495
+    connect \A $419
     connect \B \rdflag_CR_cr_c
-    connect \Y $497
+    connect \Y $421
   end
   process $group_205
     assign \rdpick_CR_cr_c_i 1'0
-    assign \rdpick_CR_cr_c_i $497
+    assign \rdpick_CR_cr_c_i $421
     sync init
   end
   process $group_206
-    assign \fus_src6_i$202 4'0000
-    assign \fus_src6_i$202 \cr_src3__data_o
+    assign \fus_src6_i$126 4'0000
+    assign \fus_src6_i$126 \cr_src3__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_FAST_fast1
   process $group_207
     assign \rdflag_FAST_fast1 1'0
@@ -154846,9 +155108,9 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  wire width 8 $499
+  wire width 8 $423
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  cell $sshl $500
+  cell $sshl $424
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -154856,119 +155118,119 @@ module \core
     parameter \Y_WIDTH 8
     connect \A 1'1
     connect \B \fast1
-    connect \Y $499
+    connect \Y $423
   end
   process $group_208
     assign \fast_src1__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_FAST_fast1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \fast_src1__ren $499
+        assign \fast_src1__ren $423
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $501
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $502
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $425
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $426
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$97 [0]
+    connect \A \cu_rd__rel_o$47 [0]
     connect \B \fu_enable [2]
-    connect \Y $501
+    connect \Y $425
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $503
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $504
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $427
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $428
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $501
+    connect \A $425
     connect \B \rdflag_FAST_fast1
-    connect \Y $503
+    connect \Y $427
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $505
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $506
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $429
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $430
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$73 [2]
+    connect \A \cu_rd__rel_o$23 [2]
     connect \B \fu_enable [3]
-    connect \Y $505
+    connect \Y $429
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $507
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $508
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $431
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $432
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $505
+    connect \A $429
     connect \B \rdflag_FAST_fast1
-    connect \Y $507
+    connect \Y $431
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $509
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $510
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $433
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $434
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$79 [2]
+    connect \A \cu_rd__rel_o$29 [2]
     connect \B \fu_enable [5]
-    connect \Y $509
+    connect \Y $433
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $511
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $512
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $435
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $436
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $509
+    connect \A $433
     connect \B \rdflag_FAST_fast1
-    connect \Y $511
+    connect \Y $435
   end
   process $group_209
     assign \rdpick_FAST_fast1_i 3'000
-    assign \rdpick_FAST_fast1_i [0] $503
-    assign \rdpick_FAST_fast1_i [1] $507
-    assign \rdpick_FAST_fast1_i [2] $511
+    assign \rdpick_FAST_fast1_i [0] $427
+    assign \rdpick_FAST_fast1_i [1] $431
+    assign \rdpick_FAST_fast1_i [2] $435
     sync init
   end
   process $group_210
-    assign \src1_i$100 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$100 \fast_src1__data_o
+    assign \src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_i$50 \fast_src1__data_o
     sync init
   end
   process $group_211
-    assign \fus_src3_i$203 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$203 \fast_src1__data_o
+    assign \fus_src3_i$127 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$127 \fast_src1__data_o
     sync init
   end
   process $group_212
-    assign \fus_src3_i$204 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$204 \fast_src1__data_o
+    assign \fus_src3_i$128 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$128 \fast_src1__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_FAST_fast2
   process $group_213
     assign \rdflag_FAST_fast2 1'0
@@ -154976,9 +155238,9 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  wire width 8 $513
+  wire width 8 $437
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  cell $sshl $514
+  cell $sshl $438
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -154986,87 +155248,87 @@ module \core
     parameter \Y_WIDTH 8
     connect \A 1'1
     connect \B \fast2
-    connect \Y $513
+    connect \Y $437
   end
   process $group_214
     assign \fast_src2__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_FAST_fast2_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \fast_src2__ren $513
+        assign \fast_src2__ren $437
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $515
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $516
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $439
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $440
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$97 [1]
+    connect \A \cu_rd__rel_o$47 [1]
     connect \B \fu_enable [2]
-    connect \Y $515
+    connect \Y $439
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $517
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $518
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $441
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $442
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $515
+    connect \A $439
     connect \B \rdflag_FAST_fast2
-    connect \Y $517
+    connect \Y $441
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $519
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $520
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $443
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $444
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$73 [3]
+    connect \A \cu_rd__rel_o$23 [3]
     connect \B \fu_enable [3]
-    connect \Y $519
+    connect \Y $443
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $521
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $522
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $445
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $446
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $519
+    connect \A $443
     connect \B \rdflag_FAST_fast2
-    connect \Y $521
+    connect \Y $445
   end
   process $group_215
     assign \rdpick_FAST_fast2_i 2'00
-    assign \rdpick_FAST_fast2_i [0] $517
-    assign \rdpick_FAST_fast2_i [1] $521
+    assign \rdpick_FAST_fast2_i [0] $441
+    assign \rdpick_FAST_fast2_i [1] $445
     sync init
   end
   process $group_216
-    assign \src2_i$101 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$101 \fast_src2__data_o
+    assign \src2_i$51 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$51 \fast_src2__data_o
     sync init
   end
   process $group_217
-    assign \fus_src4_i$205 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src4_i$205 \fast_src2__data_o
+    assign \fus_src4_i$129 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src4_i$129 \fast_src2__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_SPR_spr1
   process $group_218
     assign \rdflag_SPR_spr1 1'0
@@ -155075,54 +155337,54 @@ module \core
   end
   process $group_219
     assign \spr_src__ren 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_SPR_spr1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
         assign \spr_src__ren \spr1 [0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $523
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $524
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $447
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $448
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \rd__rel$79 [1]
+    connect \A \cu_rd__rel_o$29 [1]
     connect \B \fu_enable [5]
-    connect \Y $523
+    connect \Y $447
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  wire width 1 $525
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
-  cell $and $526
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  wire width 1 $449
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
+  cell $and $450
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $523
+    connect \A $447
     connect \B \rdflag_SPR_spr1
-    connect \Y $525
+    connect \Y $449
   end
   process $group_220
     assign \rdpick_SPR_spr1_i 1'0
-    assign \rdpick_SPR_spr1_i $525
+    assign \rdpick_SPR_spr1_i $449
     sync init
   end
   process $group_221
-    assign \src2_i$102 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$102 \spr_src__data_o
+    assign \src2_i$52 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_i$52 \spr_src__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  wire width 32 $527
+  wire width 32 $451
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  cell $sshl $528
+  cell $sshl $452
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155130,161 +155392,161 @@ module \core
     parameter \Y_WIDTH 32
     connect \A 1'1
     connect \B \rego
-    connect \Y $527
+    connect \Y $451
   end
   process $group_222
     assign \int_wen 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_INT_o_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \int_wen $527
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \int_wen $451
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \int_wen 32'00000000000000000000000000000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $529
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $530
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $453
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $454
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_o_ok
-    connect \B \busy_o
-    connect \Y $529
+    connect \B \cu_busy_o
+    connect \Y $453
   end
   process $group_223
     assign \wrflag_alu0_o_0 1'0
-    assign \wrflag_alu0_o_0 $529
+    assign \wrflag_alu0_o_0 $453
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $531
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $532
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $455
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $456
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel [0]
+    connect \A \cu_wr__rel_o [0]
     connect \B \fu_enable [0]
-    connect \Y $531
+    connect \Y $455
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $533
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $534
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $457
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $458
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$103 [0]
+    connect \A \cu_wr__rel_o$53 [0]
     connect \B \fu_enable [1]
-    connect \Y $533
+    connect \Y $457
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $535
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $536
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $459
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $460
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$105 [0]
+    connect \A \cu_wr__rel_o$55 [0]
     connect \B \fu_enable [3]
-    connect \Y $535
+    connect \Y $459
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $537
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $538
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $461
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $462
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$107 [0]
+    connect \A \cu_wr__rel_o$57 [0]
     connect \B \fu_enable [4]
-    connect \Y $537
+    connect \Y $461
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $539
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $540
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $463
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $464
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$109 [0]
+    connect \A \cu_wr__rel_o$59 [0]
     connect \B \fu_enable [5]
-    connect \Y $539
+    connect \Y $463
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $541
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $542
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $465
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $466
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$111 [0]
+    connect \A \cu_wr__rel_o$61 [0]
     connect \B \fu_enable [6]
-    connect \Y $541
+    connect \Y $465
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $543
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $544
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $467
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $468
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$113 [0]
+    connect \A \cu_wr__rel_o$63 [0]
     connect \B \fu_enable [7]
-    connect \Y $543
+    connect \Y $467
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $545
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $546
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $469
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $470
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$115 [0]
+    connect \A \cu_wr__rel_o$65 [0]
     connect \B \fu_enable [8]
-    connect \Y $545
+    connect \Y $469
   end
   process $group_224
     assign \wrpick_INT_o_i 8'00000000
-    assign \wrpick_INT_o_i [0] $531
-    assign \wrpick_INT_o_i [1] $533
-    assign \wrpick_INT_o_i [2] $535
-    assign \wrpick_INT_o_i [3] $537
-    assign \wrpick_INT_o_i [4] $539
-    assign \wrpick_INT_o_i [5] $541
-    assign \wrpick_INT_o_i [6] $543
-    assign \wrpick_INT_o_i [7] $545
+    assign \wrpick_INT_o_i [0] $455
+    assign \wrpick_INT_o_i [1] $457
+    assign \wrpick_INT_o_i [2] $459
+    assign \wrpick_INT_o_i [3] $461
+    assign \wrpick_INT_o_i [4] $463
+    assign \wrpick_INT_o_i [5] $465
+    assign \wrpick_INT_o_i [6] $467
+    assign \wrpick_INT_o_i [7] $469
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $547
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $548
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $471
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $472
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155292,12 +155554,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [0]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $547
+    connect \Y $471
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $549
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $550
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $473
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $474
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155305,12 +155567,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [0]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $549
+    connect \Y $473
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $551
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $552
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $475
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $476
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155318,12 +155580,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [0]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $551
+    connect \Y $475
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $553
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $554
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $477
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $478
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155331,12 +155593,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ov_o [0]
     connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $553
+    connect \Y $477
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $555
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $556
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $479
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $480
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155344,41 +155606,41 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_so_o [0]
     connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $555
+    connect \Y $479
   end
   process $group_225
-    assign \wr__go 5'00000
-    assign \wr__go [0] $547
-    assign \wr__go [1] $549
-    assign \wr__go [2] $551
-    assign \wr__go [3] $553
-    assign \wr__go [4] $555
+    assign \cu_wr__go_i 5'00000
+    assign \cu_wr__go_i [0] $471
+    assign \cu_wr__go_i [1] $473
+    assign \cu_wr__go_i [2] $475
+    assign \cu_wr__go_i [3] $477
+    assign \cu_wr__go_i [4] $479
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_cr0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $557
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $558
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $481
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $482
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$206
-    connect \B \busy_o$6
-    connect \Y $557
+    connect \A \fus_o_ok$130
+    connect \B \cu_busy_o$2
+    connect \Y $481
   end
   process $group_226
     assign \wrflag_cr0_o_0 1'0
-    assign \wrflag_cr0_o_0 $557
+    assign \wrflag_cr0_o_0 $481
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $559
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $560
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $483
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $484
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155386,12 +155648,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [1]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $559
+    connect \Y $483
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $561
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $562
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $485
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $486
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155399,12 +155661,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_full_cr_o
     connect \B \wrpick_CR_full_cr_en_o
-    connect \Y $561
+    connect \Y $485
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $563
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $564
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $487
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $488
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155412,39 +155674,39 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [1]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $563
+    connect \Y $487
   end
   process $group_227
-    assign \wr__go$104 3'000
-    assign \wr__go$104 [0] $559
-    assign \wr__go$104 [1] $561
-    assign \wr__go$104 [2] $563
+    assign \cu_wr__go_i$54 3'000
+    assign \cu_wr__go_i$54 [0] $483
+    assign \cu_wr__go_i$54 [1] $485
+    assign \cu_wr__go_i$54 [2] $487
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $565
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $566
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $489
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $490
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$207
-    connect \B \busy_o$22
-    connect \Y $565
+    connect \A \fus_o_ok$131
+    connect \B \cu_busy_o$9
+    connect \Y $489
   end
   process $group_228
     assign \wrflag_trap0_o_0 1'0
-    assign \wrflag_trap0_o_0 $565
+    assign \wrflag_trap0_o_0 $489
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $567
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $568
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $491
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $492
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155452,12 +155714,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [2]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $567
+    connect \Y $491
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $569
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $570
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $493
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $494
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155465,12 +155727,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast1_o [1]
     connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $569
+    connect \Y $493
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $571
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $572
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $495
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $496
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155478,12 +155740,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast2_o [1]
     connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $571
+    connect \Y $495
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $573
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $574
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $497
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $498
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155491,12 +155753,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_nia_o [1]
     connect \B \wrpick_FAST_nia_en_o
-    connect \Y $573
+    connect \Y $497
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $575
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $576
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $499
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $500
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155504,41 +155766,41 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_msr_o
     connect \B \wrpick_FAST_msr_en_o
-    connect \Y $575
+    connect \Y $499
   end
   process $group_229
-    assign \wr__go$106 5'00000
-    assign \wr__go$106 [0] $567
-    assign \wr__go$106 [1] $569
-    assign \wr__go$106 [2] $571
-    assign \wr__go$106 [3] $573
-    assign \wr__go$106 [4] $575
+    assign \cu_wr__go_i$56 5'00000
+    assign \cu_wr__go_i$56 [0] $491
+    assign \cu_wr__go_i$56 [1] $493
+    assign \cu_wr__go_i$56 [2] $495
+    assign \cu_wr__go_i$56 [3] $497
+    assign \cu_wr__go_i$56 [4] $499
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_logical0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $577
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $578
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $501
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $502
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$208
-    connect \B \busy_o$36
-    connect \Y $577
+    connect \A \fus_o_ok$132
+    connect \B \cu_busy_o$11
+    connect \Y $501
   end
   process $group_230
     assign \wrflag_logical0_o_0 1'0
-    assign \wrflag_logical0_o_0 $577
+    assign \wrflag_logical0_o_0 $501
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $579
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $580
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $503
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $504
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155546,12 +155808,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [3]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $579
+    connect \Y $503
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $581
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $582
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $505
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $506
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155559,12 +155821,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [2]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $581
+    connect \Y $505
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $583
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $584
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $507
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $508
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155572,39 +155834,39 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [1]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $583
+    connect \Y $507
   end
   process $group_231
-    assign \wr__go$108 3'000
-    assign \wr__go$108 [0] $579
-    assign \wr__go$108 [1] $581
-    assign \wr__go$108 [2] $583
+    assign \cu_wr__go_i$58 3'000
+    assign \cu_wr__go_i$58 [0] $503
+    assign \cu_wr__go_i$58 [1] $505
+    assign \cu_wr__go_i$58 [2] $507
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $585
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $586
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $509
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $510
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$209
-    connect \B \busy_o$42
-    connect \Y $585
+    connect \A \fus_o_ok$133
+    connect \B \cu_busy_o$13
+    connect \Y $509
   end
   process $group_232
     assign \wrflag_spr0_o_0 1'0
-    assign \wrflag_spr0_o_0 $585
+    assign \wrflag_spr0_o_0 $509
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $587
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $588
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $511
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $512
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155612,12 +155874,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [4]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $587
+    connect \Y $511
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $589
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $590
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $513
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $514
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155625,12 +155887,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [2]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $589
+    connect \Y $513
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $591
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $592
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $515
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $516
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155638,12 +155900,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ov_o [1]
     connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $591
+    connect \Y $515
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $593
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $594
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $517
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $518
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155651,12 +155913,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_so_o [1]
     connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $593
+    connect \Y $517
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $595
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $596
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $519
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $520
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155664,12 +155926,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast1_o [2]
     connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $595
+    connect \Y $519
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $597
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $598
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $521
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $522
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155677,42 +155939,42 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_SPR_spr1_o
     connect \B \wrpick_SPR_spr1_en_o
-    connect \Y $597
+    connect \Y $521
   end
   process $group_233
-    assign \wr__go$110 6'000000
-    assign \wr__go$110 [0] $587
-    assign \wr__go$110 [5] $589
-    assign \wr__go$110 [4] $591
-    assign \wr__go$110 [3] $593
-    assign \wr__go$110 [2] $595
-    assign \wr__go$110 [1] $597
+    assign \cu_wr__go_i$60 6'000000
+    assign \cu_wr__go_i$60 [0] $511
+    assign \cu_wr__go_i$60 [5] $513
+    assign \cu_wr__go_i$60 [4] $515
+    assign \cu_wr__go_i$60 [3] $517
+    assign \cu_wr__go_i$60 [2] $519
+    assign \cu_wr__go_i$60 [1] $521
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $599
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $600
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $523
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $524
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$210
-    connect \B \busy_o$53
-    connect \Y $599
+    connect \A \fus_o_ok$134
+    connect \B \cu_busy_o$15
+    connect \Y $523
   end
   process $group_234
     assign \wrflag_mul0_o_0 1'0
-    assign \wrflag_mul0_o_0 $599
+    assign \wrflag_mul0_o_0 $523
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $601
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $602
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $525
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $526
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155720,12 +155982,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [5]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $601
+    connect \Y $525
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $603
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $604
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $527
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $528
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155733,12 +155995,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [3]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $603
+    connect \Y $527
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $605
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $606
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $529
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $530
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155746,12 +156008,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ov_o [2]
     connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $605
+    connect \Y $529
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $607
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $608
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $531
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $532
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155759,40 +156021,40 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_so_o [2]
     connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $607
+    connect \Y $531
   end
   process $group_235
-    assign \wr__go$112 4'0000
-    assign \wr__go$112 [0] $601
-    assign \wr__go$112 [1] $603
-    assign \wr__go$112 [2] $605
-    assign \wr__go$112 [3] $607
+    assign \cu_wr__go_i$62 4'0000
+    assign \cu_wr__go_i$62 [0] $525
+    assign \cu_wr__go_i$62 [1] $527
+    assign \cu_wr__go_i$62 [2] $529
+    assign \cu_wr__go_i$62 [3] $531
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_shiftrot0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $609
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $610
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $533
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $534
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$211
-    connect \B \busy_o$62
-    connect \Y $609
+    connect \A \fus_o_ok$135
+    connect \B \cu_busy_o$17
+    connect \Y $533
   end
   process $group_236
     assign \wrflag_shiftrot0_o_0 1'0
-    assign \wrflag_shiftrot0_o_0 $609
+    assign \wrflag_shiftrot0_o_0 $533
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $611
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $612
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $535
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $536
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155800,12 +156062,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [6]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $611
+    connect \Y $535
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $613
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $614
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $537
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $538
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155813,12 +156075,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [4]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $613
+    connect \Y $537
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $615
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $616
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $539
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $540
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155826,39 +156088,39 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [3]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $615
+    connect \Y $539
   end
   process $group_237
-    assign \wr__go$114 3'000
-    assign \wr__go$114 [0] $611
-    assign \wr__go$114 [1] $613
-    assign \wr__go$114 [2] $615
+    assign \cu_wr__go_i$64 3'000
+    assign \cu_wr__go_i$64 [0] $535
+    assign \cu_wr__go_i$64 [1] $537
+    assign \cu_wr__go_i$64 [2] $539
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_ldst0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $617
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $618
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $541
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $542
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \o_ok
-    connect \B \busy_o$69
-    connect \Y $617
+    connect \B \cu_busy_o$19
+    connect \Y $541
   end
   process $group_238
     assign \wrflag_ldst0_o_0 1'0
-    assign \wrflag_ldst0_o_0 $617
+    assign \wrflag_ldst0_o_0 $541
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $619
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $620
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $543
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $544
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155866,12 +156128,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [7]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $619
+    connect \Y $543
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $621
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $622
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $545
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $546
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155879,117 +156141,117 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o1_o
     connect \B \wrpick_INT_o1_en_o
-    connect \Y $621
+    connect \Y $545
   end
   process $group_239
-    assign \wr__go$116 2'00
-    assign \wr__go$116 [0] $619
-    assign \wr__go$116 [1] $621
+    assign \cu_wr__go_i$66 2'00
+    assign \cu_wr__go_i$66 [0] $543
+    assign \cu_wr__go_i$66 [1] $545
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $623
+  wire width 65 $547
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $624
+  wire width 64 $548
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $625
+  cell $or $549
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
     connect \A \dest1_o
-    connect \B \dest1_o$117
-    connect \Y $624
+    connect \B \dest1_o$67
+    connect \Y $548
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $626
+  wire width 64 $550
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $627
+  cell $or $551
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \dest1_o$118
-    connect \B \dest1_o$119
-    connect \Y $626
+    connect \A \dest1_o$68
+    connect \B \dest1_o$69
+    connect \Y $550
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $628
+  wire width 64 $552
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $629
+  cell $or $553
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $624
-    connect \B $626
-    connect \Y $628
+    connect \A $548
+    connect \B $550
+    connect \Y $552
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $630
+  wire width 64 $554
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $631
+  cell $or $555
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \dest1_o$120
-    connect \B \dest1_o$121
-    connect \Y $630
+    connect \A \dest1_o$70
+    connect \B \dest1_o$71
+    connect \Y $554
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 65 $632
+  wire width 65 $556
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $633
+  cell $or $557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 65
     parameter \Y_WIDTH 65
-    connect \A \dest1_o$122
+    connect \A \dest1_o$72
     connect \B { \o_ok \o }
-    connect \Y $632
+    connect \Y $556
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $634
+  wire width 65 $558
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $635
+  cell $or $559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 65
     parameter \Y_WIDTH 65
-    connect \A $630
-    connect \B $632
-    connect \Y $634
+    connect \A $554
+    connect \B $556
+    connect \Y $558
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $636
+  wire width 65 $560
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $637
+  cell $or $561
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 65
     parameter \Y_WIDTH 65
-    connect \A $628
-    connect \B $634
-    connect \Y $636
+    connect \A $552
+    connect \B $558
+    connect \Y $560
   end
-  connect $623 $636
+  connect $547 $560
   process $group_240
     assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i $623 [63:0]
+    assign \int_data_i $547 [63:0]
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  wire width 32 $638
+  wire width 32 $562
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  cell $sshl $639
+  cell $sshl $563
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155997,113 +156259,113 @@ module \core
     parameter \Y_WIDTH 32
     connect \A 1'1
     connect \B \ea
-    connect \Y $638
+    connect \Y $562
   end
   process $group_241
-    assign \int_wen$246 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    assign \int_wen$170 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_INT_o1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \int_wen$246 $638
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \int_wen$170 $562
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \int_wen$246 32'00000000000000000000000000000000
+        assign \int_wen$170 32'00000000000000000000000000000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_ldst0_o1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $640
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $641
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $564
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $565
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \ea_ok
-    connect \B \busy_o$69
-    connect \Y $640
+    connect \B \cu_busy_o$19
+    connect \Y $564
   end
   process $group_242
     assign \wrflag_ldst0_o1_1 1'0
-    assign \wrflag_ldst0_o1_1 $640
+    assign \wrflag_ldst0_o1_1 $564
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $642
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $643
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $566
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $567
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$115 [1]
+    connect \A \cu_wr__rel_o$65 [1]
     connect \B \fu_enable [8]
-    connect \Y $642
+    connect \Y $566
   end
   process $group_243
     assign \wrpick_INT_o1_i 1'0
-    assign \wrpick_INT_o1_i $642
+    assign \wrpick_INT_o1_i $566
     sync init
   end
   process $group_244
-    assign \int_data_i$247 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i$247 { \ea_ok \ea$123 } [63:0]
+    assign \int_data_i$171 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \int_data_i$171 { \ea_ok \ea$73 } [63:0]
     sync init
   end
   process $group_245
     assign \cr_full_wr__wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_CR_full_cr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
         assign \cr_full_wr__wen 8'11111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \cr_full_wr__wen 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_cr0_full_cr_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $644
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $645
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $568
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $569
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_full_cr_ok
-    connect \B \busy_o$6
-    connect \Y $644
+    connect \B \cu_busy_o$2
+    connect \Y $568
   end
   process $group_246
     assign \wrflag_cr0_full_cr_1 1'0
-    assign \wrflag_cr0_full_cr_1 $644
+    assign \wrflag_cr0_full_cr_1 $568
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $646
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $647
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $570
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $571
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$103 [1]
+    connect \A \cu_wr__rel_o$53 [1]
     connect \B \fu_enable [1]
-    connect \Y $646
+    connect \Y $570
   end
   process $group_247
     assign \wrpick_CR_full_cr_i 1'0
-    assign \wrpick_CR_full_cr_i $646
+    assign \wrpick_CR_full_cr_i $570
     sync init
   end
   process $group_248
@@ -156112,11 +156374,11 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $648
+  wire width 16 $572
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 4 $649
+  wire width 4 $573
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sub $650
+  cell $sub $574
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -156124,777 +156386,777 @@ module \core
     parameter \Y_WIDTH 4
     connect \A 3'111
     connect \B \cr_out
-    connect \Y $649
+    connect \Y $573
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $651
+  wire width 16 $575
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sshl $652
+  cell $sshl $576
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $649
-    connect \Y $651
+    connect \B $573
+    connect \Y $575
   end
-  connect $648 $651
+  connect $572 $575
   process $group_249
     assign \cr_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_CR_cr_a_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \cr_wen $648 [7:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \cr_wen $572 [7:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \cr_wen 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $653
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $654
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $577
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_cr_a_ok
-    connect \B \busy_o
-    connect \Y $653
+    connect \B \cu_busy_o
+    connect \Y $577
   end
   process $group_250
     assign \wrflag_alu0_cr_a_1 1'0
-    assign \wrflag_alu0_cr_a_1 $653
+    assign \wrflag_alu0_cr_a_1 $577
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $655
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $656
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $579
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel [1]
+    connect \A \cu_wr__rel_o [1]
     connect \B \fu_enable [0]
-    connect \Y $655
+    connect \Y $579
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $657
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $658
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $581
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $582
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$103 [2]
+    connect \A \cu_wr__rel_o$53 [2]
     connect \B \fu_enable [1]
-    connect \Y $657
+    connect \Y $581
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $659
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $660
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $583
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$107 [1]
+    connect \A \cu_wr__rel_o$57 [1]
     connect \B \fu_enable [4]
-    connect \Y $659
+    connect \Y $583
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $661
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $662
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $585
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $586
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$111 [1]
+    connect \A \cu_wr__rel_o$61 [1]
     connect \B \fu_enable [6]
-    connect \Y $661
+    connect \Y $585
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $663
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $664
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $587
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $588
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$113 [1]
+    connect \A \cu_wr__rel_o$63 [1]
     connect \B \fu_enable [7]
-    connect \Y $663
+    connect \Y $587
   end
   process $group_251
     assign \wrpick_CR_cr_a_i 5'00000
-    assign \wrpick_CR_cr_a_i [0] $655
-    assign \wrpick_CR_cr_a_i [1] $657
-    assign \wrpick_CR_cr_a_i [2] $659
-    assign \wrpick_CR_cr_a_i [3] $661
-    assign \wrpick_CR_cr_a_i [4] $663
+    assign \wrpick_CR_cr_a_i [0] $579
+    assign \wrpick_CR_cr_a_i [1] $581
+    assign \wrpick_CR_cr_a_i [2] $583
+    assign \wrpick_CR_cr_a_i [3] $585
+    assign \wrpick_CR_cr_a_i [4] $587
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_cr0_cr_a_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $665
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $666
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $589
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $590
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$212
-    connect \B \busy_o$6
-    connect \Y $665
+    connect \A \fus_cr_a_ok$136
+    connect \B \cu_busy_o$2
+    connect \Y $589
   end
   process $group_252
     assign \wrflag_cr0_cr_a_2 1'0
-    assign \wrflag_cr0_cr_a_2 $665
+    assign \wrflag_cr0_cr_a_2 $589
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_logical0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $667
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $668
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $591
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $592
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$213
-    connect \B \busy_o$36
-    connect \Y $667
+    connect \A \fus_cr_a_ok$137
+    connect \B \cu_busy_o$11
+    connect \Y $591
   end
   process $group_253
     assign \wrflag_logical0_cr_a_1 1'0
-    assign \wrflag_logical0_cr_a_1 $667
+    assign \wrflag_logical0_cr_a_1 $591
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $669
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $670
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $593
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $594
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$214
-    connect \B \busy_o$53
-    connect \Y $669
+    connect \A \fus_cr_a_ok$138
+    connect \B \cu_busy_o$15
+    connect \Y $593
   end
   process $group_254
     assign \wrflag_mul0_cr_a_1 1'0
-    assign \wrflag_mul0_cr_a_1 $669
+    assign \wrflag_mul0_cr_a_1 $593
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_shiftrot0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $671
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $672
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $595
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $596
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$215
-    connect \B \busy_o$62
-    connect \Y $671
+    connect \A \fus_cr_a_ok$139
+    connect \B \cu_busy_o$17
+    connect \Y $595
   end
   process $group_255
     assign \wrflag_shiftrot0_cr_a_1 1'0
-    assign \wrflag_shiftrot0_cr_a_1 $671
+    assign \wrflag_shiftrot0_cr_a_1 $595
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $673
+  wire width 4 $597
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $674
+  cell $or $598
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$216
+    connect \A \fus_dest2_o$140
     connect \B \fus_dest3_o
-    connect \Y $673
+    connect \Y $597
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $675
+  wire width 4 $599
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $676
+  cell $or $600
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$218
-    connect \B \fus_dest2_o$219
-    connect \Y $675
+    connect \A \fus_dest2_o$142
+    connect \B \fus_dest2_o$143
+    connect \Y $599
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $677
+  wire width 4 $601
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $678
+  cell $or $602
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$217
-    connect \B $675
-    connect \Y $677
+    connect \A \fus_dest2_o$141
+    connect \B $599
+    connect \Y $601
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $679
+  wire width 4 $603
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $680
+  cell $or $604
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A $673
-    connect \B $677
-    connect \Y $679
+    connect \A $597
+    connect \B $601
+    connect \Y $603
   end
   process $group_256
     assign \cr_data_i 4'0000
-    assign \cr_data_i $679
+    assign \cr_data_i $603
     sync init
   end
   process $group_257
     assign \xer_wen 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_XER_xer_ca_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
         assign \xer_wen 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \xer_wen 3'000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $681
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $682
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $605
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $606
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_xer_ca_ok
-    connect \B \busy_o
-    connect \Y $681
+    connect \B \cu_busy_o
+    connect \Y $605
   end
   process $group_258
     assign \wrflag_alu0_xer_ca_2 1'0
-    assign \wrflag_alu0_xer_ca_2 $681
+    assign \wrflag_alu0_xer_ca_2 $605
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $683
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $684
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $607
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $608
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel [2]
+    connect \A \cu_wr__rel_o [2]
     connect \B \fu_enable [0]
-    connect \Y $683
+    connect \Y $607
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $685
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $686
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $609
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $610
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$107 [2]
+    connect \A \cu_wr__rel_o$57 [2]
     connect \B \fu_enable [4]
-    connect \Y $685
+    connect \Y $609
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $687
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $688
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $611
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $612
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$109 [5]
+    connect \A \cu_wr__rel_o$59 [5]
     connect \B \fu_enable [5]
-    connect \Y $687
+    connect \Y $611
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $689
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $690
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $613
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $614
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$113 [2]
+    connect \A \cu_wr__rel_o$63 [2]
     connect \B \fu_enable [7]
-    connect \Y $689
+    connect \Y $613
   end
   process $group_259
     assign \wrpick_XER_xer_ca_i 4'0000
-    assign \wrpick_XER_xer_ca_i [0] $683
-    assign \wrpick_XER_xer_ca_i [1] $685
-    assign \wrpick_XER_xer_ca_i [2] $687
-    assign \wrpick_XER_xer_ca_i [3] $689
+    assign \wrpick_XER_xer_ca_i [0] $607
+    assign \wrpick_XER_xer_ca_i [1] $609
+    assign \wrpick_XER_xer_ca_i [2] $611
+    assign \wrpick_XER_xer_ca_i [3] $613
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_logical0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $691
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $692
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $615
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $616
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$220
-    connect \B \busy_o$36
-    connect \Y $691
+    connect \A \fus_xer_ca_ok$144
+    connect \B \cu_busy_o$11
+    connect \Y $615
   end
   process $group_260
     assign \wrflag_logical0_xer_ca_2 1'0
-    assign \wrflag_logical0_xer_ca_2 $691
+    assign \wrflag_logical0_xer_ca_2 $615
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_xer_ca_5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $693
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $694
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $617
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $618
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$221
-    connect \B \busy_o$42
-    connect \Y $693
+    connect \A \fus_xer_ca_ok$145
+    connect \B \cu_busy_o$13
+    connect \Y $617
   end
   process $group_261
     assign \wrflag_spr0_xer_ca_5 1'0
-    assign \wrflag_spr0_xer_ca_5 $693
+    assign \wrflag_spr0_xer_ca_5 $617
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_shiftrot0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $695
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $696
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $619
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $620
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$222
-    connect \B \busy_o$62
-    connect \Y $695
+    connect \A \fus_xer_ca_ok$146
+    connect \B \cu_busy_o$17
+    connect \Y $619
   end
   process $group_262
     assign \wrflag_shiftrot0_xer_ca_2 1'0
-    assign \wrflag_shiftrot0_xer_ca_2 $695
+    assign \wrflag_shiftrot0_xer_ca_2 $619
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $697
+  wire width 2 $621
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $698
+  cell $or $622
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A \fus_dest3_o$223
-    connect \B \fus_dest3_o$224
-    connect \Y $697
+    connect \A \fus_dest3_o$147
+    connect \B \fus_dest3_o$148
+    connect \Y $621
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $699
+  wire width 2 $623
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $700
+  cell $or $624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \fus_dest6_o
-    connect \B \fus_dest3_o$225
-    connect \Y $699
+    connect \B \fus_dest3_o$149
+    connect \Y $623
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $701
+  wire width 2 $625
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $702
+  cell $or $626
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A $697
-    connect \B $699
-    connect \Y $701
+    connect \A $621
+    connect \B $623
+    connect \Y $625
   end
   process $group_263
     assign \xer_data_i 2'00
-    assign \xer_data_i $701
+    assign \xer_data_i $625
     sync init
   end
   process $group_264
-    assign \xer_wen$248 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    assign \xer_wen$172 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_XER_xer_ov_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \xer_wen$248 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \xer_wen$172 3'100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \xer_wen$248 3'000
+        assign \xer_wen$172 3'000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_xer_ov_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $703
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $704
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $627
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $628
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_xer_ov_ok
-    connect \B \busy_o
-    connect \Y $703
+    connect \B \cu_busy_o
+    connect \Y $627
   end
   process $group_265
     assign \wrflag_alu0_xer_ov_3 1'0
-    assign \wrflag_alu0_xer_ov_3 $703
+    assign \wrflag_alu0_xer_ov_3 $627
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $705
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $706
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $629
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $630
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel [3]
+    connect \A \cu_wr__rel_o [3]
     connect \B \fu_enable [0]
-    connect \Y $705
+    connect \Y $629
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $707
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $708
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $631
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $632
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$109 [4]
+    connect \A \cu_wr__rel_o$59 [4]
     connect \B \fu_enable [5]
-    connect \Y $707
+    connect \Y $631
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $709
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $710
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $633
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $634
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$111 [2]
+    connect \A \cu_wr__rel_o$61 [2]
     connect \B \fu_enable [6]
-    connect \Y $709
+    connect \Y $633
   end
   process $group_266
     assign \wrpick_XER_xer_ov_i 3'000
-    assign \wrpick_XER_xer_ov_i [0] $705
-    assign \wrpick_XER_xer_ov_i [1] $707
-    assign \wrpick_XER_xer_ov_i [2] $709
+    assign \wrpick_XER_xer_ov_i [0] $629
+    assign \wrpick_XER_xer_ov_i [1] $631
+    assign \wrpick_XER_xer_ov_i [2] $633
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_xer_ov_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $711
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $712
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $635
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $636
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$226
-    connect \B \busy_o$42
-    connect \Y $711
+    connect \A \fus_xer_ov_ok$150
+    connect \B \cu_busy_o$13
+    connect \Y $635
   end
   process $group_267
     assign \wrflag_spr0_xer_ov_4 1'0
-    assign \wrflag_spr0_xer_ov_4 $711
+    assign \wrflag_spr0_xer_ov_4 $635
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_xer_ov_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $713
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $714
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $637
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $638
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$227
-    connect \B \busy_o$53
-    connect \Y $713
+    connect \A \fus_xer_ov_ok$151
+    connect \B \cu_busy_o$15
+    connect \Y $637
   end
   process $group_268
     assign \wrflag_mul0_xer_ov_2 1'0
-    assign \wrflag_mul0_xer_ov_2 $713
+    assign \wrflag_mul0_xer_ov_2 $637
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $715
+  wire width 2 $639
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $716
+  cell $or $640
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \fus_dest5_o
-    connect \B \fus_dest3_o$228
-    connect \Y $715
+    connect \B \fus_dest3_o$152
+    connect \Y $639
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $717
+  wire width 2 $641
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $718
+  cell $or $642
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \fus_dest4_o
-    connect \B $715
-    connect \Y $717
+    connect \B $639
+    connect \Y $641
   end
   process $group_269
-    assign \xer_data_i$249 2'00
-    assign \xer_data_i$249 $717
+    assign \xer_data_i$173 2'00
+    assign \xer_data_i$173 $641
     sync init
   end
   process $group_270
-    assign \xer_wen$250 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    assign \xer_wen$174 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_XER_xer_so_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \xer_wen$250 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \xer_wen$174 3'001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \xer_wen$250 3'000
+        assign \xer_wen$174 3'000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_xer_so_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $719
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $720
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $643
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $644
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_xer_so_ok
-    connect \B \busy_o
-    connect \Y $719
+    connect \B \cu_busy_o
+    connect \Y $643
   end
   process $group_271
     assign \wrflag_alu0_xer_so_4 1'0
-    assign \wrflag_alu0_xer_so_4 $719
+    assign \wrflag_alu0_xer_so_4 $643
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $721
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $722
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $645
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $646
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel [4]
+    connect \A \cu_wr__rel_o [4]
     connect \B \fu_enable [0]
-    connect \Y $721
+    connect \Y $645
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $723
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $724
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $647
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $648
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$109 [3]
+    connect \A \cu_wr__rel_o$59 [3]
     connect \B \fu_enable [5]
-    connect \Y $723
+    connect \Y $647
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $725
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $726
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $649
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $650
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$111 [3]
+    connect \A \cu_wr__rel_o$61 [3]
     connect \B \fu_enable [6]
-    connect \Y $725
+    connect \Y $649
   end
   process $group_272
     assign \wrpick_XER_xer_so_i 3'000
-    assign \wrpick_XER_xer_so_i [0] $721
-    assign \wrpick_XER_xer_so_i [1] $723
-    assign \wrpick_XER_xer_so_i [2] $725
+    assign \wrpick_XER_xer_so_i [0] $645
+    assign \wrpick_XER_xer_so_i [1] $647
+    assign \wrpick_XER_xer_so_i [2] $649
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_xer_so_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $727
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $728
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $651
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $652
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$229
-    connect \B \busy_o$42
-    connect \Y $727
+    connect \A \fus_xer_so_ok$153
+    connect \B \cu_busy_o$13
+    connect \Y $651
   end
   process $group_273
     assign \wrflag_spr0_xer_so_3 1'0
-    assign \wrflag_spr0_xer_so_3 $727
+    assign \wrflag_spr0_xer_so_3 $651
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_xer_so_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $729
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $730
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $653
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $654
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$230
-    connect \B \busy_o$53
-    connect \Y $729
+    connect \A \fus_xer_so_ok$154
+    connect \B \cu_busy_o$15
+    connect \Y $653
   end
   process $group_274
     assign \wrflag_mul0_xer_so_3 1'0
-    assign \wrflag_mul0_xer_so_3 $729
+    assign \wrflag_mul0_xer_so_3 $653
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $731
+  wire width 2 $655
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 1 $732
+  wire width 1 $656
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $733
+  cell $or $657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_dest4_o$232
-    connect \B \fus_dest4_o$233
-    connect \Y $732
+    connect \A \fus_dest4_o$156
+    connect \B \fus_dest4_o$157
+    connect \Y $656
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 1 $734
+  wire width 1 $658
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $735
+  cell $or $659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_dest5_o$231
-    connect \B $732
-    connect \Y $734
+    connect \A \fus_dest5_o$155
+    connect \B $656
+    connect \Y $658
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $pos $736
+  cell $pos $660
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 2
-    connect \A $734
-    connect \Y $731
+    connect \A $658
+    connect \Y $655
   end
   process $group_275
-    assign \xer_data_i$251 2'00
-    assign \xer_data_i$251 $731
+    assign \xer_data_i$175 2'00
+    assign \xer_data_i$175 $655
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  wire width 8 $737
+  wire width 8 $661
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  cell $sshl $738
+  cell $sshl $662
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156902,91 +157164,91 @@ module \core
     parameter \Y_WIDTH 8
     connect \A 1'1
     connect \B \fasto1
-    connect \Y $737
+    connect \Y $661
   end
   process $group_276
     assign \fast_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_FAST_fast1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \fast_wen $737
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \fast_wen $661
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \fast_wen 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_branch0_fast1_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $739
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $740
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $663
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $664
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_fast1_ok
-    connect \B \busy_o$14
-    connect \Y $739
+    connect \B \cu_busy_o$6
+    connect \Y $663
   end
   process $group_277
     assign \wrflag_branch0_fast1_0 1'0
-    assign \wrflag_branch0_fast1_0 $739
+    assign \wrflag_branch0_fast1_0 $663
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $741
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $742
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $665
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $666
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$124 [0]
+    connect \A \cu_wr__rel_o$74 [0]
     connect \B \fu_enable [2]
-    connect \Y $741
+    connect \Y $665
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $743
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $744
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $667
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $668
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$105 [1]
+    connect \A \cu_wr__rel_o$55 [1]
     connect \B \fu_enable [3]
-    connect \Y $743
+    connect \Y $667
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $745
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $746
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $669
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $670
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$109 [2]
+    connect \A \cu_wr__rel_o$59 [2]
     connect \B \fu_enable [5]
-    connect \Y $745
+    connect \Y $669
   end
   process $group_278
     assign \wrpick_FAST_fast1_i 3'000
-    assign \wrpick_FAST_fast1_i [0] $741
-    assign \wrpick_FAST_fast1_i [1] $743
-    assign \wrpick_FAST_fast1_i [2] $745
+    assign \wrpick_FAST_fast1_i [0] $665
+    assign \wrpick_FAST_fast1_i [1] $667
+    assign \wrpick_FAST_fast1_i [2] $669
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $747
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $748
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $671
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $672
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156994,12 +157256,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast1_o [0]
     connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $747
+    connect \Y $671
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $749
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $750
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $673
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $674
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -157007,12 +157269,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast2_o [0]
     connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $749
+    connect \Y $673
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $751
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $752
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  wire width 1 $675
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
+  cell $and $676
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -157020,90 +157282,90 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_nia_o [0]
     connect \B \wrpick_FAST_nia_en_o
-    connect \Y $751
+    connect \Y $675
   end
   process $group_279
-    assign \wr__go$125 3'000
-    assign \wr__go$125 [0] $747
-    assign \wr__go$125 [1] $749
-    assign \wr__go$125 [2] $751
+    assign \cu_wr__go_i$75 3'000
+    assign \cu_wr__go_i$75 [0] $671
+    assign \cu_wr__go_i$75 [1] $673
+    assign \cu_wr__go_i$75 [2] $675
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_fast1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $753
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $754
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $677
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $678
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast1_ok$234
-    connect \B \busy_o$22
-    connect \Y $753
+    connect \A \fus_fast1_ok$158
+    connect \B \cu_busy_o$9
+    connect \Y $677
   end
   process $group_280
     assign \wrflag_trap0_fast1_1 1'0
-    assign \wrflag_trap0_fast1_1 $753
+    assign \wrflag_trap0_fast1_1 $677
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_fast1_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $755
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $756
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $679
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $680
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast1_ok$235
-    connect \B \busy_o$42
-    connect \Y $755
+    connect \A \fus_fast1_ok$159
+    connect \B \cu_busy_o$13
+    connect \Y $679
   end
   process $group_281
     assign \wrflag_spr0_fast1_2 1'0
-    assign \wrflag_spr0_fast1_2 $755
+    assign \wrflag_spr0_fast1_2 $679
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $757
+  wire width 64 $681
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $758
+  cell $or $682
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \fus_dest2_o$236
-    connect \B \fus_dest3_o$237
-    connect \Y $757
+    connect \A \fus_dest2_o$160
+    connect \B \fus_dest3_o$161
+    connect \Y $681
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $759
+  wire width 64 $683
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $760
+  cell $or $684
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \dest1_o$126
-    connect \B $757
-    connect \Y $759
+    connect \A \dest1_o$76
+    connect \B $681
+    connect \Y $683
   end
   process $group_282
     assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i $759
+    assign \fast_data_i $683
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  wire width 8 $761
+  wire width 8 $685
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  cell $sshl $762
+  cell $sshl $686
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -157111,379 +157373,379 @@ module \core
     parameter \Y_WIDTH 8
     connect \A 1'1
     connect \B \fasto2
-    connect \Y $761
+    connect \Y $685
   end
   process $group_283
-    assign \fast_wen$252 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    assign \fast_wen$176 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_FAST_fast2_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \fast_wen$252 $761
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \fast_wen$176 $685
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \fast_wen$252 8'00000000
+        assign \fast_wen$176 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_branch0_fast2_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $763
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $764
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $687
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_fast2_ok
-    connect \B \busy_o$14
-    connect \Y $763
+    connect \B \cu_busy_o$6
+    connect \Y $687
   end
   process $group_284
     assign \wrflag_branch0_fast2_1 1'0
-    assign \wrflag_branch0_fast2_1 $763
+    assign \wrflag_branch0_fast2_1 $687
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $765
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $766
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $689
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $690
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$124 [1]
+    connect \A \cu_wr__rel_o$74 [1]
     connect \B \fu_enable [2]
-    connect \Y $765
+    connect \Y $689
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $767
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $768
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $691
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$105 [2]
+    connect \A \cu_wr__rel_o$55 [2]
     connect \B \fu_enable [3]
-    connect \Y $767
+    connect \Y $691
   end
   process $group_285
     assign \wrpick_FAST_fast2_i 2'00
-    assign \wrpick_FAST_fast2_i [0] $765
-    assign \wrpick_FAST_fast2_i [1] $767
+    assign \wrpick_FAST_fast2_i [0] $689
+    assign \wrpick_FAST_fast2_i [1] $691
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_fast2_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $769
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $770
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $693
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $694
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast2_ok$238
-    connect \B \busy_o$22
-    connect \Y $769
+    connect \A \fus_fast2_ok$162
+    connect \B \cu_busy_o$9
+    connect \Y $693
   end
   process $group_286
     assign \wrflag_trap0_fast2_2 1'0
-    assign \wrflag_trap0_fast2_2 $769
+    assign \wrflag_trap0_fast2_2 $693
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $771
+  wire width 64 $695
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $772
+  cell $or $696
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \fus_dest2_o$239
-    connect \B \fus_dest3_o$240
-    connect \Y $771
+    connect \A \fus_dest2_o$163
+    connect \B \fus_dest3_o$164
+    connect \Y $695
   end
   process $group_287
-    assign \fast_data_i$253 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$253 $771
+    assign \fast_data_i$177 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$177 $695
     sync init
   end
   process $group_288
     assign \fast_nia_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_FAST_nia_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
         assign \fast_nia_wen 8'00000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \fast_nia_wen 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_branch0_nia_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $773
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $774
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $697
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $698
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_nia_ok
-    connect \B \busy_o$14
-    connect \Y $773
+    connect \B \cu_busy_o$6
+    connect \Y $697
   end
   process $group_289
     assign \wrflag_branch0_nia_2 1'0
-    assign \wrflag_branch0_nia_2 $773
+    assign \wrflag_branch0_nia_2 $697
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $775
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $776
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $699
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $700
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$124 [2]
+    connect \A \cu_wr__rel_o$74 [2]
     connect \B \fu_enable [2]
-    connect \Y $775
+    connect \Y $699
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $777
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $778
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $701
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $702
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$105 [3]
+    connect \A \cu_wr__rel_o$55 [3]
     connect \B \fu_enable [3]
-    connect \Y $777
+    connect \Y $701
   end
   process $group_290
     assign \wrpick_FAST_nia_i 2'00
-    assign \wrpick_FAST_nia_i [0] $775
-    assign \wrpick_FAST_nia_i [1] $777
+    assign \wrpick_FAST_nia_i [0] $699
+    assign \wrpick_FAST_nia_i [1] $701
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_nia_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $779
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $780
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $703
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $704
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_nia_ok$241
-    connect \B \busy_o$22
-    connect \Y $779
+    connect \A \fus_nia_ok$165
+    connect \B \cu_busy_o$9
+    connect \Y $703
   end
   process $group_291
     assign \wrflag_trap0_nia_3 1'0
-    assign \wrflag_trap0_nia_3 $779
+    assign \wrflag_trap0_nia_3 $703
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $781
+  wire width 64 $705
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $782
+  cell $or $706
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \fus_dest3_o$242
-    connect \B \fus_dest4_o$243
-    connect \Y $781
+    connect \A \fus_dest3_o$166
+    connect \B \fus_dest4_o$167
+    connect \Y $705
   end
   process $group_292
-    assign \fast_data_i$254 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$254 $781
+    assign \fast_data_i$178 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$178 $705
     sync init
   end
   process $group_293
-    assign \fast_wen$255 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    assign \fast_wen$179 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_FAST_msr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \fast_wen$255 8'00000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+        assign \fast_wen$179 8'00000010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \fast_wen$255 8'00000000
+        assign \fast_wen$179 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_msr_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $783
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $784
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $707
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $708
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_msr_ok
-    connect \B \busy_o$22
-    connect \Y $783
+    connect \B \cu_busy_o$9
+    connect \Y $707
   end
   process $group_294
     assign \wrflag_trap0_msr_4 1'0
-    assign \wrflag_trap0_msr_4 $783
+    assign \wrflag_trap0_msr_4 $707
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $785
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $786
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $709
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $710
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$105 [4]
+    connect \A \cu_wr__rel_o$55 [4]
     connect \B \fu_enable [3]
-    connect \Y $785
+    connect \Y $709
   end
   process $group_295
     assign \wrpick_FAST_msr_i 1'0
-    assign \wrpick_FAST_msr_i $785
+    assign \wrpick_FAST_msr_i $709
     sync init
   end
   process $group_296
-    assign \fast_data_i$256 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$256 \fus_dest5_o$244
+    assign \fast_data_i$180 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$180 \fus_dest5_o$168
     sync init
   end
   process $group_297
     assign \spr_dest__wen 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_SPR_spr1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
         assign \spr_dest__wen \spro [0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \spr_dest__wen 1'0
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_spr1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  wire width 1 $787
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
-  cell $and $788
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  wire width 1 $711
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+  cell $and $712
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_spr1_ok
-    connect \B \busy_o$42
-    connect \Y $787
+    connect \B \cu_busy_o$13
+    connect \Y $711
   end
   process $group_298
     assign \wrflag_spr0_spr1_1 1'0
-    assign \wrflag_spr0_spr1_1 $787
+    assign \wrflag_spr0_spr1_1 $711
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  wire width 1 $789
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
-  cell $and $790
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  wire width 1 $713
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
+  cell $and $714
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr__rel$109 [1]
+    connect \A \cu_wr__rel_o$59 [1]
     connect \B \fu_enable [5]
-    connect \Y $789
+    connect \Y $713
   end
   process $group_299
     assign \wrpick_SPR_spr1_i 1'0
-    assign \wrpick_SPR_spr1_i $789
+    assign \wrpick_SPR_spr1_i $713
     sync init
   end
   process $group_300
     assign \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \spr_dest__data_i \fus_dest2_o$245
+    assign \spr_dest__data_i \fus_dest2_o$169
     sync init
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.imem"
 module \imem
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:21"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
   wire width 48 input 0 \a_pc_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:23"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
   wire width 1 input 1 \a_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
   wire width 1 input 2 \f_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:29"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
   wire width 1 output 3 \f_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:30"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
   wire width 64 output 4 \f_instr_o
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 5 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 6 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 output 7 \ibus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 \ibus__cyc$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:22"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
   wire width 1 input 8 \a_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 input 9 \ibus__ack
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 input 10 \ibus__err
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 output 11 \ibus__stb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 \ibus__stb$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 64 input 12 \ibus__dat_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 45 output 13 \ibus__adr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 45 \ibus__adr$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
   wire width 1 input 14 \f_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
   wire width 1 output 15 \f_fetch_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
   wire width 1 \f_fetch_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
   wire width 45 output 16 \f_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
   wire width 45 \f_badaddr_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
   wire width 1 output 17 \a_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157491,9 +157753,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157504,9 +157766,9 @@ module \imem
     connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157517,9 +157779,9 @@ module \imem
     connect \B \ibus__err
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157527,9 +157789,9 @@ module \imem
     connect \A \f_valid_i
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157542,17 +157804,17 @@ module \imem
   end
   process $group_0
     assign \ibus__cyc$next \ibus__cyc
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
     switch { $3 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
         switch { $9 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
           case 1'1
             assign \ibus__cyc$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
       case 2'1-
         assign \ibus__cyc$next 1'1
     end
@@ -157566,9 +157828,9 @@ module \imem
     sync posedge \clk
       update \ibus__cyc \ibus__cyc$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157576,9 +157838,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $and $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157589,9 +157851,9 @@ module \imem
     connect \B $11
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157602,9 +157864,9 @@ module \imem
     connect \B \ibus__err
     connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157612,9 +157874,9 @@ module \imem
     connect \A \f_valid_i
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $or $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157627,17 +157889,17 @@ module \imem
   end
   process $group_1
     assign \ibus__stb$next \ibus__stb
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
     switch { $13 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
         switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
           case 1'1
             assign \ibus__stb$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
       case 2'1-
         assign \ibus__stb$next 1'1
     end
@@ -157651,13 +157913,13 @@ module \imem
     sync posedge \clk
       update \ibus__stb \ibus__stb$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
   wire width 64 \ibus_rdata
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
   wire width 64 \ibus_rdata$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157665,9 +157927,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $and $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157678,9 +157940,9 @@ module \imem
     connect \B $21
     connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $or $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157691,9 +157953,9 @@ module \imem
     connect \B \ibus__err
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $not $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157701,9 +157963,9 @@ module \imem
     connect \A \f_valid_i
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
   cell $or $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157716,17 +157978,17 @@ module \imem
   end
   process $group_2
     assign \ibus_rdata$next \ibus_rdata
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
     switch { $23 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
         switch { $29 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:58"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
           case 1'1
             assign \ibus_rdata$next \ibus__dat_r
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
       case 2'1-
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -157739,9 +158001,9 @@ module \imem
     sync posedge \clk
       update \ibus_rdata \ibus_rdata$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $not $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157749,9 +158011,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
   cell $and $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157764,11 +158026,11 @@ module \imem
   end
   process $group_3
     assign \ibus__adr$next \ibus__adr
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
     switch { $33 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:57"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:64"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
       case 2'1-
         assign \ibus__adr$next \a_pc_i [47:3]
     end
@@ -157782,9 +158044,9 @@ module \imem
     sync posedge \clk
       update \ibus__adr \ibus__adr$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
   cell $and $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157795,9 +158057,9 @@ module \imem
     connect \B \ibus__err
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
   cell $not $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157807,12 +158069,12 @@ module \imem
   end
   process $group_4
     assign \f_fetch_err_o$next \f_fetch_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
     switch { $37 $35 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
       case 2'-1
         assign \f_fetch_err_o$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
       case 2'1-
         assign \f_fetch_err_o$next 1'0
     end
@@ -157826,9 +158088,9 @@ module \imem
     sync posedge \clk
       update \f_fetch_err_o \f_fetch_err_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
   cell $and $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157839,9 +158101,9 @@ module \imem
     connect \B \ibus__err
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
   cell $not $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157851,12 +158113,12 @@ module \imem
   end
   process $group_5
     assign \f_badaddr_o$next \f_badaddr_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
     switch { $41 $39 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
       case 2'-1
         assign \f_badaddr_o$next \ibus__adr
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
       case 2'1-
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -157876,12 +158138,12 @@ module \imem
   end
   process $group_7
     assign \f_busy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
     switch { \f_fetch_err_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
       case 1'1
         assign \f_busy_o 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:83"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
       case
         assign \f_busy_o \ibus__cyc
     end
@@ -157889,11 +158151,11 @@ module \imem
   end
   process $group_8
     assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
     switch { \f_fetch_err_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
       case 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:83"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
       case
         assign \f_instr_o \ibus_rdata
     end
@@ -157904,9 +158166,9 @@ attribute \generator "nMigen"
 attribute \top 1
 attribute \nmigen.hierarchy "test_issuer"
 module \test_issuer
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 input 0 \pc_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 1 \pc_i_ok
   attribute \src "simple/issuer.py:49"
   wire width 64 output 2 \pc_o
@@ -157915,15 +158177,15 @@ module \test_issuer
   attribute \src "simple/issuer.py:56"
   wire width 1 input 4 \memerr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 5 \rd__go
+  wire width 4 output 5 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 6 \wr__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 7 \issue_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 8 \shadown_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 9 \go_die_i
+  wire width 5 output 6 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 output 7 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 8 \cu_shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 9 \cu_go_die_i
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -157997,8 +158259,8 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 10 \oper_i__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 10 \oper_i_alu_alu0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -158011,54 +158273,54 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 11 \oper_i__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 12 \oper_i__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 13 \oper_i__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 14 \oper_i__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 15 \oper_i__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 11 \oper_i_alu_alu0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 12 \oper_i_alu_alu0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 13 \oper_i_alu_alu0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 14 \oper_i_alu_alu0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 15 \oper_i_alu_alu0__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 16 \oper_i__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 17 \oper_i__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 18 \oper_i__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 19 \oper_i__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 20 \oper_i__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 21 \oper_i__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 16 \oper_i_alu_alu0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 17 \oper_i_alu_alu0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 18 \oper_i_alu_alu0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 19 \oper_i_alu_alu0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 20 \oper_i_alu_alu0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 21 \oper_i_alu_alu0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 output 22 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 output 23 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 24 \busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 24 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 25 \rd__rel
+  wire width 4 output 25 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 26 \wr__rel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+  wire width 5 output 26 \cu_wr__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 27 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 28 \rd__go$1
+  wire width 6 output 28 \cu_rd__go_i$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 29 \wr__go$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 30 \issue_i$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 31 \shadown_i$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 32 \go_die_i$5
+  wire width 3 output 29 \cu_wr__go_i$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 output 30 \cu_issue_i$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 31 \cu_shadown_i$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 32 \cu_go_die_i$5
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -158132,8 +158394,8 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 33 \oper_i__insn_type$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 33 \oper_i_alu_cr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -158146,38 +158408,38 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 34 \oper_i__fn_unit$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 35 \oper_i__insn$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 36 \oper_i__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 37 \oper_i__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 38 \src1_i$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 39 \src2_i$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 40 \busy_o$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 34 \oper_i_alu_cr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 35 \oper_i_alu_cr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \oper_i_alu_cr0__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \oper_i_alu_cr0__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 38 \src1_i$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 39 \src2_i$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 40 \cu_busy_o$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 41 \rd__rel$12
+  wire width 6 output 41 \cu_rd__rel_o$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 42 \wr__rel$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 43 \dest1_o$14
+  wire width 3 output 42 \cu_wr__rel_o$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 43 \dest1_o$11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 44 \rd__go$15
+  wire width 3 output 44 \cu_rd__go_i$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 45 \wr__go$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 46 \issue_i$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 47 \shadown_i$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 48 \go_die_i$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 49 \oper_i__cia
+  wire width 3 output 45 \cu_wr__go_i$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 output 46 \cu_issue_i$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 47 \cu_shadown_i$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 48 \cu_go_die_i$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 49 \oper_i_alu_branch0__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -158251,8 +158513,8 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 50 \oper_i__insn_type$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 50 \oper_i_alu_branch0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -158265,36 +158527,36 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 51 \oper_i__fn_unit$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 52 \oper_i__insn$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 53 \oper_i__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 54 \oper_i__is_32bit$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 55 \src1_i$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 56 \src2_i$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 57 \busy_o$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 51 \oper_i_alu_branch0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 52 \oper_i_alu_branch0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 53 \oper_i_alu_branch0__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 54 \oper_i_alu_branch0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 55 \src1_i$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 56 \src2_i$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 57 \cu_busy_o$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 58 \rd__rel$27
+  wire width 3 output 58 \cu_rd__rel_o$20
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 59 \wr__rel$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 60 \dest1_o$29
+  wire width 3 output 59 \cu_wr__rel_o$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 60 \dest1_o$22
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 61 \rd__go$30
+  wire width 4 output 61 \cu_rd__go_i$23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 62 \wr__go$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 63 \issue_i$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 64 \shadown_i$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 65 \go_die_i$34
+  wire width 5 output 62 \cu_wr__go_i$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 output 63 \cu_issue_i$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 64 \cu_shadown_i$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 65 \cu_go_die_i$27
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -158368,8 +158630,8 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 66 \oper_i__insn_type$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 66 \oper_i_alu_trap0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -158382,42 +158644,42 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 67 \oper_i__fn_unit$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 68 \oper_i__insn$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 69 \oper_i__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 64 output 70 \oper_i__cia$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 71 \oper_i__is_32bit$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 5 output 72 \oper_i__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 13 output 73 \oper_i__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 74 \src1_i$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 75 \src2_i$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 76 \busy_o$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 67 \oper_i_alu_trap0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 68 \oper_i_alu_trap0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 69 \oper_i_alu_trap0__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 70 \oper_i_alu_trap0__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 71 \oper_i_alu_trap0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 output 72 \oper_i_alu_trap0__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 output 73 \oper_i_alu_trap0__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 74 \src1_i$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 75 \src2_i$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 76 \cu_busy_o$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 77 \rd__rel$43
+  wire width 4 output 77 \cu_rd__rel_o$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 78 \wr__rel$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 79 \dest1_o$45
+  wire width 5 output 78 \cu_wr__rel_o$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 79 \dest1_o$33
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 80 \rd__go$46
+  wire width 2 output 80 \cu_rd__go_i$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 81 \wr__go$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 82 \issue_i$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 83 \shadown_i$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 84 \go_die_i$50
+  wire width 3 output 81 \cu_wr__go_i$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 output 82 \cu_issue_i$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 83 \cu_shadown_i$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 84 \cu_go_die_i$38
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -158491,8 +158753,8 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 85 \oper_i__insn_type$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 85 \oper_i_alu_logical0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -158505,169 +158767,54 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 86 \oper_i__fn_unit$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 87 \oper_i__invert_a$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 88 \oper_i__zero_a$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 86 \oper_i_alu_logical0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 87 \oper_i_alu_logical0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 88 \oper_i_alu_logical0__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 89 \oper_i__input_carry$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 90 \oper_i__invert_out$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 91 \oper_i__write_cr0$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 92 \oper_i__output_carry$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 93 \oper_i__is_32bit$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 94 \oper_i__is_signed$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 95 \oper_i__data_len$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 96 \oper_i__insn$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 97 \src1_i$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 98 \src2_i$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 99 \busy_o$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 89 \oper_i_alu_logical0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 90 \oper_i_alu_logical0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 91 \oper_i_alu_logical0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 92 \oper_i_alu_logical0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 93 \oper_i_alu_logical0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 94 \oper_i_alu_logical0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 95 \oper_i_alu_logical0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 96 \oper_i_alu_logical0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 97 \src1_i$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 98 \src2_i$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 99 \cu_busy_o$41
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 100 \rd__rel$66
+  wire width 2 output 100 \cu_rd__rel_o$42
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 101 \wr__rel$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 102 \dest1_o$68
+  wire width 3 output 101 \cu_wr__rel_o$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 102 \dest1_o$44
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 103 \rd__go$69
+  wire width 6 output 103 \cu_rd__go_i$45
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 104 \wr__go$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 105 \issue_i$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 106 \shadown_i$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 107 \go_die_i$73
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 108 \oper_i__insn_type$74
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 109 \oper_i__fn_unit$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 110 \oper_i__insn$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 111 \oper_i__is_32bit$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 112 \src1_i$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 113 \src2_i$79
+  wire width 6 output 104 \cu_wr__go_i$46
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 114 \busy_o$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 115 \rd__rel$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 116 \wr__rel$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 117 \dest1_o$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 118 \rd__go$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 119 \wr__go$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 120 \issue_i$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 121 \shadown_i$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 122 \go_die_i$88
+  wire width 1 output 105 \cu_issue_i$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 106 \cu_shadown_i$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 107 \cu_go_die_i$49
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -158741,8 +158888,8 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 123 \oper_i__insn_type$89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 108 \oper_i_alu_spr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -158755,44 +158902,159 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 124 \oper_i__fn_unit$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 125 \oper_i__invert_a$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 126 \oper_i__zero_a$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 127 \oper_i__invert_out$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 128 \oper_i__write_cr0$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 129 \oper_i__is_32bit$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 130 \oper_i__is_signed$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 131 \oper_i__insn$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 132 \src1_i$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 133 \src2_i$99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 109 \oper_i_alu_spr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 110 \oper_i_alu_spr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 111 \oper_i_alu_spr0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 112 \src1_i$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 113 \src2_i$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 114 \cu_busy_o$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 output 115 \cu_rd__rel_o$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 output 116 \cu_wr__rel_o$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 117 \dest1_o$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 118 \cu_rd__go_i$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 output 119 \cu_wr__go_i$57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 134 \busy_o$100
+  wire width 1 output 120 \cu_issue_i$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 121 \cu_shadown_i$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 122 \cu_go_die_i$60
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 123 \oper_i_alu_mul0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 124 \oper_i_alu_mul0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 125 \oper_i_alu_mul0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 126 \oper_i_alu_mul0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 127 \oper_i_alu_mul0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 128 \oper_i_alu_mul0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 129 \oper_i_alu_mul0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 130 \oper_i_alu_mul0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 131 \oper_i_alu_mul0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 132 \src1_i$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 133 \src2_i$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 134 \cu_busy_o$63
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 135 \rd__rel$101
+  wire width 3 output 135 \cu_rd__rel_o$64
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 136 \wr__rel$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 137 \dest1_o$103
+  wire width 4 output 136 \cu_wr__rel_o$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 137 \dest1_o$66
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 138 \rd__go$104
+  wire width 4 output 138 \cu_rd__go_i$67
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 139 \wr__go$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 140 \issue_i$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 141 \shadown_i$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 142 \go_die_i$108
+  wire width 3 output 139 \cu_wr__go_i$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 output 140 \cu_issue_i$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 141 \cu_shadown_i$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 142 \cu_go_die_i$71
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -158866,8 +159128,8 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 143 \oper_i__insn_type$109
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 143 \oper_i_alu_shift_rot0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -158880,52 +159142,52 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 11 output 144 \oper_i__fn_unit$110
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 144 \oper_i_alu_shift_rot0__fn_unit
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 146 \oper_i__input_carry$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 147 \oper_i__output_carry$112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 148 \oper_i__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 149 \oper_i__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 150 \oper_i__is_32bit$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 151 \oper_i__is_signed$114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 32 output 152 \oper_i__insn$115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 153 \src1_i$116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 154 \src2_i$117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 155 \busy_o$118
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 146 \oper_i_alu_shift_rot0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 147 \oper_i_alu_shift_rot0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 148 \oper_i_alu_shift_rot0__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 149 \oper_i_alu_shift_rot0__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 150 \oper_i_alu_shift_rot0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 151 \oper_i_alu_shift_rot0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 152 \oper_i_alu_shift_rot0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 153 \src1_i$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 154 \src2_i$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 155 \cu_busy_o$74
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 156 \rd__rel$119
+  wire width 4 output 156 \cu_rd__rel_o$75
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 157 \wr__rel$120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
-  wire width 64 output 158 \dest1_o$121
+  wire width 3 output 157 \cu_wr__rel_o$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 158 \dest1_o$77
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 159 \rd__go$122
+  wire width 3 output 159 \cu_rd__go_i$78
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 160 \ad__go
+  wire width 1 output 160 \ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 161 \wr__go$123
+  wire width 2 output 161 \cu_wr__go_i$79
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 162 \st__go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
-  wire width 1 output 163 \issue_i$124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 1 input 164 \shadown_i$125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 1 input 165 \go_die_i$126
+  wire width 1 output 162 \st__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 output 163 \cu_issue_i$80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 input 164 \cu_shadown_i$81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 input 165 \cu_go_die_i$82
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -158999,60 +159261,60 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 7 output 166 \oper_i__insn_type$127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 167 \oper_i__zero_a$128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 168 \oper_i__is_32bit$129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 169 \oper_i__is_signed$130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 4 output 170 \oper_i__data_len$131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 171 \oper_i__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 1 output 172 \oper_i__sign_extend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 166 \oper_i_ldst_ldst0__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 167 \oper_i_ldst_ldst0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 168 \oper_i_ldst_ldst0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 169 \oper_i_ldst_ldst0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 170 \oper_i_ldst_ldst0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 171 \oper_i_ldst_ldst0__byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 172 \oper_i_ldst_ldst0__sign_extend
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
-  wire width 2 output 173 \oper_i__ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 174 \src1_i$132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
-  wire width 64 output 175 \src2_i$133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 173 \oper_i_ldst_ldst0__ldst_mode
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 174 \src1_i$83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 output 175 \src2_i$84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 output 176 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 177 \busy_o$134
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 177 \cu_busy_o$85
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 178 \rd__rel$135
+  wire width 3 output 178 \cu_rd__rel_o$86
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 179 \ad__rel
+  wire width 1 output 179 \ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 180 \st__rel
+  wire width 1 output 180 \st__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 181 \wr__rel$136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  wire width 2 output 181 \cu_wr__rel_o$87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 182 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 183 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 184 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 185 \ea_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
   wire width 1 output 186 \load_mem_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
   wire width 1 output 187 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
   wire width 32 output 188 \raw_opcode_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 input 189 \bigendian
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 output 190 \opcode_in
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -159066,7 +159328,7 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
   wire width 11 output 191 \function_unit
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
@@ -159074,7 +159336,7 @@ module \test_issuer
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
   wire width 3 output 192 \in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
@@ -159091,20 +159353,20 @@ module \test_issuer
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
   wire width 4 output 193 \in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
   wire width 2 output 194 \in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
   wire width 2 output 195 \out_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
@@ -159114,7 +159376,7 @@ module \test_issuer
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
   wire width 3 output 196 \cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
@@ -159122,7 +159384,7 @@ module \test_issuer
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
   wire width 3 output 197 \cr_out
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
@@ -159130,13 +159392,13 @@ module \test_issuer
   attribute \enum_value_0010 "is2B"
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
   wire width 4 output 198 \ldst_len
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
   wire width 2 output 199 \rc_sel
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -159211,7 +159473,7 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
   wire width 7 output 200 \internal_op
   attribute \enum_base_type "Form"
   attribute \enum_value_00000 "NONE"
@@ -159243,51 +159505,51 @@ module \test_issuer
   attribute \enum_value_11010 "EVS"
   attribute \enum_value_11011 "Z22"
   attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
   wire width 5 output 201 \form
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
   wire width 8 output 202 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 203 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 204 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 205 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 206 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 207 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 208 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 209 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 210 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 211 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
   wire width 1 output 212 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
-  wire width 8 output 213 \asmcode$137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
+  wire width 8 output 213 \asmcode$88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 214 \rego
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 215 \rego_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 5 output 216 \ea$138
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 217 \ea_ok$139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 5 output 216 \ea$89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 217 \ea_ok$90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 218 \reg1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 219 \reg1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 220 \reg2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 221 \reg2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 222 \reg3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 223 \reg3_ok
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -159400,9 +159662,9 @@ module \test_issuer
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 224 \spro
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 225 \spro_ok
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -159515,51 +159777,51 @@ module \test_issuer
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 226 \spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 227 \spr1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:81"
-  wire width 1 output 228 \xer_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
+  wire width 1 output 228 \xer_in
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83"
   wire width 1 output 229 \xer_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 230 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 231 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 232 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 233 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 234 \fasto1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 235 \fasto1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 236 \fasto2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 237 \fasto2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 238 \cr_in1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 239 \cr_in1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 240 \cr_in2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 241 \cr_in2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 3 output 242 \cr_in2$140
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 243 \cr_in2_ok$141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 3 output 244 \cr_out$142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 output 242 \cr_in2$91
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 243 \cr_in2_ok$92
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 output 244 \cr_out$93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 245 \cr_out_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
-  wire width 64 output 246 \msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+  wire width 64 output 246 \msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
   wire width 64 output 247 \cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
   wire width 32 output 248 \insn
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -159634,7 +159896,7 @@ module \test_issuer
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
   wire width 7 output 249 \insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
@@ -159648,66 +159910,66 @@ module \test_issuer
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40"
   wire width 11 output 250 \fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 251 \imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 252 \imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41"
-  wire width 1 output 253 \lk$143
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
+  wire width 1 output 253 \lk$94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 254 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 255 \rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 256 \oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 257 \oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
-  wire width 1 output 258 \invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
+  wire width 1 output 258 \invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
   wire width 1 output 259 \zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
-  wire width 2 output 260 \input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
-  wire width 1 output 261 \output_carry
+  wire width 2 output 260 \input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
-  wire width 1 output 262 \input_cr
+  wire width 1 output 261 \output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
-  wire width 1 output 263 \output_cr
+  wire width 1 output 262 \input_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
-  wire width 1 output 264 \invert_out
+  wire width 1 output 263 \output_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
-  wire width 1 output 265 \is_32bit
+  wire width 1 output 264 \invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
-  wire width 1 output 266 \is_signed
+  wire width 1 output 265 \is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
-  wire width 4 output 267 \data_len
+  wire width 1 output 266 \is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
-  wire width 1 output 268 \byte_reverse
+  wire width 4 output 267 \data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+  wire width 1 output 268 \byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
   wire width 1 output 269 \sign_extend
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
   attribute \enum_value_10 "cix"
   attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
-  wire width 2 output 270 \ldst_mode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
-  wire width 5 output 271 \traptype
+  wire width 2 output 270 \ldst_mode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
-  wire width 13 output 272 \trapaddr
+  wire width 5 output 271 \traptype
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
-  wire width 1 output 273 \read_cr_whole
+  wire width 13 output 272 \trapaddr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
-  wire width 1 output 274 \write_cr_whole
+  wire width 1 output 273 \read_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
+  wire width 1 output 274 \write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
   wire width 1 output 275 \write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 output 276 \ldst_port0_is_ld_i
@@ -159719,21 +159981,21 @@ module \test_issuer
   wire width 1 output 279 \ldst_port0_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
   wire width 1 output 280 \ldst_port0_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 48 output 281 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 282 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
   wire width 1 output 283 \ldst_port0_addr_ok_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 input 284 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 285 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 286 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 287 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 288 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
   wire width 48 output 289 \x_addr_i
@@ -159763,7 +160025,7 @@ module \test_issuer
   wire width 1 output 301 \m_load_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
   wire width 1 output 302 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
   wire width 45 output 303 \m_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 45 output 304 \dbus__adr
@@ -159788,100 +160050,110 @@ module \test_issuer
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 input 314 \dbus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 315 \ldst_port0_is_ld_i$144
+  wire width 1 output 315 \ldst_port0_is_ld_i$95
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 316 \ldst_port0_is_st_i$145
+  wire width 1 output 316 \ldst_port0_is_st_i$96
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 317 \ldst_port0_data_len$146
+  wire width 4 output 317 \ldst_port0_data_len$97
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 318 \ldst_port0_busy_o$147
+  wire width 1 output 318 \ldst_port0_busy_o$98
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 input 319 \ldst_port0_go_die_i$148
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 96 output 320 \ldst_port0_addr_i$149
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 321 \ldst_port0_addr_i_ok$150
+  wire width 1 input 319 \ldst_port0_go_die_i$99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 96 output 320 \ldst_port0_addr_i$100
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 321 \ldst_port0_addr_i_ok$101
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 322 \ldst_port0_addr_ok_o$151
+  wire width 1 output 322 \ldst_port0_addr_ok_o$102
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 output 323 \ldst_port0_addr_exc_o$152
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 64 output 324 \ldst_port0_ld_data_o$153
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 325 \ldst_port0_ld_data_o_ok$154
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 64 output 326 \ldst_port0_st_data_i$155
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
-  wire width 1 output 327 \ldst_port0_st_data_i_ok$156
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:21"
+  wire width 1 output 323 \ldst_port0_addr_exc_o$103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 324 \ldst_port0_ld_data_o$104
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 325 \ldst_port0_ld_data_o_ok$105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 326 \ldst_port0_st_data_i$106
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 327 \ldst_port0_st_data_i_ok$107
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
   wire width 48 output 328 \a_pc_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:22"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
   wire width 1 input 329 \a_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:23"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
   wire width 1 output 330 \a_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
   wire width 1 input 331 \f_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
-  wire width 1 output 332 \f_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
+  wire width 1 output 332 \f_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
   wire width 1 output 333 \a_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:29"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
   wire width 1 output 334 \f_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:30"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
   wire width 64 output 335 \f_instr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
   wire width 1 output 336 \f_fetch_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
   wire width 45 output 337 \f_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 45 output 338 \ibus__adr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 64 input 339 \ibus__dat_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 64 input 340 \ibus__dat_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 8 input 341 \ibus__sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 output 342 \ibus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 output 343 \ibus__stb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 input 344 \ibus__ack
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 input 345 \ibus__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 3 input 346 \ibus__cti
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 2 input 347 \ibus__bte
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 input 348 \ibus__err
+  attribute \src "simple/issuer.py:51"
+  wire width 1 output 349 \core_start_i
+  attribute \src "simple/issuer.py:52"
+  wire width 1 output 350 \core_stop_i
+  attribute \src "simple/issuer.py:53"
+  wire width 1 output 351 \core_bigendian_i
+  attribute \src "simple/issuer.py:54"
+  wire width 1 output 352 \busy_o
+  attribute \src "simple/issuer.py:55"
+  wire width 1 output 353 \halted_o
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 349 \clk
+  wire width 1 input 354 \clk
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 350 \rst
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
+  wire width 1 input 355 \rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
   wire width 1 \core_corebusy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
   wire width 1 \core_core_terminated_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:86"
-  wire width 1 \core_core_start_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
+  wire width 1 \core_core_start_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
   wire width 1 \core_core_stop_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \core_cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \core_cia__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:562"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571"
   wire width 1 \core_valid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:78"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
   wire width 1 \core_issue_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \core_msr__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \core_msr__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574"
   wire width 64 \core_msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
   wire width 64 \core_cia
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \core_fast_nia_wen
@@ -159895,10 +160167,10 @@ module \test_issuer
     connect \core_start_i \core_core_start_i
     connect \core_stop_i \core_core_stop_i
     connect \bigendian \bigendian
-    connect \ad__go \ad__go
-    connect \ad__rel \ad__rel
-    connect \st__go \st__go
-    connect \st__rel \st__rel
+    connect \ad__go_i \ad__go_i
+    connect \ad__rel_o \ad__rel_o
+    connect \st__go_i \st__go_i
+    connect \st__rel_o \st__rel_o
     connect \cia__ren \core_cia__ren
     connect \cia__data_o \core_cia__data_o
     connect \valid \core_valid
@@ -159915,215 +160187,215 @@ module \test_issuer
     connect \rst \rst
     connect \clk \clk
     connect \fn_unit \fn_unit
-    connect \oper_i__insn_type \oper_i__insn_type
-    connect \oper_i__fn_unit \oper_i__fn_unit
+    connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type
+    connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit
     connect \imm \imm
     connect \imm_ok \imm_ok
     connect \rc \rc
     connect \rc_ok \rc_ok
     connect \oe \oe
     connect \oe_ok \oe_ok
-    connect \oper_i__invert_a \oper_i__invert_a
+    connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a
     connect \invert_a \invert_a
-    connect \oper_i__zero_a \oper_i__zero_a
+    connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a
     connect \zero_a \zero_a
-    connect \oper_i__invert_out \oper_i__invert_out
+    connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out
     connect \invert_out \invert_out
-    connect \oper_i__write_cr0 \oper_i__write_cr0
+    connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0
     connect \write_cr0 \write_cr0
-    connect \oper_i__input_carry \oper_i__input_carry
+    connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry
     connect \input_carry \input_carry
-    connect \oper_i__output_carry \oper_i__output_carry
+    connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry
     connect \output_carry \output_carry
-    connect \oper_i__is_32bit \oper_i__is_32bit
+    connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit
     connect \is_32bit \is_32bit
-    connect \oper_i__is_signed \oper_i__is_signed
+    connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed
     connect \is_signed \is_signed
-    connect \oper_i__data_len \oper_i__data_len
+    connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len
     connect \data_len \data_len
-    connect \oper_i__insn \oper_i__insn
+    connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn
     connect \insn \insn
-    connect \issue_i$1 \issue_i
-    connect \busy_o \busy_o
+    connect \cu_issue_i \cu_issue_i
+    connect \cu_busy_o \cu_busy_o
     connect \reg1_ok \reg1_ok
     connect \reg2_ok \reg2_ok
     connect \xer_in \xer_in
-    connect \oper_i__insn_type$2 \oper_i__insn_type$6
-    connect \oper_i__fn_unit$3 \oper_i__fn_unit$7
-    connect \oper_i__insn$4 \oper_i__insn$8
-    connect \oper_i__read_cr_whole \oper_i__read_cr_whole
+    connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
+    connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
+    connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
+    connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole
     connect \read_cr_whole \read_cr_whole
-    connect \oper_i__write_cr_whole \oper_i__write_cr_whole
+    connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole
     connect \write_cr_whole \write_cr_whole
-    connect \issue_i$5 \issue_i$3
-    connect \busy_o$6 \busy_o$11
+    connect \cu_issue_i$1 \cu_issue_i$3
+    connect \cu_busy_o$2 \cu_busy_o$8
     connect \cr_in1_ok \cr_in1_ok
     connect \cr_in2_ok \cr_in2_ok
-    connect \cr_in2_ok$7 \cr_in2_ok$141
-    connect \oper_i__cia \oper_i__cia
-    connect \cia$8 \cia
-    connect \oper_i__insn_type$9 \oper_i__insn_type$20
-    connect \oper_i__fn_unit$10 \oper_i__fn_unit$21
-    connect \oper_i__insn$11 \oper_i__insn$22
-    connect \oper_i__lk \oper_i__lk
-    connect \lk \lk$143
-    connect \oper_i__is_32bit$12 \oper_i__is_32bit$23
-    connect \issue_i$13 \issue_i$17
-    connect \busy_o$14 \busy_o$26
+    connect \cr_in2_ok$3 \cr_in2_ok$92
+    connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia
+    connect \cia$4 \cia
+    connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type
+    connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit
+    connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn
+    connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk
+    connect \lk \lk$94
+    connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit
+    connect \cu_issue_i$5 \cu_issue_i$14
+    connect \cu_busy_o$6 \cu_busy_o$19
     connect \fast1_ok \fast1_ok
     connect \fast2_ok \fast2_ok
-    connect \oper_i__insn_type$15 \oper_i__insn_type$35
-    connect \oper_i__fn_unit$16 \oper_i__fn_unit$36
-    connect \oper_i__insn$17 \oper_i__insn$37
-    connect \oper_i__msr \oper_i__msr
-    connect \msr$18 \msr
-    connect \oper_i__cia$19 \oper_i__cia$38
-    connect \oper_i__is_32bit$20 \oper_i__is_32bit$39
-    connect \oper_i__traptype \oper_i__traptype
+    connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type
+    connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit
+    connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn
+    connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
+    connect \msr$7 \msr
+    connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia
+    connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit
+    connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
     connect \traptype \traptype
-    connect \oper_i__trapaddr \oper_i__trapaddr
+    connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
     connect \trapaddr \trapaddr
-    connect \issue_i$21 \issue_i$32
-    connect \busy_o$22 \busy_o$42
-    connect \oper_i__insn_type$23 \oper_i__insn_type$51
-    connect \oper_i__fn_unit$24 \oper_i__fn_unit$52
-    connect \oper_i__invert_a$25 \oper_i__invert_a$53
-    connect \oper_i__zero_a$26 \oper_i__zero_a$54
-    connect \oper_i__input_carry$27 \oper_i__input_carry$55
-    connect \oper_i__invert_out$28 \oper_i__invert_out$56
-    connect \oper_i__write_cr0$29 \oper_i__write_cr0$57
-    connect \oper_i__output_carry$30 \oper_i__output_carry$58
-    connect \oper_i__is_32bit$31 \oper_i__is_32bit$59
-    connect \oper_i__is_signed$32 \oper_i__is_signed$60
-    connect \oper_i__data_len$33 \oper_i__data_len$61
-    connect \oper_i__insn$34 \oper_i__insn$62
-    connect \issue_i$35 \issue_i$48
-    connect \busy_o$36 \busy_o$65
-    connect \oper_i__insn_type$37 \oper_i__insn_type$74
-    connect \oper_i__fn_unit$38 \oper_i__fn_unit$75
-    connect \oper_i__insn$39 \oper_i__insn$76
-    connect \oper_i__is_32bit$40 \oper_i__is_32bit$77
-    connect \issue_i$41 \issue_i$71
-    connect \busy_o$42 \busy_o$80
+    connect \cu_issue_i$8 \cu_issue_i$25
+    connect \cu_busy_o$9 \cu_busy_o$30
+    connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type
+    connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit
+    connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a
+    connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
+    connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry
+    connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out
+    connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
+    connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry
+    connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit
+    connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed
+    connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len
+    connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn
+    connect \cu_issue_i$10 \cu_issue_i$36
+    connect \cu_busy_o$11 \cu_busy_o$41
+    connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
+    connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit
+    connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn
+    connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
+    connect \cu_issue_i$12 \cu_issue_i$47
+    connect \cu_busy_o$13 \cu_busy_o$52
     connect \spr1_ok \spr1_ok
-    connect \oper_i__insn_type$43 \oper_i__insn_type$89
-    connect \oper_i__fn_unit$44 \oper_i__fn_unit$90
-    connect \oper_i__invert_a$45 \oper_i__invert_a$91
-    connect \oper_i__zero_a$46 \oper_i__zero_a$92
-    connect \oper_i__invert_out$47 \oper_i__invert_out$93
-    connect \oper_i__write_cr0$48 \oper_i__write_cr0$94
-    connect \oper_i__is_32bit$49 \oper_i__is_32bit$95
-    connect \oper_i__is_signed$50 \oper_i__is_signed$96
-    connect \oper_i__insn$51 \oper_i__insn$97
-    connect \issue_i$52 \issue_i$86
-    connect \busy_o$53 \busy_o$100
-    connect \oper_i__insn_type$54 \oper_i__insn_type$109
-    connect \oper_i__fn_unit$55 \oper_i__fn_unit$110
-    connect \oper_i__input_carry$56 \oper_i__input_carry$111
-    connect \oper_i__output_carry$57 \oper_i__output_carry$112
-    connect \oper_i__input_cr \oper_i__input_cr
+    connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type
+    connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit
+    connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a
+    connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a
+    connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out
+    connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
+    connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit
+    connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed
+    connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn
+    connect \cu_issue_i$14 \cu_issue_i$58
+    connect \cu_busy_o$15 \cu_busy_o$63
+    connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type
+    connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit
+    connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry
+    connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry
+    connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr
     connect \input_cr \input_cr
-    connect \oper_i__output_cr \oper_i__output_cr
+    connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr
     connect \output_cr \output_cr
-    connect \oper_i__is_32bit$58 \oper_i__is_32bit$113
-    connect \oper_i__is_signed$59 \oper_i__is_signed$114
-    connect \oper_i__insn$60 \oper_i__insn$115
-    connect \issue_i$61 \issue_i$106
-    connect \busy_o$62 \busy_o$118
+    connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit
+    connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed
+    connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn
+    connect \cu_issue_i$16 \cu_issue_i$69
+    connect \cu_busy_o$17 \cu_busy_o$74
     connect \reg3_ok \reg3_ok
-    connect \oper_i__insn_type$63 \oper_i__insn_type$127
-    connect \oper_i__zero_a$64 \oper_i__zero_a$128
-    connect \oper_i__is_32bit$65 \oper_i__is_32bit$129
-    connect \oper_i__is_signed$66 \oper_i__is_signed$130
-    connect \oper_i__data_len$67 \oper_i__data_len$131
-    connect \oper_i__byte_reverse \oper_i__byte_reverse
+    connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
+    connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
+    connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit
+    connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed
+    connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len
+    connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse
     connect \byte_reverse \byte_reverse
-    connect \oper_i__sign_extend \oper_i__sign_extend
+    connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
     connect \sign_extend \sign_extend
-    connect \oper_i__ldst_mode \oper_i__ldst_mode
+    connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode
     connect \ldst_mode \ldst_mode
-    connect \issue_i$68 \issue_i$124
-    connect \busy_o$69 \busy_o$134
+    connect \cu_issue_i$18 \cu_issue_i$80
+    connect \cu_busy_o$19 \cu_busy_o$85
     connect \reg1 \reg1
-    connect \rd__rel \rd__rel
-    connect \rd__go \rd__go
+    connect \cu_rd__rel_o \cu_rd__rel_o
+    connect \cu_rd__go_i \cu_rd__go_i
     connect \src1_i \src1_i
-    connect \rd__rel$70 \rd__rel$12
-    connect \rd__go$71 \rd__go$1
-    connect \src1_i$72 \src1_i$9
-    connect \rd__rel$73 \rd__rel$43
-    connect \rd__go$74 \rd__go$30
-    connect \src1_i$75 \src1_i$40
-    connect \rd__rel$76 \rd__rel$66
-    connect \rd__go$77 \rd__go$46
-    connect \src1_i$78 \src1_i$63
-    connect \rd__rel$79 \rd__rel$81
-    connect \rd__go$80 \rd__go$69
-    connect \src1_i$81 \src1_i$78
-    connect \rd__rel$82 \rd__rel$101
-    connect \rd__go$83 \rd__go$84
-    connect \src1_i$84 \src1_i$98
-    connect \rd__rel$85 \rd__rel$119
-    connect \rd__go$86 \rd__go$104
-    connect \src1_i$87 \src1_i$116
-    connect \rd__rel$88 \rd__rel$135
-    connect \rd__go$89 \rd__go$122
-    connect \src1_i$90 \src1_i$132
+    connect \cu_rd__rel_o$20 \cu_rd__rel_o$9
+    connect \cu_rd__go_i$21 \cu_rd__go_i$1
+    connect \src1_i$22 \src1_i$6
+    connect \cu_rd__rel_o$23 \cu_rd__rel_o$31
+    connect \cu_rd__go_i$24 \cu_rd__go_i$23
+    connect \src1_i$25 \src1_i$28
+    connect \cu_rd__rel_o$26 \cu_rd__rel_o$42
+    connect \cu_rd__go_i$27 \cu_rd__go_i$34
+    connect \src1_i$28 \src1_i$39
+    connect \cu_rd__rel_o$29 \cu_rd__rel_o$53
+    connect \cu_rd__go_i$30 \cu_rd__go_i$45
+    connect \src1_i$31 \src1_i$50
+    connect \cu_rd__rel_o$32 \cu_rd__rel_o$64
+    connect \cu_rd__go_i$33 \cu_rd__go_i$56
+    connect \src1_i$34 \src1_i$61
+    connect \cu_rd__rel_o$35 \cu_rd__rel_o$75
+    connect \cu_rd__go_i$36 \cu_rd__go_i$67
+    connect \src1_i$37 \src1_i$72
+    connect \cu_rd__rel_o$38 \cu_rd__rel_o$86
+    connect \cu_rd__go_i$39 \cu_rd__go_i$78
+    connect \src1_i$40 \src1_i$83
     connect \reg2 \reg2
     connect \src2_i \src2_i
-    connect \src2_i$91 \src2_i$10
-    connect \src2_i$92 \src2_i$41
-    connect \src2_i$93 \src2_i$64
-    connect \src2_i$94 \src2_i$99
-    connect \src2_i$95 \src2_i$117
-    connect \src2_i$96 \src2_i$133
+    connect \src2_i$41 \src2_i$7
+    connect \src2_i$42 \src2_i$29
+    connect \src2_i$43 \src2_i$40
+    connect \src2_i$44 \src2_i$62
+    connect \src2_i$45 \src2_i$73
+    connect \src2_i$46 \src2_i$84
     connect \reg3 \reg3
     connect \src3_i \src3_i
     connect \cr_in1 \cr_in1
-    connect \rd__rel$97 \rd__rel$27
-    connect \rd__go$98 \rd__go$15
+    connect \cu_rd__rel_o$47 \cu_rd__rel_o$20
+    connect \cu_rd__go_i$48 \cu_rd__go_i$12
     connect \cr_in2 \cr_in2
-    connect \cr_in2$99 \cr_in2$140
+    connect \cr_in2$49 \cr_in2$91
     connect \fast1 \fast1
-    connect \src1_i$100 \src1_i$24
+    connect \src1_i$50 \src1_i$17
     connect \fast2 \fast2
-    connect \src2_i$101 \src2_i$25
+    connect \src2_i$51 \src2_i$18
     connect \spr1 \spr1
-    connect \src2_i$102 \src2_i$79
+    connect \src2_i$52 \src2_i$51
     connect \rego \rego
-    connect \wr__rel \wr__rel
-    connect \wr__go \wr__go
-    connect \wr__rel$103 \wr__rel$13
-    connect \wr__go$104 \wr__go$2
-    connect \wr__rel$105 \wr__rel$44
-    connect \wr__go$106 \wr__go$31
-    connect \wr__rel$107 \wr__rel$67
-    connect \wr__go$108 \wr__go$47
-    connect \wr__rel$109 \wr__rel$82
-    connect \wr__go$110 \wr__go$70
-    connect \wr__rel$111 \wr__rel$102
-    connect \wr__go$112 \wr__go$85
-    connect \wr__rel$113 \wr__rel$120
-    connect \wr__go$114 \wr__go$105
+    connect \cu_wr__rel_o \cu_wr__rel_o
+    connect \cu_wr__go_i \cu_wr__go_i
+    connect \cu_wr__rel_o$53 \cu_wr__rel_o$10
+    connect \cu_wr__go_i$54 \cu_wr__go_i$2
+    connect \cu_wr__rel_o$55 \cu_wr__rel_o$32
+    connect \cu_wr__go_i$56 \cu_wr__go_i$24
+    connect \cu_wr__rel_o$57 \cu_wr__rel_o$43
+    connect \cu_wr__go_i$58 \cu_wr__go_i$35
+    connect \cu_wr__rel_o$59 \cu_wr__rel_o$54
+    connect \cu_wr__go_i$60 \cu_wr__go_i$46
+    connect \cu_wr__rel_o$61 \cu_wr__rel_o$65
+    connect \cu_wr__go_i$62 \cu_wr__go_i$57
+    connect \cu_wr__rel_o$63 \cu_wr__rel_o$76
+    connect \cu_wr__go_i$64 \cu_wr__go_i$68
     connect \o_ok \o_ok
-    connect \wr__rel$115 \wr__rel$136
-    connect \wr__go$116 \wr__go$123
+    connect \cu_wr__rel_o$65 \cu_wr__rel_o$87
+    connect \cu_wr__go_i$66 \cu_wr__go_i$79
     connect \dest1_o \dest1_o
-    connect \dest1_o$117 \dest1_o$14
-    connect \dest1_o$118 \dest1_o$45
-    connect \dest1_o$119 \dest1_o$68
-    connect \dest1_o$120 \dest1_o$83
-    connect \dest1_o$121 \dest1_o$103
-    connect \dest1_o$122 \dest1_o$121
+    connect \dest1_o$67 \dest1_o$11
+    connect \dest1_o$68 \dest1_o$33
+    connect \dest1_o$69 \dest1_o$44
+    connect \dest1_o$70 \dest1_o$55
+    connect \dest1_o$71 \dest1_o$66
+    connect \dest1_o$72 \dest1_o$77
     connect \o \o
-    connect \ea \ea$138
+    connect \ea \ea$89
     connect \ea_ok \ea_ok
-    connect \ea$123 \ea
-    connect \cr_out \cr_out$142
+    connect \ea$73 \ea
+    connect \cr_out \cr_out$93
     connect \fasto1 \fasto1
-    connect \wr__rel$124 \wr__rel$28
-    connect \wr__go$125 \wr__go$16
-    connect \dest1_o$126 \dest1_o$29
+    connect \cu_wr__rel_o$74 \cu_wr__rel_o$21
+    connect \cu_wr__go_i$75 \cu_wr__go_i$13
+    connect \dest1_o$76 \dest1_o$22
     connect \fasto2 \fasto2
     connect \spro \spro
     connect \opcode_in \opcode_in
@@ -160133,11 +160405,11 @@ module \test_issuer
     connect \out_sel \out_sel
     connect \rc_sel \rc_sel
     connect \cr_in \cr_in
-    connect \cr_out$127 \cr_out
+    connect \cr_out$77 \cr_out
     connect \internal_op \internal_op
     connect \function_unit \function_unit
     connect \rego_ok \rego_ok
-    connect \ea_ok$128 \ea_ok$139
+    connect \ea_ok$78 \ea_ok$90
     connect \spro_ok \spro_ok
     connect \fasto1_ok \fasto1_ok
     connect \fasto2_ok \fasto2_ok
@@ -160148,70 +160420,70 @@ module \test_issuer
     connect \cry_out \cry_out
     connect \is_32b \is_32b
     connect \sgn \sgn
-    connect \lk$129 \lk
+    connect \lk$79 \lk
     connect \br \br
     connect \sgn_ext \sgn_ext
     connect \xer_out \xer_out
-    connect \asmcode \asmcode$137
+    connect \asmcode \asmcode$88
     connect \form \form
     connect \rsrv \rsrv
     connect \sgl_pipe \sgl_pipe
-    connect \asmcode$130 \asmcode
-    connect \go_die_i \go_die_i
-    connect \shadown_i \shadown_i
-    connect \go_die_i$131 \go_die_i$5
-    connect \shadown_i$132 \shadown_i$4
-    connect \go_die_i$133 \go_die_i$19
-    connect \shadown_i$134 \shadown_i$18
-    connect \go_die_i$135 \go_die_i$34
-    connect \shadown_i$136 \shadown_i$33
-    connect \go_die_i$137 \go_die_i$50
-    connect \shadown_i$138 \shadown_i$49
-    connect \go_die_i$139 \go_die_i$73
-    connect \shadown_i$140 \shadown_i$72
-    connect \go_die_i$141 \go_die_i$88
-    connect \shadown_i$142 \shadown_i$87
-    connect \go_die_i$143 \go_die_i$108
-    connect \shadown_i$144 \shadown_i$107
-    connect \go_die_i$145 \go_die_i$126
+    connect \asmcode$80 \asmcode
+    connect \cu_go_die_i \cu_go_die_i
+    connect \cu_shadown_i \cu_shadown_i
+    connect \cu_go_die_i$81 \cu_go_die_i$5
+    connect \cu_shadown_i$82 \cu_shadown_i$4
+    connect \cu_go_die_i$83 \cu_go_die_i$16
+    connect \cu_shadown_i$84 \cu_shadown_i$15
+    connect \cu_go_die_i$85 \cu_go_die_i$27
+    connect \cu_shadown_i$86 \cu_shadown_i$26
+    connect \cu_go_die_i$87 \cu_go_die_i$38
+    connect \cu_shadown_i$88 \cu_shadown_i$37
+    connect \cu_go_die_i$89 \cu_go_die_i$49
+    connect \cu_shadown_i$90 \cu_shadown_i$48
+    connect \cu_go_die_i$91 \cu_go_die_i$60
+    connect \cu_shadown_i$92 \cu_shadown_i$59
+    connect \cu_go_die_i$93 \cu_go_die_i$71
+    connect \cu_shadown_i$94 \cu_shadown_i$70
+    connect \cu_go_die_i$95 \cu_go_die_i$82
     connect \load_mem_o \load_mem_o
     connect \stwd_mem_o \stwd_mem_o
-    connect \shadown_i$146 \shadown_i$125
-    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$144
-    connect \ldst_port0_is_st_i \ldst_port0_is_st_i$145
-    connect \ldst_port0_data_len \ldst_port0_data_len$146
-    connect \ldst_port0_addr_i \ldst_port0_addr_i$149
-    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$150
-    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$152
-    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$151
-    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$153
-    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$154
-    connect \ldst_port0_st_data_i \ldst_port0_st_data_i$155
-    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$156
-    connect \ldst_port0_is_ld_i$147 \ldst_port0_is_ld_i
+    connect \cu_shadown_i$96 \cu_shadown_i$81
+    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$95
+    connect \ldst_port0_is_st_i \ldst_port0_is_st_i$96
+    connect \ldst_port0_data_len \ldst_port0_data_len$97
+    connect \ldst_port0_addr_i \ldst_port0_addr_i$100
+    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$101
+    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$103
+    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$102
+    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$104
+    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$105
+    connect \ldst_port0_st_data_i \ldst_port0_st_data_i$106
+    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$107
+    connect \ldst_port0_is_ld_i$97 \ldst_port0_is_ld_i
     connect \ldst_port0_busy_o \ldst_port0_busy_o
-    connect \ldst_port0_is_st_i$148 \ldst_port0_is_st_i
-    connect \ldst_port0_data_len$149 \ldst_port0_data_len
-    connect \ldst_port0_addr_i$150 \ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok$151 \ldst_port0_addr_i_ok
+    connect \ldst_port0_is_st_i$98 \ldst_port0_is_st_i
+    connect \ldst_port0_data_len$99 \ldst_port0_data_len
+    connect \ldst_port0_addr_i$100 \ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok$101 \ldst_port0_addr_i_ok
     connect \x_mask_i \x_mask_i
     connect \x_addr_i \x_addr_i
-    connect \ldst_port0_addr_ok_o$152 \ldst_port0_addr_ok_o
+    connect \ldst_port0_addr_ok_o$102 \ldst_port0_addr_ok_o
     connect \m_ld_data_o \m_ld_data_o
-    connect \ldst_port0_ld_data_o$153 \ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok$154 \ldst_port0_ld_data_o_ok
+    connect \ldst_port0_ld_data_o$103 \ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok$104 \ldst_port0_ld_data_o_ok
     connect \x_busy_o \x_busy_o
-    connect \ldst_port0_st_data_i_ok$155 \ldst_port0_st_data_i_ok
-    connect \ldst_port0_st_data_i$156 \ldst_port0_st_data_i
+    connect \ldst_port0_st_data_i_ok$105 \ldst_port0_st_data_i_ok
+    connect \ldst_port0_st_data_i$106 \ldst_port0_st_data_i
     connect \x_st_data_i \x_st_data_i
-    connect \ldst_port0_addr_exc_o$157 \ldst_port0_addr_exc_o
+    connect \ldst_port0_addr_exc_o$107 \ldst_port0_addr_exc_o
     connect \x_ld_i \x_ld_i
     connect \x_st_i \x_st_i
     connect \m_valid_i \m_valid_i
     connect \x_valid_i \x_valid_i
     connect \ldst_port0_go_die_i \ldst_port0_go_die_i
-    connect \ldst_port0_go_die_i$158 \ldst_port0_go_die_i$148
-    connect \ldst_port0_busy_o$159 \ldst_port0_busy_o$147
+    connect \ldst_port0_go_die_i$108 \ldst_port0_go_die_i$99
+    connect \ldst_port0_busy_o$109 \ldst_port0_busy_o$98
     connect \dbus__cyc \dbus__cyc
     connect \x_stall_i \x_stall_i
     connect \dbus__ack \dbus__ack
@@ -160248,49 +160520,39 @@ module \test_issuer
     connect \f_badaddr_o \f_badaddr_o
     connect \a_busy_o \a_busy_o
   end
-  attribute \src "simple/issuer.py:54"
-  wire width 1 \busy_o$157
   process $group_0
-    assign \busy_o$157 1'0
-    assign \busy_o$157 \core_corebusy_o
+    assign \busy_o 1'0
+    assign \busy_o \core_corebusy_o
     sync init
   end
-  attribute \src "simple/issuer.py:55"
-  wire width 1 \halted_o
   process $group_1
     assign \halted_o 1'0
     assign \halted_o \core_core_terminated_o
     sync init
   end
-  attribute \src "simple/issuer.py:51"
-  wire width 1 \core_start_i
   process $group_2
     assign \core_start_i 1'0
     assign \core_start_i \core_core_start_i
     sync init
   end
-  attribute \src "simple/issuer.py:52"
-  wire width 1 \core_stop_i
   process $group_3
     assign \core_stop_i 1'0
     assign \core_stop_i \core_core_stop_i
     sync init
   end
-  attribute \src "simple/issuer.py:53"
-  wire width 1 \core_bigendian_i
   process $group_4
     assign \core_bigendian_i 1'0
     assign \core_bigendian_i \bigendian
     sync init
   end
   process $group_5
-    assign \ad__go 1'0
-    assign \ad__go \ad__rel
+    assign \ad__go_i 1'0
+    assign \ad__go_i \ad__rel_o
     sync init
   end
   process $group_6
-    assign \st__go 1'0
-    assign \st__go \st__rel
+    assign \st__go_i 1'0
+    assign \st__go_i \st__rel_o
     sync init
   end
   attribute \src "simple/issuer.py:89"
@@ -160305,11 +160567,11 @@ module \test_issuer
   attribute \src "simple/issuer.py:99"
   wire width 64 \nia
   attribute \src "simple/issuer.py:100"
-  wire width 65 $158
+  wire width 65 $108
   attribute \src "simple/issuer.py:100"
-  wire width 65 $159
+  wire width 65 $109
   attribute \src "simple/issuer.py:100"
-  cell $add $160
+  cell $add $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -160317,12 +160579,12 @@ module \test_issuer
     parameter \Y_WIDTH 65
     connect \A \cur_pc
     connect \B 3'100
-    connect \Y $159
+    connect \Y $109
   end
-  connect $158 $159
+  connect $108 $109
   process $group_8
     assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \nia $158 [63:0]
+    assign \nia $108 [63:0]
     sync init
   end
   attribute \src "simple/issuer.py:90"
@@ -160330,33 +160592,33 @@ module \test_issuer
   attribute \src "simple/issuer.py:90"
   wire width 1 \pc_changed$next
   attribute \src "simple/issuer.py:114"
-  wire width 1 $161
+  wire width 1 $111
   attribute \src "simple/issuer.py:114"
-  cell $not $162
+  cell $not $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $161
+    connect \Y $111
   end
   attribute \src "simple/issuer.py:121"
   wire width 2 \fsm_state
   attribute \src "simple/issuer.py:121"
   wire width 2 \fsm_state$next
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  wire width 1 $163
+  wire width 1 $113
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_bool $164
+  cell $reduce_bool $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A \core_fast_nia_wen
-    connect \Y $163
+    connect \Y $113
   end
   process $group_9
     assign \pc_changed$next \pc_changed
     attribute \src "simple/issuer.py:114"
-    switch { $161 }
+    switch { $111 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160368,18 +160630,18 @@ module \test_issuer
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
-                attribute \src "simple/issuer.py:181"
-                switch { $163 }
-                  attribute \src "simple/issuer.py:181"
+                attribute \src "simple/issuer.py:185"
+                switch { $113 }
+                  attribute \src "simple/issuer.py:185"
                   case 1'1
                     assign \pc_changed$next 1'1
                 end
@@ -160399,19 +160661,19 @@ module \test_issuer
   attribute \src "simple/issuer.py:128"
   wire width 64 \pc
   attribute \src "simple/issuer.py:114"
-  wire width 1 $165
+  wire width 1 $115
   attribute \src "simple/issuer.py:114"
-  cell $not $166
+  cell $not $116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $165
+    connect \Y $115
   end
   process $group_10
     assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $165 }
+    switch { $115 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160436,7 +160698,7 @@ module \test_issuer
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160444,19 +160706,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $167
+  wire width 1 $117
   attribute \src "simple/issuer.py:114"
-  cell $not $168
+  cell $not $118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $167
+    connect \Y $117
   end
   process $group_11
     assign \core_cia__ren 8'00000000
     attribute \src "simple/issuer.py:114"
-    switch { $167 }
+    switch { $117 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160480,7 +160742,7 @@ module \test_issuer
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160488,19 +160750,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $169
+  wire width 1 $119
   attribute \src "simple/issuer.py:114"
-  cell $not $170
+  cell $not $120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $169
+    connect \Y $119
   end
   process $group_12
     assign \a_pc_i 48'000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $169 }
+    switch { $119 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160517,7 +160779,7 @@ module \test_issuer
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160525,19 +160787,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $171
+  wire width 1 $121
   attribute \src "simple/issuer.py:114"
-  cell $not $172
+  cell $not $122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $171
+    connect \Y $121
   end
   process $group_13
     assign \a_valid_i 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $171 }
+    switch { $121 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160562,7 +160824,7 @@ module \test_issuer
               attribute \src "simple/issuer.py:151"
               case
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160570,19 +160832,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $173
+  wire width 1 $123
   attribute \src "simple/issuer.py:114"
-  cell $not $174
+  cell $not $124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $173
+    connect \Y $123
   end
   process $group_14
     assign \f_valid_i 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $173 }
+    switch { $123 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160607,7 +160869,7 @@ module \test_issuer
               attribute \src "simple/issuer.py:151"
               case
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160615,19 +160877,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $175
+  wire width 1 $125
   attribute \src "simple/issuer.py:114"
-  cell $not $176
+  cell $not $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $175
+    connect \Y $125
   end
   process $group_15
     assign \cur_pc$next \cur_pc
     attribute \src "simple/issuer.py:114"
-    switch { $175 }
+    switch { $125 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160644,7 +160906,7 @@ module \test_issuer
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160660,29 +160922,29 @@ module \test_issuer
       update \cur_pc \cur_pc$next
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $177
+  wire width 1 $127
   attribute \src "simple/issuer.py:114"
-  cell $not $178
+  cell $not $128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $177
+    connect \Y $127
   end
-  attribute \src "simple/issuer.py:183"
-  wire width 1 $179
-  attribute \src "simple/issuer.py:183"
-  cell $not $180
+  attribute \src "simple/issuer.py:187"
+  wire width 1 $129
+  attribute \src "simple/issuer.py:187"
+  cell $not $130
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $179
+    connect \Y $129
   end
   process $group_16
     assign \fsm_state$next \fsm_state
     attribute \src "simple/issuer.py:114"
-    switch { $177 }
+    switch { $127 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160707,19 +160969,19 @@ module \test_issuer
               case
                 assign \fsm_state$next 2'10
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
                 assign \fsm_state$next 2'00
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
-                attribute \src "simple/issuer.py:183"
-                switch { $179 }
-                  attribute \src "simple/issuer.py:183"
+                attribute \src "simple/issuer.py:187"
+                switch { $129 }
+                  attribute \src "simple/issuer.py:187"
                   case 1'1
                     assign \fsm_state$next 2'00
                 end
@@ -160739,21 +161001,21 @@ module \test_issuer
   attribute \src "simple/issuer.py:88"
   wire width 32 \current_insn
   attribute \src "simple/issuer.py:114"
-  wire width 1 $181
+  wire width 1 $131
   attribute \src "simple/issuer.py:114"
-  cell $not $182
+  cell $not $132
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $181
+    connect \Y $131
   end
-  attribute \src "simple/issuer.py:153"
-  wire width 32 $183
+  attribute \src "simple/issuer.py:157"
+  wire width 32 $133
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  wire width 7 $184
+  wire width 7 $134
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  cell $mul $185
+  cell $mul $135
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -160761,23 +161023,23 @@ module \test_issuer
     parameter \Y_WIDTH 7
     connect \A \cur_pc [2]
     connect \B 6'100000
-    connect \Y $184
+    connect \Y $134
   end
-  attribute \src "simple/issuer.py:153"
-  cell $shift $186
+  attribute \src "simple/issuer.py:157"
+  cell $shift $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 32
     connect \A \f_instr_o
-    connect \B $184
-    connect \Y $183
+    connect \B $134
+    connect \Y $133
   end
   process $group_17
     assign \current_insn 32'00000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $181 }
+    switch { $131 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160794,9 +161056,9 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \current_insn $183
+                assign \current_insn $133
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160804,19 +161066,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $187
+  wire width 1 $137
   attribute \src "simple/issuer.py:114"
-  cell $not $188
+  cell $not $138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $187
+    connect \Y $137
   end
-  attribute \src "simple/issuer.py:176"
-  wire width 1 $189
-  attribute \src "simple/issuer.py:176"
-  cell $ne $190
+  attribute \src "simple/issuer.py:180"
+  wire width 1 $139
+  attribute \src "simple/issuer.py:180"
+  cell $ne $140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -160824,12 +161086,12 @@ module \test_issuer
     parameter \Y_WIDTH 1
     connect \A \insn_type
     connect \B 7'0000001
-    connect \Y $189
+    connect \Y $139
   end
   process $group_18
     assign \core_valid 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $187 }
+    switch { $137 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160848,18 +161110,18 @@ module \test_issuer
               case
                 assign \core_valid 1'1
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
-                attribute \src "simple/issuer.py:176"
-                switch { $189 }
-                  attribute \src "simple/issuer.py:176"
+                attribute \src "simple/issuer.py:180"
+                switch { $139 }
+                  attribute \src "simple/issuer.py:180"
                   case 1'1
                     assign \core_valid 1'1
                 end
@@ -160869,19 +161131,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $191
+  wire width 1 $141
   attribute \src "simple/issuer.py:114"
-  cell $not $192
+  cell $not $142
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $191
+    connect \Y $141
   end
   process $group_19
     assign \core_issue_i 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $191 }
+    switch { $141 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160900,7 +161162,7 @@ module \test_issuer
               case
                 assign \core_issue_i 1'1
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -160908,14 +161170,14 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $193
+  wire width 1 $143
   attribute \src "simple/issuer.py:114"
-  cell $not $194
+  cell $not $144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $193
+    connect \Y $143
   end
   attribute \src "simple/issuer.py:92"
   wire width 32 \ilatch
@@ -160924,7 +161186,7 @@ module \test_issuer
   process $group_20
     assign \raw_opcode_in 32'00000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $193 }
+    switch { $143 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160943,14 +161205,14 @@ module \test_issuer
               case
                 assign \raw_opcode_in \current_insn
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
                 assign \raw_opcode_in \ilatch
             end
@@ -160959,19 +161221,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $195
+  wire width 1 $145
   attribute \src "simple/issuer.py:114"
-  cell $not $196
+  cell $not $146
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $195
+    connect \Y $145
   end
   process $group_21
     assign \ilatch$next \ilatch
     attribute \src "simple/issuer.py:114"
-    switch { $195 }
+    switch { $145 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160990,7 +161252,7 @@ module \test_issuer
               case
                 assign \ilatch$next \current_insn
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -161006,19 +161268,19 @@ module \test_issuer
       update \ilatch \ilatch$next
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $197
+  wire width 1 $147
   attribute \src "simple/issuer.py:114"
-  cell $not $198
+  cell $not $148
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $197
+    connect \Y $147
   end
   process $group_22
     assign \core_msr__ren 8'00000000
     attribute \src "simple/issuer.py:114"
-    switch { $197 }
+    switch { $147 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161037,7 +161299,7 @@ module \test_issuer
               case
                 assign \core_msr__ren 8'00000010
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -161045,21 +161307,21 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:96"
-  wire width 64 \msr$199
+  wire width 64 \msr$149
   attribute \src "simple/issuer.py:114"
-  wire width 1 $200
+  wire width 1 $150
   attribute \src "simple/issuer.py:114"
-  cell $not $201
+  cell $not $151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $200
+    connect \Y $150
   end
   process $group_23
-    assign \msr$199 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \msr$149 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $200 }
+    switch { $150 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161076,9 +161338,9 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \msr$199 \core_msr__data_o
+                assign \msr$149 \core_msr__data_o
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -161086,14 +161348,14 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $202
+  wire width 1 $152
   attribute \src "simple/issuer.py:114"
-  cell $not $203
+  cell $not $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $202
+    connect \Y $152
   end
   attribute \src "simple/issuer.py:95"
   wire width 64 \cur_msr
@@ -161102,7 +161364,7 @@ module \test_issuer
   process $group_24
     assign \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $202 }
+    switch { $152 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161119,16 +161381,16 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \core_msr \msr$199
+                assign \core_msr \msr$149
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
                 assign \core_msr \cur_msr
             end
@@ -161137,19 +161399,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $204
+  wire width 1 $154
   attribute \src "simple/issuer.py:114"
-  cell $not $205
+  cell $not $155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $204
+    connect \Y $154
   end
   process $group_25
     assign \cur_msr$next \cur_msr
     attribute \src "simple/issuer.py:114"
-    switch { $204 }
+    switch { $154 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161166,9 +161428,9 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \cur_msr$next \msr$199
+                assign \cur_msr$next \msr$149
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
         end
@@ -161184,19 +161446,19 @@ module \test_issuer
       update \cur_msr \cur_msr$next
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $206
+  wire width 1 $156
   attribute \src "simple/issuer.py:114"
-  cell $not $207
+  cell $not $157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $206
+    connect \Y $156
   end
   process $group_26
     assign \core_cia 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $206 }
+    switch { $156 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161215,14 +161477,14 @@ module \test_issuer
               case
                 assign \core_cia \cur_pc
             end
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
                 assign \core_cia \cur_pc
             end
@@ -161231,39 +161493,39 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $208
+  wire width 1 $158
   attribute \src "simple/issuer.py:114"
-  cell $not $209
+  cell $not $159
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $208
+    connect \Y $158
   end
-  attribute \src "simple/issuer.py:183"
-  wire width 1 $210
-  attribute \src "simple/issuer.py:183"
-  cell $not $211
+  attribute \src "simple/issuer.py:187"
+  wire width 1 $160
+  attribute \src "simple/issuer.py:187"
+  cell $not $161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $210
+    connect \Y $160
   end
-  attribute \src "simple/issuer.py:187"
-  wire width 1 $212
-  attribute \src "simple/issuer.py:187"
-  cell $not $213
+  attribute \src "simple/issuer.py:191"
+  wire width 1 $162
+  attribute \src "simple/issuer.py:191"
+  cell $not $163
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $212
+    connect \Y $162
   end
   process $group_27
     assign \core_wen 8'00000000
     attribute \src "simple/issuer.py:114"
-    switch { $208 }
+    switch { $158 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161274,22 +161536,22 @@ module \test_issuer
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
-                attribute \src "simple/issuer.py:183"
-                switch { $210 }
-                  attribute \src "simple/issuer.py:183"
+                attribute \src "simple/issuer.py:187"
+                switch { $160 }
+                  attribute \src "simple/issuer.py:187"
                   case 1'1
-                    attribute \src "simple/issuer.py:187"
-                    switch { $212 }
-                      attribute \src "simple/issuer.py:187"
+                    attribute \src "simple/issuer.py:191"
+                    switch { $162 }
+                      attribute \src "simple/issuer.py:191"
                       case 1'1
                         assign \core_wen 8'00000001
                     end
@@ -161300,39 +161562,39 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $214
+  wire width 1 $164
   attribute \src "simple/issuer.py:114"
-  cell $not $215
+  cell $not $165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $214
+    connect \Y $164
   end
-  attribute \src "simple/issuer.py:183"
-  wire width 1 $216
-  attribute \src "simple/issuer.py:183"
-  cell $not $217
+  attribute \src "simple/issuer.py:187"
+  wire width 1 $166
+  attribute \src "simple/issuer.py:187"
+  cell $not $167
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $216
+    connect \Y $166
   end
-  attribute \src "simple/issuer.py:187"
-  wire width 1 $218
-  attribute \src "simple/issuer.py:187"
-  cell $not $219
+  attribute \src "simple/issuer.py:191"
+  wire width 1 $168
+  attribute \src "simple/issuer.py:191"
+  cell $not $169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $218
+    connect \Y $168
   end
   process $group_28
     assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $214 }
+    switch { $164 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161343,22 +161605,22 @@ module \test_issuer
           attribute \src "simple/issuer.py:146"
           attribute \nmigen.decoding "INSN_READ/1"
           case 2'01
-          attribute \src "simple/issuer.py:172"
+          attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
           case 2'10
-            attribute \src "simple/issuer.py:173"
+            attribute \src "simple/issuer.py:177"
             switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:173"
+              attribute \src "simple/issuer.py:177"
               case 1'1
-              attribute \src "simple/issuer.py:175"
+              attribute \src "simple/issuer.py:179"
               case
-                attribute \src "simple/issuer.py:183"
-                switch { $216 }
-                  attribute \src "simple/issuer.py:183"
+                attribute \src "simple/issuer.py:187"
+                switch { $166 }
+                  attribute \src "simple/issuer.py:187"
                   case 1'1
-                    attribute \src "simple/issuer.py:187"
-                    switch { $218 }
-                      attribute \src "simple/issuer.py:187"
+                    attribute \src "simple/issuer.py:191"
+                    switch { $168 }
+                      attribute \src "simple/issuer.py:191"
                       case 1'1
                         assign \core_data_i \nia
                     end