sort out hacking of PowerDecoder to suit extra.csv

diff --git a/src/decoder/power_decoder.py b/src/decoder/power_decoder.py
index 1f77842e1907fa9ca7ef7214207fbbdcdc839529..666188663c9309627c147a028786f94140c47daa 100644 (file)
--- a/src/decoder/power_decoder.py
+++ b/src/decoder/power_decoder.py
@@ -61,7 +61,8 @@ class PowerDecoder(Elaboratable):
     """PowerDecoder - decodes an incoming opcode into the type of operation
     """
 
-    def __init__(self, width, csvname):
+    def __init__(self, width, csvname, opint=True):
+        self.opint = opint # true if the opcode needs to be converted to int
         self.opcodes = get_csv(csvname)
         self.opcode_in = Signal(width, reset_less=True)
 
@@ -73,9 +74,12 @@ class PowerDecoder(Elaboratable):
 
         with m.Switch(self.opcode_in):
             for row in self.opcodes:
-                opcode = int(row['opcode'], 0)
+                opcode = row['opcode']
+                if self.opint:
+                    opcode = int(opcode, 0)
                 if not row['unit']:
                     continue
+                print ("opcode", opcode)
                 with m.Case(opcode):
                     comb += self.op._eq(row)
             with m.Default():

diff --git a/src/decoder/test/test_power_decoder.py b/src/decoder/test/test_power_decoder.py
index 582926856ceefb05d0037d348e7249117a887227..9955b66665e5b28e00aa1394b2d440cb4220f488 100644 (file)
--- a/src/decoder/test/test_power_decoder.py
+++ b/src/decoder/test/test_power_decoder.py
@@ -13,7 +13,7 @@ from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
 
 
 class DecoderTestCase(FHDLTestCase):
-    def run_test(self, width, csvname):
+    def run_test(self, width, csvname, opint=True):
         m = Module()
         comb = m.d.comb
         opcode = Signal(width)
@@ -27,7 +27,7 @@ class DecoderTestCase(FHDLTestCase):
         ldst_len = Signal(LdstLen)
         cry_in = Signal(CryIn)
 
-        m.submodules.dut = dut = PowerDecoder(width, csvname)
+        m.submodules.dut = dut = PowerDecoder(width, csvname, opint)
         comb += [dut.opcode_in.eq(opcode),
                  function_unit.eq(dut.op.function_unit),
                  in1_sel.eq(dut.op.in1_sel),
@@ -45,7 +45,11 @@ class DecoderTestCase(FHDLTestCase):
             for row in dut.opcodes:
                 if not row['unit']:
                     continue
-                yield opcode.eq(int(row['opcode'], 0))
+                op = row['opcode']
+                if not opint: # HACK: convert 001---10 to 0b00100010
+                    op = "0b" + op.replace('-', '0')
+                print ("opint", opint, row['opcode'], op)
+                yield opcode.eq(int(op, 0))
                 yield Delay(1e-6)
                 signals = [(function_unit, Function, 'unit'),
                            (internal_op, InternalOp, 'internal op'),
@@ -73,9 +77,9 @@ class DecoderTestCase(FHDLTestCase):
                 in1_sel, in2_sel]):
             sim.run()
 
-    def generate_ilang(self, width, csvname):
+    def generate_ilang(self, width, csvname, opint=True):
         prefix = os.path.splitext(csvname)[0]
-        dut = PowerDecoder(width, csvname)
+        dut = PowerDecoder(width, csvname, opint)
         vl = rtlil.convert(dut, ports=dut.ports())
         with open("%s_decoder.il" % prefix, "w") as f:
             f.write(vl)
@@ -96,5 +100,9 @@ class DecoderTestCase(FHDLTestCase):
         self.run_test(10, "minor_31.csv")
         self.generate_ilang(10, "minor_31.csv")
 
+    def test_minor_31(self):
+        self.run_test(32, "extra.csv", False)
+        self.generate_ilang(32, "extra.csv", False)
+
 if __name__ == "__main__":
     unittest.main()