reduce args to FPAddStage1

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 55438c2bad49a56f4f3ae718b59699c875639f79..94060c4c350e1d7aba7db45fc77dc5ce25f6023f 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -915,10 +915,10 @@ class FPAddStage1(FPState, FPID):
         self.out_of = Overflow()
         self.norm_stb = Signal()
 
-    def setup(self, m, in_tot, in_z, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_tot, in_z)
+        self.mod.setup(m, i)
 
         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state