mmu unit test working again

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 78969252c70aed940766fe710c6e3d91034a1044..e6345df73f14e8de8d3740bff7c93bea1c4ad8bc 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -165,7 +165,8 @@ class FSMMMUStage(ControlBase):
                         comb += done.eq(1) # FIXME l_out.done
 
                 with m.Case(MicrOp.OP_MFSPR):
-                    comb += Display("MMUTEST: OP_MFSPR: spr=%i",spr);
+                    comb += Display("MMUTEST: OP_MFSPR: spr=%i returns=%i",
+                                    spr,spr1_i);
                     comb += o.data.eq(spr1_i)
                     comb += o.ok.eq(1)
                     comb += done.eq(1)

diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py
index e8f14b25d483fad154cb09df008466b165fbf27d..d377e935d455c1ebf5b77ac6207c2372605e531e 100644 (file)
--- a/src/soc/simple/test/test_issuer_mmu.py
+++ b/src/soc/simple/test/test_issuer_mmu.py
@@ -54,7 +54,7 @@ class MMUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
-    # BROKEN - missing expected Display output
+    # OP_MTSPR: spr=720
     def case_3_mtspr(self):
         lst = ["mtspr 720,1"] # mtspr PRTBL,r1
         initial_regs = [0] * 32
@@ -63,7 +63,7 @@ class MMUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
-    # BROKEN - missing expected Display output
+    # OP_MFSPR: spr=18/19
     def case_4_mfspr(self):
         lst = ["mfspr 1,18", # mtspr r1,DSISR
                "mfspr 2,19"] # mtspr r2,DAR