forgot to add submodules

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 8ddd45eb8bda5eb5a18dd14feeb56fab6124f876..130d49e814d05028f5248206c4e87611e304a35b 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -28,6 +28,10 @@ class FPMUL(FPBase):
         product = Signal(mw)
 
         of = Overflow()
+        m.submodules.of = of
+        m.submodules.a = a
+        m.submodules.b = b
+        m.submodules.z = z
 
         with m.FSM() as fsm:
 
@@ -127,7 +131,7 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, of)
+                self.roundz(m, z, of.roundz)
                 m.next = "corrections"
 
             # ******

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index db95dcccba623d026138f3d998934633aed6a751..db95eb13e2a4ef7ae7199c6a29e05865674fc62a 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -558,10 +558,10 @@ class FPBase:
         with m.Else():
             m.next = next_state
 
-    def roundz(self, m, z, of):
+    def roundz(self, m, z, roundz):
         """ performs rounding on the output.  TODO: different kinds of rounding
         """
-        with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])):
+        with m.If(roundz):
             m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
             with m.If(z.m == z.m1s): # all 1s
                 m.d.sync += z.e.eq(z.e + 1) # exponent rounds up