* XER regfile - XER.so, XER.ca/ca32, XER.ov/ov32
* FAST regfile - PC, MSR, CTR, LR, TAR, SRR1, SRR2
+Note: this should NOT have name conventions hard-coded (dedicated ports per
+regname). However it is convenient for now.
+
Links:
* https://bugs.libre-soc.org/show_bug.cgi?id=345
"""
def __init__(self):
super().__init__(64, 32)
- self.w_ports = [self.write_port("dest1"),
- self.write_port("dest2")] # for now (LD/ST update)
- self.r_ports = [self.read_port("src1"),
- self.read_port("src2"),
- self.read_port("src3")]
+ self.w_ports = {'o': self.write_port("dest1"),
+ 'o1': self.write_port("dest2")} # for now (LD/ST update)
+ self.r_ports = {'ra': self.read_port("src1"),
+ 'rb': self.read_port("src2"),
+ 'rc': self.read_port("src3")}
# Fast SPRs Regfile
SRR1 = 6
def __init__(self):
super().__init__(64, 8)
- self.w_ports = [self.write_port("dest1"),
- self.write_port("dest2"),
- self.write_port("dest3")]
- self.r_ports = [self.read_port("src1"),
- self.read_port("src2"),
- self.read_port("src3")]
+ self.w_ports = {'nia': self.write_port("dest1"),
+ 'msr': self.write_port("dest2"),
+ 'spr1': self.write_port("dest3"),
+ 'spr2': self.write_port("dest3")}
+ self.r_ports = {'cia': self.read_port("src1"),
+ 'msr': self.read_port("src2"),
+ 'spr1': self.read_port("src3"),
+ 'spr2': self.read_port("src3")}
# CR Regfile
"""
def __init__(self):
super().__init__(32, 8)
- self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
- self.write_port("dest1"), # 4-bit wide, unary-indexed
- self.write_port("dest2")] # 4-bit wide, unary-indexed
- self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
- self.read_port("src1"),
- self.read_port("src2"),
- self.read_port("src3")]
+ self.w_ports = {'full_cr': self.full_wr, # 32-bit (masked, 8-en lines)
+ 'cr_a': self.write_port("dest1"), # 4-bit, unary-indexed
+ 'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed
+ self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines)
+ 'cr_a': self.read_port("src1"),
+ 'cr_b': self.read_port("src2"),
+ 'cr_c': self.read_port("src3")}
# XER Regfile
OV=2 # OV and OV32
def __init__(self):
super().__init__(6, 3)
- self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
- self.write_port("dest1"),
- self.write_port("dest2"),
- self.write_port("dest3")]
- self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
- self.read_port("src1"),
- self.read_port("src2"),
- self.read_port("src3")]
+ self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
+ 'xer_so': self.write_port("dest1"),
+ 'xer_ca': self.write_port("dest2"),
+ 'xer_ov': self.write_port("dest3")}
+ self.r_ports = {'full_xer': self.full_rd, # 6-bit (masked, 3-en lines)
+ 'xer_so': self.read_port("src1"),
+ 'xer_ca': self.read_port("src2"),
+ 'xer_ov': self.read_port("src3")}
# SPR Regfile
def __init__(self):
n_sprs = len(SPR)
super().__init__(64, n_sprs)
- self.w_ports = [self.write_port(name="dest")]
- self.r_ports = [self.read_port("src")]
+ self.w_ports = {'spr': self.write_port(name="dest")}
+ self.r_ports = {'spr': self.read_port("src")}
# class containing all regfiles: int, cr, xer, fast, spr
for (regname, fspec) in fuspecs.items():
if not regname.startswith("full"):
res.append((regname, fspec))
- return enumerate(res)
+ return res # enumerate(res)
class NonProductionCore(Elaboratable):
rdpickers[regfile] = {}
# for each named regfile port, connect up all FUs to that port
- for rpidx, (regname, fspec) in sort_fuspecs(fuspecs):
- print ("connect rd", rpidx, regname, fspec)
+ for (regname, fspec) in sort_fuspecs(fuspecs):
+ print ("connect rd", regname, fspec)
+ rpidx = regname
# get the regfile specs for this regfile port
(rf, read, write, wid, fuspec) = fspec
name = "rdflag_%s_%s" % (regfile, regname)
rdflag = Signal(name=name, reset_less=True)
comb += rdflag.eq(rf)
- # "munge" the regfile port index, due to full-port access
- if regfile == 'XER':
- if regname.startswith('full'):
- rpidx == 0 # by convention, first port
- else:
- rpidx += 1 # start indexing port 0 from 1
- if regfile in 'CR':
- if regname.startswith('full'):
- assert rpidx == 0 # by convention, first port
- else:
- assert rpidx >= 1 # start indexing port 0 from 1
-
# select the required read port. these are pre-defined sizes
print (rpidx, regfile, regs.rf.keys())
rport = regs.rf[regfile.lower()].r_ports[rpidx]
# create a priority picker to manage this port
rdpickers[regfile][rpidx] = rdpick = PriorityPicker(len(fuspec))
- setattr(m.submodules, "rdpick_%s_%d" % (regfile, rpidx), rdpick)
+ setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
# connect the regspec "reg select" number to this port
with m.If(rdpick.en_o):
for regfile, spec in byregfiles_wr.items():
fuspecs = byregfiles_wrspec[regfile]
wrpickers[regfile] = {}
- for rpidx, (regname, fspec) in sort_fuspecs(fuspecs):
- print ("connect wr", rpidx, regname, fspec)
+ for (regname, fspec) in sort_fuspecs(fuspecs):
+ print ("connect wr", regname, fspec)
+ rpidx = regname
# get the regfile specs for this regfile port
(rf, read, write, wid, fuspec) = fspec
- # "munge" the regfile port index, due to full-port access
- if regfile == 'XER':
- if regname.startswith('full'):
- rpidx == 0 # by convention, first port
- else:
- rpidx += 1 # start indexing port 0 from 1
- if regfile == 'CR':
- if regname.startswith('full'):
- assert rpidx == 0 # by convention, first port
- else:
- assert rpidx >= 1 # start indexing port 0 from 1
-
# select the required write port. these are pre-defined sizes
print (regfile, regs.rf.keys())
wport = regs.rf[regfile.lower()].w_ports[rpidx]
# create a priority picker to manage this port
wrpickers[regfile][rpidx] = wrpick = PriorityPicker(len(fuspec))
- setattr(m.submodules, "wrpick_%s_%d" % (regfile, rpidx), wrpick)
+ setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
# connect the regspec write "reg select" number to this port
# only if one FU actually requests (and is granted) the port
projects / soc.git / commitdiff