rename spblock_512w64b8w, and vco_test_ana for pll

diff --git a/experiments9/build_full_4ksram.sh b/experiments9/build_full_4ksram.sh
index 829664458a34f30e7aae49409cc099ac412e5e39..5b2498cfa493a41d064b992fa06b703ef05ada7a 100755 (executable)
--- a/experiments9/build_full_4ksram.sh
+++ b/experiments9/build_full_4ksram.sh
@@ -24,7 +24,7 @@ rm *.vst *.ap
 cp non_generated/full_core_4_4ksram_ls180.v ls180.v
 cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
 cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
-cp non_generated/SPBlock*.v* .
+cp non_generated/spblock*.v* .
 touch mem.init
 touch mem_1.init
 touch mem_2.init

diff --git a/experiments9/non_generated/SPBlock_512W64B8W.v b/experiments9/non_generated/SPBlock_512W64B8W.v
deleted file mode 100644 (file)
index ddab968..0000000
--- a/experiments9/non_generated/SPBlock_512W64B8W.v
+++ /dev/null
@@ -1,7 +0,0 @@
-(* blackbox = 1 *)
-module SPBlock_512W64B8W(input [8:0] a,
-                        input [63:0] d,
-                        output [63:0] q,
-                        input [7:0] we,
-                        input clk);
-endmodule // SPBlock_512W64B8W

diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
index b53b5db977011450e54dfeedfa9dde7e2397e5fe..0715492fb506f0a233e2727a240347f512f510ca 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v
+++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
@@ -176489,51 +176489,49 @@ endmodule
 
 (* \nmigen.hierarchy  = "test_issuer.pll" *)
 (* generator = "nMigen" *)
-module pll(\ref , div_out_test, vco_test_ana, clk_sel_i, out);
+module pll(\ref , div_out_test, a0, a1, vco_test_ana, out);
   reg \initial  = 0;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
   wire \$1 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
   wire \$11 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:23" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:22" *)
   wire \$13 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
   wire \$3 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
   wire \$5 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
   wire \$7 ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
   wire \$9 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *)
-  wire a0;
+  input a0;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *)
-  wire a1;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *)
-  output [1:0] clk_sel_i;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *)
+  input a1;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *)
   output div_out_test;
   reg div_out_test;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *)
   output out;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *)
   input \ref ;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *)
   output vco_test_ana;
   reg vco_test_ana;
-  assign \$9  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a1;
-  assign \$11  = \$7  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) \$9 ;
-  assign \$13  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:23" *) \ref ;
-  assign \$1  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a0;
-  assign \$3  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a1;
-  assign \$5  = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) \$3 ;
-  assign \$7  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a0;
+  assign \$9  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a1;
+  assign \$11  = \$7  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) \$9 ;
+  assign \$13  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:22" *) \ref ;
+  assign \$1  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a0;
+  assign \$3  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a1;
+  assign \$5  = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) \$3 ;
+  assign \$7  = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *) a0;
   always @* begin
     if (\initial ) begin end
     vco_test_ana = 1'h0;
-    (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+    (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
     casez (\$5 )
-      /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" */
+      /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" */
       1'h1:
           vco_test_ana = \ref ;
     endcase
@@ -176541,16 +176539,13 @@ module pll(\ref , div_out_test, vco_test_ana, clk_sel_i, out);
   always @* begin
     if (\initial ) begin end
     div_out_test = 1'h0;
-    (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+    (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" *)
     casez (\$11 )
-      /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" */
+      /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" */
       1'h1:
           div_out_test = \$13 ;
     endcase
   end
-  assign a0 = 1'h0;
-  assign a1 = 1'h0;
-  assign clk_sel_i = 2'h0;
   assign out = \ref ;
 endmodule
 
@@ -193406,7 +193401,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac
   assign \$1  = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb;
   always @(posedge clk)
     sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
-  SPBlock_512W64B8W \U$$0  (
+  spblock_512w64b8w \U$$0  (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193550,7 +193545,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac
   assign \$1  = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb;
   always @(posedge clk)
     sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
-  SPBlock_512W64B8W \U$$0  (
+  spblock_512w64b8w \U$$0  (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193694,7 +193689,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac
   assign \$1  = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb;
   always @(posedge clk)
     sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
-  SPBlock_512W64B8W \U$$0  (
+  spblock_512w64b8w \U$$0  (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193838,7 +193833,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac
   assign \$1  = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb;
   always @(posedge clk)
     sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
-  SPBlock_512W64B8W \U$$0  (
+  spblock_512w64b8w \U$$0  (
     .a(a),
     .clk(clk),
     .d(d),
@@ -195047,6 +195042,8 @@ endmodule
 (* top =  1  *)
 (* generator = "nMigen" *)
 module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, vco_test_ana, pc_i);
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *)
+  wire [1:0] \$1 ;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
   input TAP_bus__tck;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
@@ -195059,8 +195056,8 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t
   output busy_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
   input clk;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *)
-  output [1:0] clk_sel_i;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *)
+  input clk_sel_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *)
   input core_bigendian_i;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
@@ -195409,15 +195406,19 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t
   output [63:0] pc_o;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *)
   output pll_18_o;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *)
-  wire pll_div_out_test;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *)
+  wire pll_a0;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *)
+  wire pll_a1;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *)
+  wire pll_div_out_test;
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *)
   wire pll_out;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *)
   wire pll_ref;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
   wire pllclk_clk;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *)
   wire pllclk_rst;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
   input rst;
@@ -195779,10 +195780,12 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t
   input sram4k_3_wb__we;
   (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
   wire ti_coresync_clk;
-  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *)
+  (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *)
   output vco_test_ana;
+  assign \$1  = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) clk_sel_i;
   pll pll (
-    .clk_sel_i(clk_sel_i),
+    .a0(pll_a0),
+    .a1(pll_a1),
     .div_out_test(pll_div_out_test),
     .out(pll_out),
     .\ref (pll_ref),
@@ -196136,6 +196139,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t
   );
   assign ti_coresync_clk = pll_out;
   assign pllclk_rst = rst;
+  assign { pll_a1, pll_a0 } = \$1 ;
   assign pll_18_o = pll_div_out_test;
   assign pll_ref = clk;
   assign pllclk_clk = pll_out;

diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v
index c795a514da0f749aa11aa7204d60d7af87902a82..200764c9b8ca0428a649b842f09219ab756f5396 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v
+++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v
@@ -1,10 +1,11 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-18 21:13:03
+// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-18 21:41:43
 //--------------------------------------------------------------------------------
-module ls180sram4k(
-       input wire eint_0,
-       input wire eint_1,
-       input wire eint_2,
+module ls180(
+       output wire i2c_scl,
+       input wire i2c_sda_i,
+       output wire i2c_sda_o,
+       output wire i2c_sda_oe,
        output wire [12:0] sdram_a,
        input wire [15:0] sdram_dq_i,
        output wire [15:0] sdram_dq_o,
@@ -17,19 +18,18 @@ module ls180sram4k(
        output wire [1:0] sdram_ba,
        output wire [1:0] sdram_dm,
        output wire sdram_clock,
-       input wire uart_tx,
-       input wire uart_rx,
        input wire [15:0] gpio_i,
        output wire [15:0] gpio_o,
        output wire [15:0] gpio_oe,
-       output wire i2c_scl,
-       input wire i2c_sda_i,
-       output wire i2c_sda_o,
-       output wire i2c_sda_oe,
        output wire spimaster_clk,
        output wire spimaster_mosi,
        output wire spimaster_cs_n,
        input wire spimaster_miso,
+       input wire uart_tx,
+       input wire uart_rx,
+       input wire eint_0,
+       input wire eint_1,
+       input wire eint_2,
        input wire sys_clk,
        input wire sys_rst,
        input wire [1:0] sys_clksel_i,
@@ -159,9 +159,10 @@ wire [63:0] libresocsim_libresoc3;
 wire libresocsim_libresoc_pll_18_o;
 wire [1:0] libresocsim_libresoc_clk_sel;
 wire libresocsim_libresoc_pll_ana_o;
-wire libresocsim_libresoc_constraintmanager_eint_0;
-wire libresocsim_libresoc_constraintmanager_eint_1;
-wire libresocsim_libresoc_constraintmanager_eint_2;
+wire libresocsim_libresoc_constraintmanager_i2c_scl;
+wire libresocsim_libresoc_constraintmanager_i2c_sda_i;
+wire libresocsim_libresoc_constraintmanager_i2c_sda_o;
+wire libresocsim_libresoc_constraintmanager_i2c_sda_oe;
 reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0;
 wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i;
 reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0;
@@ -174,19 +175,18 @@ reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0;
 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0;
 reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0;
 reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0;
-reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
-reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
 wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i;
 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0;
 reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0;
-wire libresocsim_libresoc_constraintmanager_i2c_scl;
-wire libresocsim_libresoc_constraintmanager_i2c_sda_i;
-wire libresocsim_libresoc_constraintmanager_i2c_sda_o;
-wire libresocsim_libresoc_constraintmanager_i2c_sda_oe;
 reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0;
 reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0;
 reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0;
 wire libresocsim_libresoc_constraintmanager_spimaster_miso;
+reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1;
+reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0;
+wire libresocsim_libresoc_constraintmanager_eint_0;
+wire libresocsim_libresoc_constraintmanager_eint_1;
+wire libresocsim_libresoc_constraintmanager_eint_2;
 reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0;
 reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0;
 wire [31:0] libresocsim_interface0_converted_interface_dat_r;
@@ -6173,7 +6173,7 @@ test_issuer test_issuer(
        .sram4k_3_wb__ack(libresocsim_libresoc_interface3_ack),
        .sram4k_3_wb__dat_r(libresocsim_libresoc_interface3_dat_r),
        .sram4k_3_wb__err(libresocsim_libresoc_interface3_err),
-       .vco_test_ana_o(libresocsim_libresoc_pll_ana_o)
+       .vco_test_ana(libresocsim_libresoc_pll_ana_o)
 );
 
 endmodule

diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.v b/experiments9/non_generated/full_core_4_4ksram_ls180.v
index 6b3619a64b8ac05fcb198d1a34cee598b6ac465a..17b5558ce04982506119b4b6739f27ac832a0bde 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_ls180.v
+++ b/experiments9/non_generated/full_core_4_4ksram_ls180.v
@@ -1,3 +1,3 @@
 `include "litex_ls180.v"
-`include "SPBlock_512W64B8W.v"
+`include "spblock_512w64b8w.v"
 `include "libresoc.v"

diff --git a/experiments9/non_generated/pll.v b/experiments9/non_generated/pll.v
new file mode 100644 (file)
index 0000000..e178f5b
--- /dev/null
+++ b/experiments9/non_generated/pll.v
@@ -0,0 +1,10 @@
+(* blackbox = 1 *)
+module pll(ref , div_out_test, a0, a1, vco_test_ana, out);
+  input a0;
+  input a1;
+  output div_out_test;
+  output out;
+  input ref ;
+  output vco_test_ana;
+endmodule
+

diff --git a/experiments9/non_generated/spblock_512w64b8w.v b/experiments9/non_generated/spblock_512w64b8w.v
new file mode 100644 (file)
index 0000000..cd6b9c8
--- /dev/null
+++ b/experiments9/non_generated/spblock_512w64b8w.v
@@ -0,0 +1,7 @@
+(* blackbox = 1 *)
+module spblock_512w64b8w(input [8:0] a,
+                        input [63:0] d,
+                        output [63:0] q,
+                        input [7:0] we,
+                        input clk);
+endmodule // SPBlock_512W64B8W