def __init__(self, name=None):
layout = (('insn_type', InternalOp),
('fn_unit', Function),
+ ('insn', 32),
('read_cr_whole', 1),
('write_cr_whole', 1),
)
# grrr. Record does not have kwargs
self.insn_type.reset_less = True
+ self.insn.reset_less = True
self.fn_unit.reset_less = True
self.read_cr_whole.reset_less = True
self.write_cr_whole.reset_less = True
def ports(self):
return [self.insn_type,
+ self.insn,
self.fn_unit,
self.read_cr_whole,
self.write_cr_whole,
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
-from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
+from soc.fu.cr.cr_input_record import CompCROpSubset
from soc.decoder.power_decoder2 import Data
self.full_cr.eq(i.full_cr),
self.cr_o.eq(i.cr_o)]
-# TODO: replace CompALUOpSubset with CompCROpSubset
class CRPipeSpec(CommonPipeSpec):
regspec = (CRInputData.regspec, CROutputData.regspec)
- opsubsetkls = CompALUOpSubset
+ opsubsetkls = CompCROpSubset