add blinky lights so we know FPGA is alive

diff --git a/examples/soc.py b/examples/soc.py
index 8e489e19206589e3839e96e8fa3a3edc07721189..8b856481fdb0361e61b6315150e15ef31996405f 100644 (file)
--- a/examples/soc.py
+++ b/examples/soc.py
@@ -26,6 +26,7 @@ from gram.modules import MT41K256M16
 from gram.frontend.wishbone import gramWishbone
 
 from nmigen_boards.versa_ecp5 import VersaECP5Platform
+from nmigen_boards.test.blinky import Blinky
 from uartbridge import UARTBridge
 from crg import ECPIX5CRG
 
@@ -124,6 +125,9 @@ class DDR3SoC(SoC, Elaboratable):
         m.submodules.dramcore = self.dramcore
         m.submodules.drambone = self.drambone
 
+        # add blinky lights so we know FPGA is alive
+        m.submodules.blinky = Blinky()
+
         # connect the arbiter (of wishbone masters)
         # to the decoder (addressing wishbone slaves)
         comb += self._arbiter.bus.connect(self._decoder.bus)