whoops forgot that the mul pipeline is actually a pipeline (3 stage, first one)

diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py
index e8e099bb10691be2a9a51e3ecb275dd51d2e1821..bdee2ec5cce0cb1fbc6ddfbdbcace73f75f357fd 100644 (file)
--- a/src/soc/fu/mul/post_stage.py
+++ b/src/soc/fu/mul/post_stage.py
@@ -36,6 +36,7 @@ class MulMainStage3(PipeModBase):
         comb += mul_o.eq(Mux(self.i.neg_res, -o_i, o_i))
         comb += o.ok.eq(1)
 
+        # OP_MUL_nnn - select hi32/hi64/lo64 from result
         with m.Switch(op.insn_type):
             # hi-32 replicated twice
             with m.Case(InternalOp.OP_MUL_H32):

diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py
index ef1f100dee80b657ba8879646040b0a771c81b8a..cd93e1290117dc388a75b958f1f7e04ebdff68e4 100644 (file)
--- a/src/soc/fu/mul/test/test_pipe_caller.py
+++ b/src/soc/fu/mul/test/test_pipe_caller.py
@@ -40,6 +40,7 @@ def set_alu_inputs(alu, dec2, sim):
     # and place it into data_i.b
 
     inp = yield from get_cu_inputs(dec2, sim)
+    print ("set alu inputs", inp)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
 
@@ -77,7 +78,7 @@ class MulTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def test_0_mullw(self):
+    def tst_0_mullw(self):
         lst = [f"mullw 3, 1, 2"]
         initial_regs = [0] * 32
         #initial_regs[1] = 0xffffffffffffffff
@@ -93,14 +94,22 @@ class MulTestCase(FHDLTestCase):
         initial_regs[2] = 0xfdeba998
         self.run_tst_program(Program(lst), initial_regs)
 
-    def tst_2_mullwo_(self):
-        lst = [f"mullwo. 3, 1, 2"]
+    def tst_2_mullwo(self):
+        lst = [f"mullwo 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffffa988 # -5678
         initial_regs[2] = 0xffffffffffffedcc # -1234
         self.run_tst_program(Program(lst), initial_regs)
 
-    def test_3_mullw(self):
+    def tst_3_mullw(self):
+        lst = ["mullw 3, 1, 2",
+               "mullw 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x6
+        initial_regs[2] = 0xe
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_4_mullw_rand(self):
         for i in range(40):
             lst = ["mullw 3, 1, 2"]
             initial_regs = [0] * 32
@@ -108,6 +117,14 @@ class MulTestCase(FHDLTestCase):
             initial_regs[2] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_4_mullw_nonrand(self):
+        for i in range(40):
+            lst = ["mullw 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = i+1
+            initial_regs[2] = i+20
+            self.run_tst_program(Program(lst), initial_regs)
+
     def tst_rand_mullw(self):
         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
         for i in range(40):
@@ -144,7 +161,6 @@ class TestRunner(FHDLTestCase):
         m.submodules.alu = alu = MulBasePipe(pspec)
 
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
-        comb += alu.p.valid_i.eq(1)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
@@ -159,6 +175,7 @@ class TestRunner(FHDLTestCase):
                                 test.mem, test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
+                yield Settle()
 
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
@@ -179,11 +196,17 @@ class TestRunner(FHDLTestCase):
                     fn_unit = yield pdecode2.e.do.fn_unit
                     self.assertEqual(fn_unit, Function.MUL.value)
                     yield from set_alu_inputs(alu, pdecode2, sim)
+
+                    # set valid for one cycle, propagate through pipeline...
+                    yield alu.p.valid_i.eq(1)
                     yield
+                    yield alu.p.valid_i.eq(0)
+
                     opname = code.split(' ')[0]
                     yield from sim.call(opname)
                     index = sim.pc.CIA.value//4
 
+                    # ...wait for valid to pop out the end
                     vld = yield alu.n.valid_o
                     while not vld:
                         yield
@@ -191,6 +214,7 @@ class TestRunner(FHDLTestCase):
                     yield
 
                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
+                    yield Settle()
 
         sim.add_sync_process(process)
         with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",

diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py
index 6d3b5aa533082ab4636d91e6489b6a2ec3d367d8..4201d4008eb4993e9a11ad9d0a79e9ddd9ccafba 100644 (file)
--- a/src/soc/fu/pipe_data.py
+++ b/src/soc/fu/pipe_data.py
@@ -27,6 +27,7 @@ class IntegerData:
     def eq(self, i):
         eqs = [self.ctx.eq(i.ctx)]
         for j in range(len(self.data)):
+            assert type(self.data[j]) == type(i.data[j])
             eqs.append(self.data[j].eq(i.data[j]))
         return eqs
 

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index b07b3885899e82fabc1c275df511fab8d2d6f036..902d9747a96871e89923e053645775dd694a291e 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -376,7 +376,7 @@ class ALUHelpers:
         if 'o' in res:
             expected = sim_o['o']
             alu_out = res['o']
-            print(f"expected {expected:x}, actual: {alu_out:x}")
+            print(f"expected int sim {expected:x}, actual: {alu_out:x}")
             dut.assertEqual(expected, alu_out, msg)
 
     def check_msr(dut, res, sim_o, msg):

diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index 7c24fa669db8155911dd274ccbb1e9be1e62e193..a3db0f133d648095aec6cdd4700e623f89b521ac 100644 (file)
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -30,7 +30,7 @@ class MulTestCases(FHDLTestCase):
                "mullw 3, 1, 2"]
         self.run_tst_program(Program(lst), [3])
 
-    def test_mullwo_(self):
+    def test_mullwo(self):
         lst = ["addi 1, 0, 0x5678",
                "neg 1, 1",
                "addi 2, 0, 0x1234",