swap encode responses, 3210 not 0123 for left mode

diff --git a/src/soc/countzero/countzero.py b/src/soc/countzero/countzero.py
index 7826d947ed1f18a5d93e6ae2ee6653f30d5eae47..bd61f571d43ee6420442f712af9b8a71ae589160 100644 (file)
--- a/src/soc/countzero/countzero.py
+++ b/src/soc/countzero/countzero.py
@@ -53,14 +53,14 @@ class ZeroCounter(Elaboratable):
                 with m.Else():
                     m.d.comb += ret.eq(3)
             with m.Else():
-                with m.If(v[0]):
-                    m.d.comb += ret.eq(0)
-                with m.Elif(v[1]):
-                    m.d.comb += ret.eq(1)
+                with m.If(v[3]):
+                    m.d.comb += ret.eq(3)
                 with m.Elif(v[2]):
                     m.d.comb += ret.eq(2)
+                with m.Elif(v[1]):
+                    m.d.comb += ret.eq(1)
                 with m.Else():
-                    m.d.comb += ret.eq(3)
+                    m.d.comb += ret.eq(0)
             return ret
 
         r = IntermediateResult()

diff --git a/src/soc/countzero/test/test_countzero.py b/src/soc/countzero/test/test_countzero.py
index e4ca3519ff88cf8b19f5308faeb4d02f10597aa2..8bb3fe153fad9c7b42563cbe7e871e633fc6a1a0 100644 (file)
--- a/src/soc/countzero/test/test_countzero.py
+++ b/src/soc/countzero/test/test_countzero.py
@@ -65,7 +65,7 @@ class ZeroCounterTestCase(FHDLTestCase):
             yield dut.count_right_i.eq(0)
             yield Delay(1e-6)
             result = yield dut.result_o
-            assert result == 8, "result %d" % result
+            assert result == 14, "result %d" % result
 
             yield dut.count_right_i.eq(1)
             yield Delay(1e-6)
@@ -77,6 +77,11 @@ class ZeroCounterTestCase(FHDLTestCase):
             result = yield dut.result_o
             assert result == 23, "result %d" % result
 
+            yield dut.count_right_i.eq(0)
+            yield Delay(1e-6)
+            result = yield dut.result_o
+            assert result == 14, "result %d" % result
+
 
         sim.add_process(process)  # or sim.add_sync_process(process), see below