yield from alusim.check(dut)
- for i in range(1):
+ for i in range(20):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
while True:
break
if dest not in [src1, src2]:
break
- src1 = 2
- src2 = 2
- dest = 2
+ #src1 = 2
+ #src2 = 3
+ #dest = 2
op = randint(0, 1)
- op = 0
+ #op = 1
print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
yield from int_instr(dut, alusim, op, src1, src2, dest)
yield from print_reg(dut, [3,4,5])
yield dut.int_insn_i[i].eq(0)
yield
yield
- yield
yield
# readable output signal
g_rd = Signal(self.reg_width, reset_less=True)
- m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
+ m.d.comb += g_rd.eq((~self.g_wr_pend_i) & self.rd_pend_o)
m.d.comb += self.readable_o.eq(g_rd.bool())
# writable output signal