add an if for OP_MTMSR and some comments

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index d165aefbe7078f171bd300eb839b37f81572b65d..7d585a2de17701baca581de57bf33183ae451def 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -132,7 +132,12 @@ class TrapMainStage(PipeModBase):
                         ctrl_tmp.msr(MSR_IR) <= '1';
                         ctrl_tmp.msr(MSR_DR) <= '1';
                 """
-                comb += self.o.msr.data.eq(a)
+                for stt, end in [(1,12), (13, 60), (61, 64)]:
+                    comb += self.o.msr.data[stt:end].eq(a[stt:end])
+                with m.If(a[MSR_PR]):
+                        self.o.msr[MSR_EE].eq(1)
+                        self.o.msr[MSR_IR].eq(1)
+                        self.o.msr[MSR_DR].eq(1)
                 comb += self.o.msr.ok.eq(1)
 
             # move from SPR
@@ -165,7 +170,7 @@ class TrapMainStage(PipeModBase):
                 """
                 comb += self.o.msr.data[:16].eq(b[:16])
                 comb += self.o.msr.data[22:27].eq(b[22:27])
-                comb += self.o.msr.data[31:]
+                comb += self.o.msr.data[31:] # <- oops missed the eq here
                 comb += self.o.msr.ok.eq(1)
                 comb += self.o.msr.data.eq(b)
                 comb += self.o.msr.ok.eq(1)
@@ -178,8 +183,9 @@ class TrapMainStage(PipeModBase):
                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
                 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
                 """
-                comb += self.o.nia.eq(0xC00)
+                comb += self.o.nia.eq(0xC00) # trap address
                 comb += self.o.nia.ok.eq(1)
+                # TODO: srr1 (see 2nd line of vhdl above. remember set ok=1 too)
 
             #with m.Case(InternalOp.OP_ADDPCIS):
             #    pass