This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.
UINT_64 dccRamBaseAlign; ///< Base alignment of dcc key
UINT_64 dccRamSize; ///< Size of dcc key
UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
- BOOL_32 subLvlCompressible; ///< whether sub resource is compressiable
+ BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
+ BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
} ADDR_COMPUTE_DCCINFO_OUTPUT;
/**
HwlGetPipes(&pIn->tileInfo) *
m_pipeInterleaveBytes;
pOut->dccFastClearSize = dccFastClearSize;
+ pOut->dccRamSizeAligned = TRUE;
ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign));
{
pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
}
+ if ((pOut->dccRamSize & (dccRamSizeAlign - 1)) != 0)
+ {
+ pOut->dccRamSizeAligned = FALSE;
+ }
pOut->dccRamSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
pOut->subLvlCompressible = FALSE;
}