cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
cp non_generated/spblock*.v .
+cp non_generated/spblock*.vbe .
cp non_generated/pll.v .
touch mem.init
touch mem_1.init
cp non_generated/litex_ls180.v litex_ls180.v
cp non_generated/libresoc.v libresoc.v
cp non_generated/spblock*.v .
+cp non_generated/spblock*.vbe .
cp non_generated/pll.v .
touch mem.init
touch mem_1.init
+++ /dev/null
-
--- Phony VHDL interface for SRAM block.
-
-entity SPBlock_512W64B8W is
- port ( clk : in bit
- ; we : in bit_vector( 7 downto 0)
- ; a : in bit_vector( 8 downto 0)
- ; d : in bit_vector(63 downto 0)
- ; q : out bit_vector(63 downto 0)
- ; vdd : in bit
- ; vss : in bit
- );
-end SPBlock_512W64B8W;
-
-architecture behavioral of SPBlock_512W64B8W is
-
-begin
-
-end behavioral;
--- /dev/null
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w is
+ port ( clk : in bit
+ ; we : in bit_vector( 7 downto 0)
+ ; a : in bit_vector( 8 downto 0)
+ ; d : in bit_vector(63 downto 0)
+ ; q : out bit_vector(63 downto 0)
+ ; vdd : in bit
+ ; vss : in bit
+ );
+end spblock512w64b8w;
+
+architecture behavioral of spblock512w64b8w is
+
+begin
+
+end behavioral;
--- /dev/null
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_0 is
+ port ( clk : in bit
+ ; we : in bit_vector( 7 downto 0)
+ ; a : in bit_vector( 8 downto 0)
+ ; d : in bit_vector(63 downto 0)
+ ; q : out bit_vector(63 downto 0)
+ ; vdd : in bit
+ ; vss : in bit
+ );
+end spblock512w64b8w_0;
+
+architecture behavioral of spblock512w64b8w_0 is
+
+begin
+
+end behavioral;
--- /dev/null
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b81_1 is
+ port ( clk : in bit
+ ; we : in bit_vector( 7 downto 0)
+ ; a : in bit_vector( 8 downto 0)
+ ; d : in bit_vector(63 downto 0)
+ ; q : out bit_vector(63 downto 0)
+ ; vdd : in bit
+ ; vss : in bit
+ );
+end spblock512w64b81_1;
+
+architecture behavioral of spblock512w64b81_1 is
+
+begin
+
+end behavioral;
--- /dev/null
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_2 is
+ port ( clk : in bit
+ ; we : in bit_vector( 7 downto 0)
+ ; a : in bit_vector( 8 downto 0)
+ ; d : in bit_vector(63 downto 0)
+ ; q : out bit_vector(63 downto 0)
+ ; vdd : in bit
+ ; vss : in bit
+ );
+end spblock512w64b8w_2;
+
+architecture behavioral of spblock512w64b8w_2 is
+
+begin
+
+end behavioral;
--- /dev/null
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_3 is
+ port ( clk : in bit
+ ; we : in bit_vector( 7 downto 0)
+ ; a : in bit_vector( 8 downto 0)
+ ; d : in bit_vector(63 downto 0)
+ ; q : out bit_vector(63 downto 0)
+ ; vdd : in bit
+ ; vss : in bit
+ );
+end spblock512w64b8w_3;
+
+architecture behavioral of spblock512w64b8w_3 is
+
+begin
+
+end behavioral;