add vbe spblock models to non_generated and build scripts
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 28 Apr 2021 10:15:41 +0000 (10:15 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 28 Apr 2021 10:15:41 +0000 (10:15 +0000)
experiments9/build_full_4ksram.sh
experiments9/freepdk_c4m45/build_full.sh
experiments9/non_generated/SPBlock_512W64B8W.vbe [deleted file]
experiments9/non_generated/spblock512w64b8w.vbe [new file with mode: 0644]
experiments9/non_generated/spblock512w64b8w_0.vbe [new file with mode: 0644]
experiments9/non_generated/spblock512w64b8w_1.vbe [new file with mode: 0644]
experiments9/non_generated/spblock512w64b8w_2.vbe [new file with mode: 0644]
experiments9/non_generated/spblock512w64b8w_3.vbe [new file with mode: 0644]

index ef2257d26d77c2f1106bd52befafe25d22de06aa..050c7190f6ee0dc77b2b81eb9779772b9ffb85f1 100755 (executable)
@@ -25,6 +25,7 @@ cp non_generated/full_core_4_4ksram_ls180.v ls180.v
 cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
 cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
 cp non_generated/spblock*.v .
+cp non_generated/spblock*.vbe .
 cp non_generated/pll.v .
 touch mem.init
 touch mem_1.init
index 4b44222e9ee1ebb3936dcd0796d9ffdd9a137e53..ffc8e3e7190333b1a0d061079e4b3f7185b46338 100755 (executable)
@@ -27,6 +27,7 @@ cp non_generated/ls180.v ls180.v
 cp non_generated/litex_ls180.v litex_ls180.v
 cp non_generated/libresoc.v libresoc.v
 cp non_generated/spblock*.v .
+cp non_generated/spblock*.vbe .
 cp non_generated/pll.v .
 touch mem.init
 touch mem_1.init
diff --git a/experiments9/non_generated/SPBlock_512W64B8W.vbe b/experiments9/non_generated/SPBlock_512W64B8W.vbe
deleted file mode 100644 (file)
index c752468..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-
--- Phony VHDL interface for SRAM block.
-
-entity SPBlock_512W64B8W is
-   port ( clk     : in  bit
-        ; we      : in  bit_vector( 7 downto 0)
-        ; a       : in  bit_vector( 8 downto 0)
-        ; d       : in  bit_vector(63 downto 0)
-        ; q       : out bit_vector(63 downto 0)
-        ; vdd     : in  bit
-        ; vss     : in  bit
-        );
-end SPBlock_512W64B8W;
-
-architecture behavioral of SPBlock_512W64B8W is
-
-begin
-
-end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w.vbe b/experiments9/non_generated/spblock512w64b8w.vbe
new file mode 100644 (file)
index 0000000..de2d3df
--- /dev/null
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w;
+
+architecture behavioral of spblock512w64b8w is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_0.vbe b/experiments9/non_generated/spblock512w64b8w_0.vbe
new file mode 100644 (file)
index 0000000..a2ba9c5
--- /dev/null
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_0 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w_0;
+
+architecture behavioral of spblock512w64b8w_0 is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_1.vbe b/experiments9/non_generated/spblock512w64b8w_1.vbe
new file mode 100644 (file)
index 0000000..40a2f77
--- /dev/null
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b81_1 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b81_1;
+
+architecture behavioral of spblock512w64b81_1 is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_2.vbe b/experiments9/non_generated/spblock512w64b8w_2.vbe
new file mode 100644 (file)
index 0000000..d14ef7f
--- /dev/null
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_2 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w_2;
+
+architecture behavioral of spblock512w64b8w_2 is
+
+begin
+
+end behavioral;
diff --git a/experiments9/non_generated/spblock512w64b8w_3.vbe b/experiments9/non_generated/spblock512w64b8w_3.vbe
new file mode 100644 (file)
index 0000000..164765c
--- /dev/null
@@ -0,0 +1,18 @@
+-- Phony VHDL interface for SRAM block.
+
+entity spblock512w64b8w_3 is
+   port ( clk     : in  bit
+        ; we      : in  bit_vector( 7 downto 0)
+        ; a       : in  bit_vector( 8 downto 0)
+        ; d       : in  bit_vector(63 downto 0)
+        ; q       : out bit_vector(63 downto 0)
+        ; vdd     : in  bit
+        ; vss     : in  bit
+        );
+end spblock512w64b8w_3;
+
+architecture behavioral of spblock512w64b8w_3 is
+
+begin
+
+end behavioral;