comment why litex sim mem map is altered

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 68be7702ebd72ef6d17e7796e8682848bc658578..9d407eecf4f01db3f2f23c00df483fec455c8b1b 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -58,7 +58,11 @@ class LibreSoCSim(SoCSDRAM):
             #    ram_fname:       "0x00000000",
             #    }, "little")
             ram_init = get_mem_data(ram_fname, "little")
+
+            # remap the main RAM to reset-start-address
             self.mem_map["main_ram"] = 0x00000000
+
+            # without sram nothing works, therefore move it to higher up
             self.mem_map["sram"] = 0x90000000