missed setting r1.store_way and r1.store_row in STORE_WAIT_ACK state

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 374297ba78d2c33ec376c3298780f65eb862de52..612e6c21ca637631812c6994b2c200d5751eb7cb 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1606,10 +1606,12 @@ class DCache(Elaboratable):
                         sync += r1.wb.sel.eq(req.byte_sel)
 
                     with m.If((adjust_acks < 7) & req.same_tag &
-                                ((req.op == Op.OP_STORE_MISS)
-                                 | (req.op == Op.OP_STORE_HIT))):
+                                ((req.op == Op.OP_STORE_MISS) |
+                                 (req.op == Op.OP_STORE_HIT))):
                         sync += r1.wb.stb.eq(1)
                         comb += st_stbs_done.eq(0)
+                        sync += r1.store_way.eq(req.hit_way)
+                        sync += r1.store_row.eq(get_row(req.real_addr))
 
                         with m.If(req.op == Op.OP_STORE_HIT):
                             sync += r1.write_bram.eq(1)