missing sticky-overflow pass-through from middle stage

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index e801c9660a927d6fd8fd7432d578d5f372722fc5..07fb0180de7d73f627386a3d847dd56ded43aadd 100644 (file)
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -39,7 +39,9 @@ class ALUMainStage(PipeModBase):
             with m.Case(InternalOp.OP_XOR):
                 comb += self.o.o.eq(self.i.a ^ self.i.b)
 
+        ###### sticky overflow and context, both pass-through #####
 
+        comb += so.eq(self.i.so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m