imports and syntax errors fixed (found test_cache.py)

diff --git a/src/soc/minerva/cache.py b/src/soc/minerva/cache.py
index 57b7ba55146d4b0eb0fd4f9235815262c8cd26be..dabcb3a7743befc473199cb777de5541477d0ba2 100644 (file)
--- a/src/soc/minerva/cache.py
+++ b/src/soc/minerva/cache.py
@@ -73,8 +73,8 @@ class L1Cache(Elaboratable):
             hit = (way.tag == self.s2_addr.tag) & way.valid
             m.d.comb += way_hit.i[j].eq(hit)
 
+        rdata = ways[way_hit.o].data.word_select(self.s2_addr.offset, 32)
         m.d.comb += [
-            rdata = ways[way_hit.o].data.word_select(self.s2_addr.offset, 32)
             self.s2_miss.eq(way_hit.n),
             self.s2_rdata.eq(rdata)
         ]

diff --git a/src/soc/minerva/test/test_cache.py b/src/soc/minerva/test/test_cache.py
index c56a465d82077d0eab4608f61234b9af1c83ab0e..02e16e551741fe6f7ee6b80f4c68969111f9215d 100644 (file)
--- a/src/soc/minerva/test/test_cache.py
+++ b/src/soc/minerva/test/test_cache.py
@@ -1,9 +1,9 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Record
 from nmigen.utils import log2_int
-from nmutil.formaltest import *
-from nmigen.asserts import *
+from nmutil.formaltest import FHDLTestCase
+from nmigen.asserts import AnyConst, AnySeq, Assert, Assume, Past, Initial
 
-from ..cache import L1Cache
+from soc.minerva.cache import L1Cache
 
 
 class L1CacheSpec(Elaboratable):