expand Memory width to 64 and granularity to 16 in SRAM test

diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py
index dfebb3b8a9deab6eb2be915f0ae4adec7045be40..d1a6d63ae795889a566c25b1e1ad4a15a41b66d9 100644 (file)
--- a/src/soc/bus/test/test_sram_wishbone.py
+++ b/src/soc/bus/test/test_sram_wishbone.py
@@ -5,8 +5,8 @@ Bugs:
 from nmigen_soc.wishbone.sram import SRAM
 from nmigen import Memory, Signal, Module
 
-memory = Memory(width=32, depth=16)
-sram = SRAM(memory=memory,granularity=8)
+memory = Memory(width=64, depth=16)
+sram = SRAM(memory=memory, granularity=16)
 
 # valid wishbone signals include
 # sram.bus.adr