commented-out core.size and chip.size which would allow the

full core to fit

diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py
index 54b8dcc4b51dd2d6962b09842f4e153fc39111af..027853c449eacfae0019e920211966b0e71d8943 100644 (file)
--- a/experiments9/coriolis2/ioring.py
+++ b/experiments9/coriolis2/ioring.py
@@ -186,6 +186,10 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
           'pads.north'      : pn,
           'pads.west'       : pw,
             #[ 'f_3', 'f_2'       , 'p_clk_0', 'f_1'       , 'f_0'     ]
+          # core option (big, time-consuming)
+          #'core.size'       : ( l(26000), l(26000) ),
+          #'chip.size'       : ( l(30000), l(30000) ),
+          # no-core option (test_issuer but no actual core)
           'core.size'       : ( l(13000), l(13000) ),
           'chip.size'       : ( l(17000), l(17000) ),
           'chip.clockTree'  : True,