update ld/st test to see what is going on

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 702f85791dcd705d86b1f30368cfc5c4c52922f4..739f95fd2bdc0fdb2aa489320f08309f7c0bed69 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -154,18 +154,17 @@ class TestRunner(FHDLTestCase):
                 if self.funit == Function.LDST:
                     mem = l0.mem.mem
                     print ("before, init mem", mem.depth, mem.width, mem)
-                    for i in range(mem.depth//2):
-                        data = sim.mem.ld(i*16, 8)
-                        data1 = sim.mem.ld(i*16+8, 8)
-                        print ("init ", i, hex(data), hex(data1))
-                        yield mem._array[i].eq(data | (data1<<32))
+                    for i in range(mem.depth):
+                        data = sim.mem.ld(i*8, 8)
+                        print ("init ", i, hex(data))
+                        yield mem._array[i].eq(data)
                     yield Settle()
                     for k, v in sim.mem.mem.items():
                         print ("    %6x %016x" % (k, v))
                     print ("before, nmigen mem dump")
-                    for i in range(mem.depth//2):
+                    for i in range(mem.depth):
                         actual_mem = yield mem._array[i]
-                        print ("    %6i %016x" % (i*2, actual_mem))
+                        print ("    %6i %016x" % (i, actual_mem))
 
 
                 index = sim.pc.CIA.value//4
@@ -250,14 +249,12 @@ class TestRunner(FHDLTestCase):
                         for k, v in sim.mem.mem.items():
                             print ("    %6x %016x" % (k, v))
                         print ("nmigen mem dump")
-                        for i in range(mem.depth//2):
+                        for i in range(mem.depth):
                             actual_mem = yield mem._array[i]
-                            print ("    %6i %016x" % (i*2, actual_mem))
+                            print ("    %6i %016x" % (i, actual_mem))
 
-                        for i in range(mem.depth//2):
-                            data = sim.mem.ld(i*16, 8)
-                            data1 = sim.mem.ld(i*16+8, 8)
-                            expected_mem = (data | (data1<<32))
+                        for i in range(mem.depth):
+                            expected_mem = sim.mem.ld(i*8, 8)
                             actual_mem = yield mem._array[i]
                             self.assertEqual(expected_mem, actual_mem,
                                     "%s %d %x %x" % (code, i,

diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index 99ea01b29532eda736ea249914c7c47c006e9ea2..2c943c7ef11f35ca4a3141f294467379dbbd0b92 100644 (file)
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -68,8 +68,8 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[1] = 0x0004
         initial_regs[2] = 0x0008
         initial_mem = {0x0000: (0x5432123412345678, 8),
-                       0x0010: (0xabcdef0187654321, 8),
-                       0x0040: (0x1828384822324252, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
                         }
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)
@@ -84,8 +84,8 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[2] = 0x0008
         initial_regs[3] = 0x00ee
         initial_mem = {0x0000: (0x5432123412345678, 8),
-                       0x0010: (0xabcdef0187654321, 8),
-                       0x0040: (0x1828384822324252, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
                         }
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)
@@ -98,8 +98,8 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[2] = 0x0002
         initial_regs[3] = 0x15eb
         initial_mem = {0x0000: (0x5432123412345678, 8),
-                       0x0010: (0xabcdef0187654321, 8),
-                       0x0040: (0x1828384822324252, 8),
+                       0x0008: (0xabcdef0187654321, 8),
+                       0x0020: (0x1828384822324252, 8),
                         }
         self.run_tst_program(Program(lst), initial_regs,
                              initial_mem=initial_mem)