restore old Multi-in/out behaviour

diff --git a/src/ieee754/fpcommon/basedata.py b/src/ieee754/fpcommon/basedata.py
index 056ad44ccd634102bf13c06604cfab25977f73d7..197ae96f3f0fe07199471db7f0c382ae21e7c7ef 100644 (file)
--- a/src/ieee754/fpcommon/basedata.py
+++ b/src/ieee754/fpcommon/basedata.py
@@ -7,8 +7,9 @@ from ieee754.fpcommon.getop import FPPipeContext
 
 class FPBaseData:
 
-    def __init__(self, pspec, n_ops=2):
+    def __init__(self, pspec):
         width = pspec.width
+        n_ops = pspec.n_ops
         self.ctx = FPPipeContext(pspec)
         ops = []
         for i in range(n_ops):

diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index 4be6b0b5c56796364471997a9575f0ffbb76f878..22101b94d6e3c1f8d30b8a4f013f156cd1b6fe2d 100644 (file)
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -80,6 +80,6 @@ class FPMULMuxInOut(ReservationStations):
     def __init__(self, width, num_rows, op_wid=0):
         self.id_wid = num_bits(num_rows)
         self.op_wid = op_wid
-        self.pspec = PipelineSpec(width, self.id_wid, self.op_wid)
+        self.pspec = PipelineSpec(width, self.id_wid, self.op_wid, n_ops=2)
         self.alu = FPMULBasePipe(self.pspec)
         ReservationStations.__init__(self, num_rows)

diff --git a/src/ieee754/pipeline.py b/src/ieee754/pipeline.py
index 8a9c408ce1992d4f4c60e86190d0bec2c4c3238d..231eec6c30e1127a88310ba98c94c5c57375ed31 100644 (file)
--- a/src/ieee754/pipeline.py
+++ b/src/ieee754/pipeline.py
@@ -22,13 +22,15 @@ class PipelineSpec:
 
     """
 
-    def __init__(self, width, id_width, op_wid=0, opkls=None, pipekls=None):
+    def __init__(self, width, id_width, op_wid=0, opkls=None,
+                       pipekls=None, n_ops=2):
         """ Create a PipelineSpec. """
         self.width = width
         self.id_wid = id_width
         self.op_wid = op_wid
         self.opkls = opkls
         self.pipekls = pipekls or SimpleHandshakeRedir
+        self.n_ops = n_ops
         self.stage = None
         self.core_config = None
         self.fpformat = None

diff --git a/src/nmutil/multipipe.py b/src/nmutil/multipipe.py
index 725afc16552bba44a8f597c680c7c84ae6465541..c63d5e02e951dace5f3d2343584419d7ae4b29ee 100644 (file)
--- a/src/nmutil/multipipe.py
+++ b/src/nmutil/multipipe.py
@@ -208,15 +208,23 @@ class CombMultiOutPipeline(MultiOutControlBase):
         p_valid_i = Signal(reset_less=True)
         pv = Signal(reset_less=True)
         m.d.comb += p_valid_i.eq(self.p.valid_i_test)
-        m.d.comb += pv.eq(self.p.valid_i) #& self.n[muxid].ready_i)
+        #m.d.comb += pv.eq(self.p.valid_i) #& self.n[muxid].ready_i)
+        m.d.comb += pv.eq(self.p.valid_i & self.p.ready_o)
 
         # all outputs to next stages first initialised to zero (invalid)
         # the only output "active" is then selected by the muxid
         for i in range(len(self.n)):
             m.d.comb += self.n[i].valid_o.eq(0)
-        #with m.If(pv):
-        m.d.comb += self.n[muxid].valid_o.eq(pv)
-        m.d.comb += self.p.ready_o.eq(self.n[muxid].ready_i)
+        if self.routemask:
+            #with m.If(pv):
+            m.d.comb += self.n[muxid].valid_o.eq(pv)
+            m.d.comb += self.p.ready_o.eq(self.n[muxid].ready_i)
+        else:
+            data_valid = self.n[muxid].valid_o
+            m.d.comb += self.p.ready_o.eq(~data_valid | self.n[muxid].ready_i)
+            m.d.comb += data_valid.eq(p_valid_i | \
+                                    (~self.n[muxid].ready_i & data_valid))
+
 
         # send data on
         #with m.If(pv):
@@ -313,7 +321,10 @@ class CombMultiInPipeline(MultiInControlBase):
             m.d.comb += self.p[i].ready_o.eq(0)
         p = self.p[mid]
         maskedout = Signal(reset_less=True)
-        m.d.comb += maskedout.eq(p.mask_i & ~p.stop_i)
+        if hasattr(p, "mask_i"):
+            m.d.comb += maskedout.eq(p.mask_i & ~p.stop_i)
+        else:
+            m.d.comb += maskedout.eq(1)
         m.d.comb += p_valid_i[mid].eq(maskedout & self.p_mux.active)
         m.d.comb += self.p[mid].ready_o.eq(~data_valid[mid] | self.n.ready_i)
         m.d.comb += n_ready_in[mid].eq(nirn & data_valid[mid])
@@ -333,7 +344,10 @@ class CombMultiInPipeline(MultiInControlBase):
                 p = self.p[i]
                 vr = Signal(reset_less=True)
                 maskedout = Signal(reset_less=True)
-                m.d.comb += maskedout.eq(p.mask_i & ~p.stop_i)
+                if hasattr(p, "mask_i"):
+                    m.d.comb += maskedout.eq(p.mask_i & ~p.stop_i)
+                else:
+                    m.d.comb += maskedout.eq(1)
                 m.d.comb += vr.eq(maskedout.bool() & p.valid_i & p.ready_o)
                 #m.d.comb += vr.eq(p.valid_i & p.ready_o)
                 with m.If(vr):
@@ -347,7 +361,10 @@ class CombMultiInPipeline(MultiInControlBase):
                 p = self.p[i]
                 vr = Signal(reset_less=True)
                 maskedout = Signal(reset_less=True)
-                m.d.comb += maskedout.eq(p.mask_i & ~p.stop_i)
+                if hasattr(p, "mask_i"):
+                    m.d.comb += maskedout.eq(p.mask_i & ~p.stop_i)
+                else:
+                    m.d.comb += maskedout.eq(1)
                 m.d.comb += vr.eq(maskedout.bool() & p.valid_i & p.ready_o)
                 with m.If(vr):
                     m.d.comb += eq(r_data[i], self.p[i].data_i)