temp = []
for i in range(1, self.n_banks):
- temp_str = "periph{}".format(i)
+ temp_str = "periph%d" % i
temp.append(Record(name=temp_str, layout=io_layout))
self.periph_ports = Array(temp)
self.pad_port = Record(name="IOPad", layout=io_layout)
- self.iomux = IOMuxBlockSingle()
+ self.iomux = IOMuxBlockSingle(self.n_banks)
self.gpio = SimpleGPIO(self.wb_wordsize, self.n_gpios)
# This is probably easier to extend in future by bringing out WB
# interface to top-level
('gpio_wb__stb', 'in'),
('gpio_wb__we', 'in'),
('gpio_wb__adr[27:0]', 'in'),
- ('gpio_wb__dat_w[{}:0]'.format(wb_data_width-1), 'in'),
- ('gpio_wb__dat_r[{}:0]'.format(wb_data_width-1), 'out'),
+ ('gpio_wb__dat_w[%d:0]' % (wb_data_width-1), 'in'),
+ ('gpio_wb__dat_r[%d:0]' % (wb_data_width-1), 'out'),
('gpio_wb__ack', 'out'),
])
traces.append(wb_traces)
for bank in range(0, n_banks):
- temp_traces = ('Bank{}'.format(bank), [
- ('bank{}__i'.format(bank), 'in'),
- ('bank{}__o'.format(bank), 'out'),
- ('bank{}__oe'.format(bank), 'out')
+ temp_traces = ('Bank%d' % bank, [
+ ('bank%d__i' % bank, 'in'),
+ ('bank%d__o' % bank, 'out'),
+ ('bank%d__oe' % bank, 'out')
])
traces.append(temp_traces)
temp_traces = ('Misc', [
- ('bank[1:0]', 'in')
+ ('bank[%d:0]' % ((n_banks-1).bit_length()-1), 'in')
])
traces.append(temp_traces)
temp_traces = ('IO port to pad', [
pden = 1
outval = 0
bank = 0
+ yield from gpios.config("0", oe=1, ie=0, puen=0, pden=1, outval=0, bank=0)
+
+ yield from gpios.set_out("0", outval=1)
+
yield from gpios.config("0", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2)
+ yield dut.periph_ports[2].o.eq(1)
+ yield
+ yield dut.periph_ports[2].oe.eq(1)
+ yield
+ yield dut.pad_port.i.eq(1)
yield
- yield dut.periph_ports[0].o.eq(1)
- yield dut.periph_ports[0].oe.eq(1)
+ yield dut.pad_port.i.eq(0)
+
+
+
yield dut.pad_port.i.eq(1)
yield
- yield from gpios.config("0", oe=0, ie=0, puen=0, pden=1, outval=0, bank=0)
+ yield from gpios.config("0", oe=0, ie=1, puen=0, pden=1, outval=0, bank=0)
yield from gpios.rd_input("0")
print("Finished the 1-bit IO mux block test!")
self.wordsize = wordsize
self.n_gpio = n_gpio
self.n_rows = ceil(self.n_gpio / self.wordsize)
- print("SimpleGPIO: WB Data # of bytes: {0}, #GPIOs: {1}, Rows: {2}"
- .format(self.wordsize, self.n_gpio, self.n_rows))
+ print("SimpleGPIO: WB Data # of bytes: %d, #GPIOs: %d, Rows: %d" %
+ (self.wordsize, self.n_gpio, self.n_rows))
class Spec: pass
spec = Spec()
spec.addr_wid = 30
temp = []
for i in range(self.n_gpio):
- name = "gpio{}".format(i)
+ name = "gpio%d" % i
temp.append(Record(name=name, layout=gpio_layout))
self.gpio_ports = Array(temp)
yield gpio_set_in_pad(dut, gpio, pattern[pat])
yield
temp = yield from gpio_rd_input(dut, gpio)
- print("Pattern: {0}, Reading {1}".format(pattern[pat], temp))
+ print("Pattern: %x, Reading %x" % (pattern[pat], temp))
assert (temp == pattern[pat])
pat += 1
if pat == len(pattern):
pden = 0
if use_random:
bank = randint(0, (2**NUMBANKBITS)-1)
- print("Random bank select: {0:b}".format(bank))
+ print("Random bank select: %x" % (bank))
else:
bank = 3 # not special, chose for testing
def _parse_gpio_arg(self, gpio_str):
# TODO: No input checking!
- print("Given GPIO/range string: {}".format(gpio_str))
+ print("Given GPIO/range string: %s" % (gpio_str))
if gpio_str == "all":
start = 0
end = self.n_gpios
if start >= self.n_gpios:
raise Exception("GPIO must be less/equal to last GPIO.")
end = start + 1
- print("Parsed GPIOs {0} until {1}".format(start, end))
+ print("Parsed GPIOs %d until %d" % (start, end))
return start, end
# Take a combined word and update shadow reg's
io = (csr_byte >> self.shift_dict['io']) & 0x1
bank = (csr_byte >> self.shift_dict['bank']) & 0x3
- print("csr={0:x} | oe={1}, ie={2}, puen={3}, pden={4}, io={5}, bank={6}"
- .format(csr_byte, oe, ie, puen, pden, io, bank))
+ print("csr=%02x | oe=%d, ie=%d, puen=%d, pden=%d, io=%d, bank=%x" %
+ (csr_byte, oe, ie, puen, pden, io, bank))
self.shadow_csr[gpio].set(oe, ie, puen, pden, io, bank)
return oe, ie, puen, pden, io, bank
self.shadow_csr[gpio].set_out(outval)
if start == end:
- print("Setting GPIO{0} output to {1}".format(start, outval))
+ print("Setting GPIO %d output to %d" % (start, outval))
else:
- print("Setting GPIOs {0}-{1} output to {2}"
- .format(start, end-1, outval))
+ print("Setting GPIOs %d-%d output to %d" % (start, end-1, outval))
yield from self.wr(start, end)
read_in[i] = self.shadow_csr[curr_gpio].io
curr_gpio += 1
- print("GPIOs %d until %d, i=%s".format(start, end, read_in))
+ print("GPIOs %d until %d, i=%r" % (start, end, read_in))
return read_in
# TODO: There's probably a cleaner way to clear the bit...
for gpio in range(start, end):
old_in_val = yield self.dut.gpio_ports[gpio].i
print(old_in_val)
- print("GPIO{0} Previous i: {1:b} | New i: {2:b}"
- .format(gpio, old_in_val, in_val))
+ print("GPIO %d Prev i: %x | New i: %x" % (gpio, old_in_val, in_val))
yield self.dut.gpio_ports[gpio].i.eq(in_val)
yield # Allow one clk cycle to propagate